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| author | Ilya Tocar <ilya.tocar@intel.com> | 2014-10-21 09:51:49 +0000 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2014-10-21 11:51:49 +0200 |
| commit | 6afcac32436a1ac52c1fd41291d0d240bc870e6c (patch) | |
| tree | 6bc2abe9ae4470ee6b96fb59e860e6cb8fc0948e | |
| parent | 0f01f7406b842ab8ebcffb2907889f67c1d3d94e (diff) | |
| download | gcc-6afcac32436a1ac52c1fd41291d0d240bc870e6c.zip gcc-6afcac32436a1ac52c1fd41291d0d240bc870e6c.tar.gz gcc-6afcac32436a1ac52c1fd41291d0d240bc870e6c.tar.bz2 | |
i386.c (expand_vec_perm_1): Fix expand_vec_perm_palignr case.
* config/i386/i386.c (expand_vec_perm_1): Fix
expand_vec_perm_palignr case.
* config/i386/sse.md (<ssse3_avx2>_palignr<mode>_mask): Use
VI1_AVX512.
From-SVN: r216504
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 1 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 12 |
3 files changed, 14 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f7dedb5..87a4102 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2014-10-21 Ilya Tocar <ilya.tocar@intel.com> + + * config/i386/i386.c (expand_vec_perm_1): Fix + expand_vec_perm_palignr case. + * config/i386/sse.md (<ssse3_avx2>_palignr<mode>_mask): Use + VI1_AVX512. + 2014-10-21 Zhenqiang Chen <zhenqiang.chen@arm.com> * cfgloopanal.c (seq_cost): Delete. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 33b21f4..34273ca 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -43552,6 +43552,7 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d) /* Try the AVX2 vpalignr instruction. */ if (expand_vec_perm_palignr (d, true)) + return true; /* Try the AVX512F vpermi2 instructions. */ if (ix86_expand_vec_perm_vpermi2 (NULL_RTX, NULL_RTX, NULL_RTX, NULL_RTX, d)) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 8157045..a3f336f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -13716,14 +13716,14 @@ (set_attr "mode" "DI")]) (define_insn "<ssse3_avx2>_palignr<mode>_mask" - [(set (match_operand:VI1_AVX2 0 "register_operand" "=v") - (vec_merge:VI1_AVX2 - (unspec:VI1_AVX2 - [(match_operand:VI1_AVX2 1 "register_operand" "v") - (match_operand:VI1_AVX2 2 "nonimmediate_operand" "vm") + [(set (match_operand:VI1_AVX512 0 "register_operand" "=v") + (vec_merge:VI1_AVX512 + (unspec:VI1_AVX512 + [(match_operand:VI1_AVX512 1 "register_operand" "v") + (match_operand:VI1_AVX512 2 "nonimmediate_operand" "vm") (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")] UNSPEC_PALIGNR) - (match_operand:VI1_AVX2 4 "vector_move_operand" "0C") + (match_operand:VI1_AVX512 4 "vector_move_operand" "0C") (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))] "TARGET_AVX512BW && (<MODE_SIZE> == 64 || TARGET_AVX512VL)" { |