path: root/include/opcode/riscv-opc-extended.h

/* riscv-opcextended.h.  RISC-V extended instruction opcode.
   Copyright (C) 2021 Free Software Foundation, Inc.

   This file is part of GDB, GAS, and the GNU binutils.

   GDB, GAS, and the GNU binutils are free software; you can redistribute
   them and/or modify them under the terms of the GNU General Public
   License as published by the Free Software Foundation; either version
   3, or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING3. If not,
   see <http://www.gnu.org/licenses/>.  */

#ifndef RISCV_EXTENDED_ENCODING_H
#define RISCV_EXTENDED_ENCODING_H
/* ZFH instruction.  */
#define MATCH_FLH		0x1007
#define MASK_FLH		0x707f
#define MATCH_FSH		0x1027
#define MASK_FSH		0x707f
#define MATCH_FADD_H		0x4000053
#define MASK_FADD_H		0xfe00007f
#define MATCH_FSUB_H		0xc000053
#define MASK_FSUB_H		0xfe00007f
#define MATCH_FMUL_H		0x14000053
#define MASK_FMUL_H		0xfe00007f
#define MATCH_FDIV_H		0x1c000053
#define MASK_FDIV_H		0xfe00007f
#define MATCH_FSGNJ_H		0x24000053
#define MASK_FSGNJ_H		0xfe00707f
#define MATCH_FSGNJN_H		0x24001053
#define MASK_FSGNJN_H		0xfe00707f
#define MATCH_FSGNJX_H		0x24002053
#define MASK_FSGNJX_H		0xfe00707f
#define MATCH_FMIN_H		0x2c000053
#define MASK_FMIN_H 		0xfe00707f
#define MATCH_FMAX_H		0x2c001053
#define MASK_FMAX_H		0xfe00707f
#define MATCH_FCVT_S_H		0x40200053
#define MASK_FCVT_S_H		0xfff0007f
#define MATCH_FCVT_H_S		0x44000053
#define MASK_FCVT_H_S		0xfff0007f
#define MATCH_FCVT_D_H		0x42200053
#define MASK_FCVT_D_H		0xfff0007f
#define MATCH_FCVT_H_D		0x44100053
#define MASK_FCVT_H_D		0xfff0007f
#define MATCH_FCVT_Q_H		0x46200053
#define MASK_FCVT_Q_H		0xfff0007f
#define MATCH_FCVT_H_Q		0x44300053
#define MASK_FCVT_H_Q		0xfff0007f
#define MATCH_FSQRT_H		0x5c000053
#define MASK_FSQRT_H		0xfff0007f
#define MATCH_FLE_H		0xa4000053
#define MASK_FLE_H		0xfe00707f
#define MATCH_FLT_H		0xa4001053
#define MASK_FLT_H		0xfe00707f
#define MATCH_FEQ_H		0xa4002053
#define MASK_FEQ_H		0xfe00707f
#define MATCH_FCVT_W_H		0xc4000053
#define MASK_FCVT_W_H		0xfff0007f
#define MATCH_FCVT_WU_H		0xc4100053
#define MASK_FCVT_WU_H		0xfff0007f
#define MATCH_FCVT_L_H		0xc4200053
#define MASK_FCVT_L_H		0xfff0007f
#define MATCH_FCVT_LU_H		0xc4300053
#define MASK_FCVT_LU_H		0xfff0007f
#define MATCH_FMV_X_H		0xe4000053
#define MASK_FMV_X_H		0xfff0707f
#define MATCH_FCLASS_H		0xe4001053
#define MASK_FCLASS_H		0xfff0707f
#define MATCH_FCVT_H_W		0xd4000053
#define MASK_FCVT_H_W		0xfff0007f
#define MATCH_FCVT_H_WU		0xd4100053
#define MASK_FCVT_H_WU		0xfff0007f
#define MATCH_FCVT_H_L		0xd4200053
#define MASK_FCVT_H_L		0xfff0007f
#define MATCH_FCVT_H_LU		0xd4300053
#define MASK_FCVT_H_LU		0xfff0007f
#define MATCH_FMV_H_X		0xf4000053
#define MASK_FMV_H_X		0xfff0707f
#define MATCH_FMADD_H		0x4000043
#define MASK_FMADD_H		0x600007f
#define MATCH_FMSUB_H		0x4000047
#define MASK_FMSUB_H		0x600007f
#define MATCH_FNMSUB_H		0x400004b
#define MASK_FNMSUB_H		0x600007f
#define MATCH_FNMADD_H		0x400004f
#define MASK_FNMADD_H		0x600007f
/* RVV instruction.  */
#define MATCH_VSETVL		0x80007057
#define MASK_VSETVL		0xfe00707f
#define MATCH_VSETIVLI		0xc0007057
#define MASK_VSETIVLI		0xc000707f
#define MATCH_VSETVLI		0x00007057
#define MASK_VSETVLI		0x8000707f
#define MATCH_VLMV		0x02b00007
#define MASK_VLMV		0xfff0707f
#define MATCH_VSMV		0x02b00027
#define MASK_VSMV		0xfff0707f
#define MATCH_VLE8V		0x00000007
#define MASK_VLE8V		0xfdf0707f
#define MATCH_VLE16V		0x00005007
#define MASK_VLE16V		0xfdf0707f
#define MATCH_VLE32V		0x00006007
#define MASK_VLE32V		0xfdf0707f
#define MATCH_VLE64V		0x00007007
#define MASK_VLE64V		0xfdf0707f
#define MATCH_VSE8V		0x00000027
#define MASK_VSE8V		0xfdf0707f
#define MATCH_VSE16V		0x00005027
#define MASK_VSE16V		0xfdf0707f
#define MATCH_VSE32V		0x00006027
#define MASK_VSE32V		0xfdf0707f
#define MATCH_VSE64V		0x00007027
#define MASK_VSE64V		0xfdf0707f
#define MATCH_VLSE8V		0x08000007
#define MASK_VLSE8V		0xfc00707f
#define MATCH_VLSE16V		0x08005007
#define MASK_VLSE16V		0xfc00707f
#define MATCH_VLSE32V		0x08006007
#define MASK_VLSE32V		0xfc00707f
#define MATCH_VLSE64V		0x08007007
#define MASK_VLSE64V		0xfc00707f
#define MATCH_VSSE8V		0x08000027
#define MASK_VSSE8V		0xfc00707f
#define MATCH_VSSE16V		0x08005027
#define MASK_VSSE16V		0xfc00707f
#define MATCH_VSSE32V		0x08006027
#define MASK_VSSE32V		0xfc00707f
#define MATCH_VSSE64V		0x08007027
#define MASK_VSSE64V		0xfc00707f
#define MATCH_VLOXEI8V		0x0c000007
#define MASK_VLOXEI8V		0xfc00707f
#define MATCH_VLOXEI16V		0x0c005007
#define MASK_VLOXEI16V		0xfc00707f
#define MATCH_VLOXEI32V		0x0c006007
#define MASK_VLOXEI32V		0xfc00707f
#define MATCH_VLOXEI64V		0x0c007007
#define MASK_VLOXEI64V		0xfc00707f
#define MATCH_VSOXEI8V		0x0c000027
#define MASK_VSOXEI8V		0xfc00707f
#define MATCH_VSOXEI16V		0x0c005027
#define MASK_VSOXEI16V		0xfc00707f
#define MATCH_VSOXEI32V		0x0c006027
#define MASK_VSOXEI32V		0xfc00707f
#define MATCH_VSOXEI64V		0x0c007027
#define MASK_VSOXEI64V		0xfc00707f
#define MATCH_VLUXEI8V		0x04000007
#define MASK_VLUXEI8V		0xfc00707f
#define MATCH_VLUXEI16V		0x04005007
#define MASK_VLUXEI16V		0xfc00707f
#define MATCH_VLUXEI32V		0x04006007
#define MASK_VLUXEI32V		0xfc00707f
#define MATCH_VLUXEI64V		0x04007007
#define MASK_VLUXEI64V		0xfc00707f
#define MATCH_VSUXEI8V		0x04000027
#define MASK_VSUXEI8V		0xfc00707f
#define MATCH_VSUXEI16V		0x04005027
#define MASK_VSUXEI16V		0xfc00707f
#define MATCH_VSUXEI32V		0x04006027
#define MASK_VSUXEI32V		0xfc00707f
#define MATCH_VSUXEI64V		0x04007027
#define MASK_VSUXEI64V		0xfc00707f
#define MATCH_VLE8FFV		0x01000007
#define MASK_VLE8FFV		0xfdf0707f
#define MATCH_VLE16FFV		0x01005007
#define MASK_VLE16FFV		0xfdf0707f
#define MATCH_VLE32FFV		0x01006007
#define MASK_VLE32FFV		0xfdf0707f
#define MATCH_VLE64FFV		0x01007007
#define MASK_VLE64FFV		0xfdf0707f
#define MATCH_VLSEG2E8V		0x20000007
#define MASK_VLSEG2E8V		0xfdf0707f
#define MATCH_VSSEG2E8V		0x20000027
#define MASK_VSSEG2E8V		0xfdf0707f
#define MATCH_VLSEG3E8V		0x40000007
#define MASK_VLSEG3E8V		0xfdf0707f
#define MATCH_VSSEG3E8V		0x40000027
#define MASK_VSSEG3E8V		0xfdf0707f
#define MATCH_VLSEG4E8V		0x60000007
#define MASK_VLSEG4E8V		0xfdf0707f
#define MATCH_VSSEG4E8V		0x60000027
#define MASK_VSSEG4E8V		0xfdf0707f
#define MATCH_VLSEG5E8V		0x80000007
#define MASK_VLSEG5E8V		0xfdf0707f
#define MATCH_VSSEG5E8V		0x80000027
#define MASK_VSSEG5E8V		0xfdf0707f
#define MATCH_VLSEG6E8V		0xa0000007
#define MASK_VLSEG6E8V		0xfdf0707f
#define MATCH_VSSEG6E8V		0xa0000027
#define MASK_VSSEG6E8V		0xfdf0707f
#define MATCH_VLSEG7E8V		0xc0000007
#define MASK_VLSEG7E8V		0xfdf0707f
#define MATCH_VSSEG7E8V		0xc0000027
#define MASK_VSSEG7E8V		0xfdf0707f
#define MATCH_VLSEG8E8V		0xe0000007
#define MASK_VLSEG8E8V		0xfdf0707f
#define MATCH_VSSEG8E8V		0xe0000027
#define MASK_VSSEG8E8V		0xfdf0707f
#define MATCH_VLSEG2E16V	0x20005007
#define MASK_VLSEG2E16V		0xfdf0707f
#define MATCH_VSSEG2E16V	0x20005027
#define MASK_VSSEG2E16V		0xfdf0707f
#define MATCH_VLSEG3E16V	0x40005007
#define MASK_VLSEG3E16V		0xfdf0707f
#define MATCH_VSSEG3E16V	0x40005027
#define MASK_VSSEG3E16V		0xfdf0707f
#define MATCH_VLSEG4E16V	0x60005007
#define MASK_VLSEG4E16V		0xfdf0707f
#define MATCH_VSSEG4E16V	0x60005027
#define MASK_VSSEG4E16V		0xfdf0707f
#define MATCH_VLSEG5E16V	0x80005007
#define MASK_VLSEG5E16V		0xfdf0707f
#define MATCH_VSSEG5E16V	0x80005027
#define MASK_VSSEG5E16V		0xfdf0707f
#define MATCH_VLSEG6E16V	0xa0005007
#define MASK_VLSEG6E16V		0xfdf0707f
#define MATCH_VSSEG6E16V	0xa0005027
#define MASK_VSSEG6E16V		0xfdf0707f
#define MATCH_VLSEG7E16V	0xc0005007
#define MASK_VLSEG7E16V		0xfdf0707f
#define MATCH_VSSEG7E16V	0xc0005027
#define MASK_VSSEG7E16V		0xfdf0707f
#define MATCH_VLSEG8E16V	0xe0005007
#define MASK_VLSEG8E16V		0xfdf0707f
#define MATCH_VSSEG8E16V	0xe0005027
#define MASK_VSSEG8E16V		0xfdf0707f
#define MATCH_VLSEG2E32V	0x20006007
#define MASK_VLSEG2E32V		0xfdf0707f
#define MATCH_VSSEG2E32V	0x20006027
#define MASK_VSSEG2E32V		0xfdf0707f
#define MATCH_VLSEG3E32V	0x40006007
#define MASK_VLSEG3E32V		0xfdf0707f
#define MATCH_VSSEG3E32V	0x40006027
#define MASK_VSSEG3E32V		0xfdf0707f
#define MATCH_VLSEG4E32V	0x60006007
#define MASK_VLSEG4E32V		0xfdf0707f
#define MATCH_VSSEG4E32V	0x60006027
#define MASK_VSSEG4E32V		0xfdf0707f
#define MATCH_VLSEG5E32V	0x80006007
#define MASK_VLSEG5E32V		0xfdf0707f
#define MATCH_VSSEG5E32V	0x80006027
#define MASK_VSSEG5E32V		0xfdf0707f
#define MATCH_VLSEG6E32V	0xa0006007
#define MASK_VLSEG6E32V		0xfdf0707f
#define MATCH_VSSEG6E32V	0xa0006027
#define MASK_VSSEG6E32V		0xfdf0707f
#define MATCH_VLSEG7E32V	0xc0006007
#define MASK_VLSEG7E32V		0xfdf0707f
#define MATCH_VSSEG7E32V	0xc0006027
#define MASK_VSSEG7E32V		0xfdf0707f
#define MATCH_VLSEG8E32V	0xe0006007
#define MASK_VLSEG8E32V		0xfdf0707f
#define MATCH_VSSEG8E32V	0xe0006027
#define MASK_VSSEG8E32V		0xfdf0707f
#define MATCH_VLSEG2E64V	0x20007007
#define MASK_VLSEG2E64V		0xfdf0707f
#define MATCH_VSSEG2E64V	0x20007027
#define MASK_VSSEG2E64V		0xfdf0707f
#define MATCH_VLSEG3E64V	0x40007007
#define MASK_VLSEG3E64V		0xfdf0707f
#define MATCH_VSSEG3E64V	0x40007027
#define MASK_VSSEG3E64V		0xfdf0707f
#define MATCH_VLSEG4E64V	0x60007007
#define MASK_VLSEG4E64V		0xfdf0707f
#define MATCH_VSSEG4E64V	0x60007027
#define MASK_VSSEG4E64V		0xfdf0707f
#define MATCH_VLSEG5E64V	0x80007007
#define MASK_VLSEG5E64V		0xfdf0707f
#define MATCH_VSSEG5E64V	0x80007027
#define MASK_VSSEG5E64V		0xfdf0707f
#define MATCH_VLSEG6E64V	0xa0007007
#define MASK_VLSEG6E64V		0xfdf0707f
#define MATCH_VSSEG6E64V	0xa0007027
#define MASK_VSSEG6E64V		0xfdf0707f
#define MATCH_VLSEG7E64V	0xc0007007
#define MASK_VLSEG7E64V		0xfdf0707f
#define MATCH_VSSEG7E64V	0xc0007027
#define MASK_VSSEG7E64V		0xfdf0707f
#define MATCH_VLSEG8E64V	0xe0007007
#define MASK_VLSEG8E64V		0xfdf0707f
#define MATCH_VSSEG8E64V	0xe0007027
#define MASK_VSSEG8E64V		0xfdf0707f
#define MATCH_VLSSEG2E8V	0x28000007
#define MASK_VLSSEG2E8V		0xfc00707f
#define MATCH_VSSSEG2E8V	0x28000027
#define MASK_VSSSEG2E8V		0xfc00707f
#define MATCH_VLSSEG3E8V	0x48000007
#define MASK_VLSSEG3E8V		0xfc00707f
#define MATCH_VSSSEG3E8V	0x48000027
#define MASK_VSSSEG3E8V		0xfc00707f
#define MATCH_VLSSEG4E8V	0x68000007
#define MASK_VLSSEG4E8V		0xfc00707f
#define MATCH_VSSSEG4E8V	0x68000027
#define MASK_VSSSEG4E8V		0xfc00707f
#define MATCH_VLSSEG5E8V	0x88000007
#define MASK_VLSSEG5E8V		0xfc00707f
#define MATCH_VSSSEG5E8V	0x88000027
#define MASK_VSSSEG5E8V		0xfc00707f
#define MATCH_VLSSEG6E8V	0xa8000007
#define MASK_VLSSEG6E8V		0xfc00707f
#define MATCH_VSSSEG6E8V	0xa8000027
#define MASK_VSSSEG6E8V		0xfc00707f
#define MATCH_VLSSEG7E8V	0xc8000007
#define MASK_VLSSEG7E8V		0xfc00707f
#define MATCH_VSSSEG7E8V	0xc8000027
#define MASK_VSSSEG7E8V		0xfc00707f
#define MATCH_VLSSEG8E8V	0xe8000007
#define MASK_VLSSEG8E8V		0xfc00707f
#define MATCH_VSSSEG8E8V	0xe8000027
#define MASK_VSSSEG8E8V		0xfc00707f
#define MATCH_VLSSEG2E16V	0x28005007
#define MASK_VLSSEG2E16V	0xfc00707f
#define MATCH_VSSSEG2E16V	0x28005027
#define MASK_VSSSEG2E16V	0xfc00707f
#define MATCH_VLSSEG3E16V	0x48005007
#define MASK_VLSSEG3E16V	0xfc00707f
#define MATCH_VSSSEG3E16V	0x48005027
#define MASK_VSSSEG3E16V	0xfc00707f
#define MATCH_VLSSEG4E16V	0x68005007
#define MASK_VLSSEG4E16V	0xfc00707f
#define MATCH_VSSSEG4E16V	0x68005027
#define MASK_VSSSEG4E16V	0xfc00707f
#define MATCH_VLSSEG5E16V	0x88005007
#define MASK_VLSSEG5E16V	0xfc00707f
#define MATCH_VSSSEG5E16V	0x88005027
#define MASK_VSSSEG5E16V	0xfc00707f
#define MATCH_VLSSEG6E16V	0xa8005007
#define MASK_VLSSEG6E16V	0xfc00707f
#define MATCH_VSSSEG6E16V	0xa8005027
#define MASK_VSSSEG6E16V	0xfc00707f
#define MATCH_VLSSEG7E16V	0xc8005007
#define MASK_VLSSEG7E16V	0xfc00707f
#define MATCH_VSSSEG7E16V	0xc8005027
#define MASK_VSSSEG7E16V	0xfc00707f
#define MATCH_VLSSEG8E16V	0xe8005007
#define MASK_VLSSEG8E16V	0xfc00707f
#define MATCH_VSSSEG8E16V	0xe8005027
#define MASK_VSSSEG8E16V	0xfc00707f
#define MATCH_VLSSEG2E32V	0x28006007
#define MASK_VLSSEG2E32V	0xfc00707f
#define MATCH_VSSSEG2E32V	0x28006027
#define MASK_VSSSEG2E32V	0xfc00707f
#define MATCH_VLSSEG3E32V	0x48006007
#define MASK_VLSSEG3E32V	0xfc00707f
#define MATCH_VSSSEG3E32V	0x48006027
#define MASK_VSSSEG3E32V	0xfc00707f
#define MATCH_VLSSEG4E32V	0x68006007
#define MASK_VLSSEG4E32V	0xfc00707f
#define MATCH_VSSSEG4E32V	0x68006027
#define MASK_VSSSEG4E32V	0xfc00707f
#define MATCH_VLSSEG5E32V	0x88006007
#define MASK_VLSSEG5E32V	0xfc00707f
#define MATCH_VSSSEG5E32V	0x88006027
#define MASK_VSSSEG5E32V	0xfc00707f
#define MATCH_VLSSEG6E32V	0xa8006007
#define MASK_VLSSEG6E32V	0xfc00707f
#define MATCH_VSSSEG6E32V	0xa8006027
#define MASK_VSSSEG6E32V	0xfc00707f
#define MATCH_VLSSEG7E32V	0xc8006007
#define MASK_VLSSEG7E32V	0xfc00707f
#define MATCH_VSSSEG7E32V	0xc8006027
#define MASK_VSSSEG7E32V	0xfc00707f
#define MATCH_VLSSEG8E32V	0xe8006007
#define MASK_VLSSEG8E32V	0xfc00707f
#define MATCH_VSSSEG8E32V	0xe8006027
#define MASK_VSSSEG8E32V	0xfc00707f
#define MATCH_VLSSEG2E64V	0x28007007
#define MASK_VLSSEG2E64V	0xfc00707f
#define MATCH_VSSSEG2E64V	0x28007027
#define MASK_VSSSEG2E64V	0xfc00707f
#define MATCH_VLSSEG3E64V	0x48007007
#define MASK_VLSSEG3E64V	0xfc00707f
#define MATCH_VSSSEG3E64V	0x48007027
#define MASK_VSSSEG3E64V	0xfc00707f
#define MATCH_VLSSEG4E64V	0x68007007
#define MASK_VLSSEG4E64V	0xfc00707f
#define MATCH_VSSSEG4E64V	0x68007027
#define MASK_VSSSEG4E64V	0xfc00707f
#define MATCH_VLSSEG5E64V	0x88007007
#define MASK_VLSSEG5E64V	0xfc00707f
#define MATCH_VSSSEG5E64V	0x88007027
#define MASK_VSSSEG5E64V	0xfc00707f
#define MATCH_VLSSEG6E64V	0xa8007007
#define MASK_VLSSEG6E64V	0xfc00707f
#define MATCH_VSSSEG6E64V	0xa8007027
#define MASK_VSSSEG6E64V	0xfc00707f
#define MATCH_VLSSEG7E64V	0xc8007007
#define MASK_VLSSEG7E64V	0xfc00707f
#define MATCH_VSSSEG7E64V	0xc8007027
#define MASK_VSSSEG7E64V	0xfc00707f
#define MATCH_VLSSEG8E64V	0xe8007007
#define MASK_VLSSEG8E64V	0xfc00707f
#define MATCH_VSSSEG8E64V	0xe8007027
#define MASK_VSSSEG8E64V	0xfc00707f
#define MATCH_VLOXSEG2EI8V	0x2c000007
#define MASK_VLOXSEG2EI8V	0xfc00707f
#define MATCH_VSOXSEG2EI8V	0x2c000027
#define MASK_VSOXSEG2EI8V	0xfc00707f
#define MATCH_VLOXSEG3EI8V	0x4c000007
#define MASK_VLOXSEG3EI8V	0xfc00707f
#define MATCH_VSOXSEG3EI8V	0x4c000027
#define MASK_VSOXSEG3EI8V	0xfc00707f
#define MATCH_VLOXSEG4EI8V	0x6c000007
#define MASK_VLOXSEG4EI8V	0xfc00707f
#define MATCH_VSOXSEG4EI8V	0x6c000027
#define MASK_VSOXSEG4EI8V	0xfc00707f
#define MATCH_VLOXSEG5EI8V	0x8c000007
#define MASK_VLOXSEG5EI8V	0xfc00707f
#define MATCH_VSOXSEG5EI8V	0x8c000027
#define MASK_VSOXSEG5EI8V	0xfc00707f
#define MATCH_VLOXSEG6EI8V	0xac000007
#define MASK_VLOXSEG6EI8V	0xfc00707f
#define MATCH_VSOXSEG6EI8V	0xac000027
#define MASK_VSOXSEG6EI8V	0xfc00707f
#define MATCH_VLOXSEG7EI8V	0xcc000007
#define MASK_VLOXSEG7EI8V	0xfc00707f
#define MATCH_VSOXSEG7EI8V	0xcc000027
#define MASK_VSOXSEG7EI8V	0xfc00707f
#define MATCH_VLOXSEG8EI8V	0xec000007
#define MASK_VLOXSEG8EI8V	0xfc00707f
#define MATCH_VSOXSEG8EI8V	0xec000027
#define MASK_VSOXSEG8EI8V	0xfc00707f
#define MATCH_VLUXSEG2EI8V	0x24000007
#define MASK_VLUXSEG2EI8V	0xfc00707f
#define MATCH_VSUXSEG2EI8V	0x24000027
#define MASK_VSUXSEG2EI8V	0xfc00707f
#define MATCH_VLUXSEG3EI8V	0x44000007
#define MASK_VLUXSEG3EI8V	0xfc00707f
#define MATCH_VSUXSEG3EI8V	0x44000027
#define MASK_VSUXSEG3EI8V	0xfc00707f
#define MATCH_VLUXSEG4EI8V	0x64000007
#define MASK_VLUXSEG4EI8V	0xfc00707f
#define MATCH_VSUXSEG4EI8V	0x64000027
#define MASK_VSUXSEG4EI8V	0xfc00707f
#define MATCH_VLUXSEG5EI8V	0x84000007
#define MASK_VLUXSEG5EI8V	0xfc00707f
#define MATCH_VSUXSEG5EI8V	0x84000027
#define MASK_VSUXSEG5EI8V	0xfc00707f
#define MATCH_VLUXSEG6EI8V	0xa4000007
#define MASK_VLUXSEG6EI8V	0xfc00707f
#define MATCH_VSUXSEG6EI8V	0xa4000027
#define MASK_VSUXSEG6EI8V	0xfc00707f
#define MATCH_VLUXSEG7EI8V	0xc4000007
#define MASK_VLUXSEG7EI8V	0xfc00707f
#define MATCH_VSUXSEG7EI8V	0xc4000027
#define MASK_VSUXSEG7EI8V	0xfc00707f
#define MATCH_VLUXSEG8EI8V	0xe4000007
#define MASK_VLUXSEG8EI8V	0xfc00707f
#define MATCH_VSUXSEG8EI8V	0xe4000027
#define MASK_VSUXSEG8EI8V	0xfc00707f
#define MATCH_VLOXSEG2EI16V	0x2c005007
#define MASK_VLOXSEG2EI16V	0xfc00707f
#define MATCH_VSOXSEG2EI16V	0x2c005027
#define MASK_VSOXSEG2EI16V	0xfc00707f
#define MATCH_VLOXSEG3EI16V	0x4c005007
#define MASK_VLOXSEG3EI16V	0xfc00707f
#define MATCH_VSOXSEG3EI16V	0x4c005027
#define MASK_VSOXSEG3EI16V	0xfc00707f
#define MATCH_VLOXSEG4EI16V	0x6c005007
#define MASK_VLOXSEG4EI16V	0xfc00707f
#define MATCH_VSOXSEG4EI16V	0x6c005027
#define MASK_VSOXSEG4EI16V	0xfc00707f
#define MATCH_VLOXSEG5EI16V	0x8c005007
#define MASK_VLOXSEG5EI16V	0xfc00707f
#define MATCH_VSOXSEG5EI16V	0x8c005027
#define MASK_VSOXSEG5EI16V	0xfc00707f
#define MATCH_VLOXSEG6EI16V	0xac005007
#define MASK_VLOXSEG6EI16V	0xfc00707f
#define MATCH_VSOXSEG6EI16V	0xac005027
#define MASK_VSOXSEG6EI16V	0xfc00707f
#define MATCH_VLOXSEG7EI16V	0xcc005007
#define MASK_VLOXSEG7EI16V	0xfc00707f
#define MATCH_VSOXSEG7EI16V	0xcc005027
#define MASK_VSOXSEG7EI16V	0xfc00707f
#define MATCH_VLOXSEG8EI16V	0xec005007
#define MASK_VLOXSEG8EI16V	0xfc00707f
#define MATCH_VSOXSEG8EI16V	0xec005027
#define MASK_VSOXSEG8EI16V	0xfc00707f
#define MATCH_VLUXSEG2EI16V	0x24005007
#define MASK_VLUXSEG2EI16V	0xfc00707f
#define MATCH_VSUXSEG2EI16V	0x24005027
#define MASK_VSUXSEG2EI16V	0xfc00707f
#define MATCH_VLUXSEG3EI16V	0x44005007
#define MASK_VLUXSEG3EI16V	0xfc00707f
#define MATCH_VSUXSEG3EI16V	0x44005027
#define MASK_VSUXSEG3EI16V	0xfc00707f
#define MATCH_VLUXSEG4EI16V	0x64005007
#define MASK_VLUXSEG4EI16V	0xfc00707f
#define MATCH_VSUXSEG4EI16V	0x64005027
#define MASK_VSUXSEG4EI16V	0xfc00707f
#define MATCH_VLUXSEG5EI16V	0x84005007
#define MASK_VLUXSEG5EI16V	0xfc00707f
#define MATCH_VSUXSEG5EI16V	0x84005027
#define MASK_VSUXSEG5EI16V	0xfc00707f
#define MATCH_VLUXSEG6EI16V	0xa4005007
#define MASK_VLUXSEG6EI16V	0xfc00707f
#define MATCH_VSUXSEG6EI16V	0xa4005027
#define MASK_VSUXSEG6EI16V	0xfc00707f
#define MATCH_VLUXSEG7EI16V	0xc4005007
#define MASK_VLUXSEG7EI16V	0xfc00707f
#define MATCH_VSUXSEG7EI16V	0xc4005027
#define MASK_VSUXSEG7EI16V	0xfc00707f
#define MATCH_VLUXSEG8EI16V	0xe4005007
#define MASK_VLUXSEG8EI16V	0xfc00707f
#define MATCH_VSUXSEG8EI16V	0xe4005027
#define MASK_VSUXSEG8EI16V	0xfc00707f
#define MATCH_VLOXSEG2EI32V	0x2c006007
#define MASK_VLOXSEG2EI32V	0xfc00707f
#define MATCH_VSOXSEG2EI32V	0x2c006027
#define MASK_VSOXSEG2EI32V	0xfc00707f
#define MATCH_VLOXSEG3EI32V	0x4c006007
#define MASK_VLOXSEG3EI32V	0xfc00707f
#define MATCH_VSOXSEG3EI32V	0x4c006027
#define MASK_VSOXSEG3EI32V	0xfc00707f
#define MATCH_VLOXSEG4EI32V	0x6c006007
#define MASK_VLOXSEG4EI32V	0xfc00707f
#define MATCH_VSOXSEG4EI32V	0x6c006027
#define MASK_VSOXSEG4EI32V	0xfc00707f
#define MATCH_VLOXSEG5EI32V	0x8c006007
#define MASK_VLOXSEG5EI32V	0xfc00707f
#define MATCH_VSOXSEG5EI32V	0x8c006027
#define MASK_VSOXSEG5EI32V	0xfc00707f
#define MATCH_VLOXSEG6EI32V	0xac006007
#define MASK_VLOXSEG6EI32V	0xfc00707f
#define MATCH_VSOXSEG6EI32V	0xac006027
#define MASK_VSOXSEG6EI32V	0xfc00707f
#define MATCH_VLOXSEG7EI32V	0xcc006007
#define MASK_VLOXSEG7EI32V	0xfc00707f
#define MATCH_VSOXSEG7EI32V	0xcc006027
#define MASK_VSOXSEG7EI32V	0xfc00707f
#define MATCH_VLOXSEG8EI32V	0xec006007
#define MASK_VLOXSEG8EI32V	0xfc00707f
#define MATCH_VSOXSEG8EI32V	0xec006027
#define MASK_VSOXSEG8EI32V	0xfc00707f
#define MATCH_VLUXSEG2EI32V	0x24006007
#define MASK_VLUXSEG2EI32V	0xfc00707f
#define MATCH_VSUXSEG2EI32V	0x24006027
#define MASK_VSUXSEG2EI32V	0xfc00707f
#define MATCH_VLUXSEG3EI32V	0x44006007
#define MASK_VLUXSEG3EI32V	0xfc00707f
#define MATCH_VSUXSEG3EI32V	0x44006027
#define MASK_VSUXSEG3EI32V	0xfc00707f
#define MATCH_VLUXSEG4EI32V	0x64006007
#define MASK_VLUXSEG4EI32V	0xfc00707f
#define MATCH_VSUXSEG4EI32V	0x64006027
#define MASK_VSUXSEG4EI32V	0xfc00707f
#define MATCH_VLUXSEG5EI32V	0x84006007
#define MASK_VLUXSEG5EI32V	0xfc00707f
#define MATCH_VSUXSEG5EI32V	0x84006027
#define MASK_VSUXSEG5EI32V	0xfc00707f
#define MATCH_VLUXSEG6EI32V	0xa4006007
#define MASK_VLUXSEG6EI32V	0xfc00707f
#define MATCH_VSUXSEG6EI32V	0xa4006027
#define MASK_VSUXSEG6EI32V	0xfc00707f
#define MATCH_VLUXSEG7EI32V	0xc4006007
#define MASK_VLUXSEG7EI32V	0xfc00707f
#define MATCH_VSUXSEG7EI32V	0xc4006027
#define MASK_VSUXSEG7EI32V	0xfc00707f
#define MATCH_VLUXSEG8EI32V	0xe4006007
#define MASK_VLUXSEG8EI32V	0xfc00707f
#define MATCH_VSUXSEG8EI32V	0xe4006027
#define MASK_VSUXSEG8EI32V	0xfc00707f
#define MATCH_VLOXSEG2EI64V	0x2c007007
#define MASK_VLOXSEG2EI64V	0xfc00707f
#define MATCH_VSOXSEG2EI64V	0x2c007027
#define MASK_VSOXSEG2EI64V	0xfc00707f
#define MATCH_VLOXSEG3EI64V	0x4c007007
#define MASK_VLOXSEG3EI64V	0xfc00707f
#define MATCH_VSOXSEG3EI64V	0x4c007027
#define MASK_VSOXSEG3EI64V	0xfc00707f
#define MATCH_VLOXSEG4EI64V	0x6c007007
#define MASK_VLOXSEG4EI64V	0xfc00707f
#define MATCH_VSOXSEG4EI64V	0x6c007027
#define MASK_VSOXSEG4EI64V	0xfc00707f
#define MATCH_VLOXSEG5EI64V	0x8c007007
#define MASK_VLOXSEG5EI64V	0xfc00707f
#define MATCH_VSOXSEG5EI64V	0x8c007027
#define MASK_VSOXSEG5EI64V	0xfc00707f
#define MATCH_VLOXSEG6EI64V	0xac007007
#define MASK_VLOXSEG6EI64V	0xfc00707f
#define MATCH_VSOXSEG6EI64V	0xac007027
#define MASK_VSOXSEG6EI64V	0xfc00707f
#define MATCH_VLOXSEG7EI64V	0xcc007007
#define MASK_VLOXSEG7EI64V	0xfc00707f
#define MATCH_VSOXSEG7EI64V	0xcc007027
#define MASK_VSOXSEG7EI64V	0xfc00707f
#define MATCH_VLOXSEG8EI64V	0xec007007
#define MASK_VLOXSEG8EI64V	0xfc00707f
#define MATCH_VSOXSEG8EI64V	0xec007027
#define MASK_VSOXSEG8EI64V	0xfc00707f
#define MATCH_VLUXSEG2EI64V	0x24007007
#define MASK_VLUXSEG2EI64V	0xfc00707f
#define MATCH_VSUXSEG2EI64V	0x24007027
#define MASK_VSUXSEG2EI64V	0xfc00707f
#define MATCH_VLUXSEG3EI64V	0x44007007
#define MASK_VLUXSEG3EI64V	0xfc00707f
#define MATCH_VSUXSEG3EI64V	0x44007027
#define MASK_VSUXSEG3EI64V	0xfc00707f
#define MATCH_VLUXSEG4EI64V	0x64007007
#define MASK_VLUXSEG4EI64V	0xfc00707f
#define MATCH_VSUXSEG4EI64V	0x64007027
#define MASK_VSUXSEG4EI64V	0xfc00707f
#define MATCH_VLUXSEG5EI64V	0x84007007
#define MASK_VLUXSEG5EI64V	0xfc00707f
#define MATCH_VSUXSEG5EI64V	0x84007027
#define MASK_VSUXSEG5EI64V	0xfc00707f
#define MATCH_VLUXSEG6EI64V	0xa4007007
#define MASK_VLUXSEG6EI64V	0xfc00707f
#define MATCH_VSUXSEG6EI64V	0xa4007027
#define MASK_VSUXSEG6EI64V	0xfc00707f
#define MATCH_VLUXSEG7EI64V	0xc4007007
#define MASK_VLUXSEG7EI64V	0xfc00707f
#define MATCH_VSUXSEG7EI64V	0xc4007027
#define MASK_VSUXSEG7EI64V	0xfc00707f
#define MATCH_VLUXSEG8EI64V	0xe4007007
#define MASK_VLUXSEG8EI64V	0xfc00707f
#define MATCH_VSUXSEG8EI64V	0xe4007027
#define MASK_VSUXSEG8EI64V	0xfc00707f
#define MATCH_VLSEG2E8FFV	0x21000007
#define MASK_VLSEG2E8FFV	0xfdf0707f
#define MATCH_VLSEG3E8FFV	0x41000007
#define MASK_VLSEG3E8FFV	0xfdf0707f
#define MATCH_VLSEG4E8FFV	0x61000007
#define MASK_VLSEG4E8FFV	0xfdf0707f
#define MATCH_VLSEG5E8FFV	0x81000007
#define MASK_VLSEG5E8FFV	0xfdf0707f
#define MATCH_VLSEG6E8FFV	0xa1000007
#define MASK_VLSEG6E8FFV	0xfdf0707f
#define MATCH_VLSEG7E8FFV	0xc1000007
#define MASK_VLSEG7E8FFV	0xfdf0707f
#define MATCH_VLSEG8E8FFV	0xe1000007
#define MASK_VLSEG8E8FFV	0xfdf0707f
#define MATCH_VLSEG2E16FFV	0x21005007
#define MASK_VLSEG2E16FFV	0xfdf0707f
#define MATCH_VLSEG3E16FFV	0x41005007
#define MASK_VLSEG3E16FFV	0xfdf0707f
#define MATCH_VLSEG4E16FFV	0x61005007
#define MASK_VLSEG4E16FFV	0xfdf0707f
#define MATCH_VLSEG5E16FFV	0x81005007
#define MASK_VLSEG5E16FFV	0xfdf0707f
#define MATCH_VLSEG6E16FFV	0xa1005007
#define MASK_VLSEG6E16FFV	0xfdf0707f
#define MATCH_VLSEG7E16FFV	0xc1005007
#define MASK_VLSEG7E16FFV	0xfdf0707f
#define MATCH_VLSEG8E16FFV	0xe1005007
#define MASK_VLSEG8E16FFV	0xfdf0707f
#define MATCH_VLSEG2E32FFV	0x21006007
#define MASK_VLSEG2E32FFV	0xfdf0707f
#define MATCH_VLSEG3E32FFV	0x41006007
#define MASK_VLSEG3E32FFV	0xfdf0707f
#define MATCH_VLSEG4E32FFV	0x61006007
#define MASK_VLSEG4E32FFV	0xfdf0707f
#define MATCH_VLSEG5E32FFV	0x81006007
#define MASK_VLSEG5E32FFV	0xfdf0707f
#define MATCH_VLSEG6E32FFV	0xa1006007
#define MASK_VLSEG6E32FFV	0xfdf0707f
#define MATCH_VLSEG7E32FFV	0xc1006007
#define MASK_VLSEG7E32FFV	0xfdf0707f
#define MATCH_VLSEG8E32FFV	0xe1006007
#define MASK_VLSEG8E32FFV	0xfdf0707f
#define MATCH_VLSEG2E64FFV	0x21007007
#define MASK_VLSEG2E64FFV	0xfdf0707f
#define MATCH_VLSEG3E64FFV	0x41007007
#define MASK_VLSEG3E64FFV	0xfdf0707f
#define MATCH_VLSEG4E64FFV	0x61007007
#define MASK_VLSEG4E64FFV	0xfdf0707f
#define MATCH_VLSEG5E64FFV	0x81007007
#define MASK_VLSEG5E64FFV	0xfdf0707f
#define MATCH_VLSEG6E64FFV	0xa1007007
#define MASK_VLSEG6E64FFV	0xfdf0707f
#define MATCH_VLSEG7E64FFV	0xc1007007
#define MASK_VLSEG7E64FFV	0xfdf0707f
#define MATCH_VLSEG8E64FFV	0xe1007007
#define MASK_VLSEG8E64FFV	0xfdf0707f
#define MATCH_VL1RE8V		0x02800007
#define MASK_VL1RE8V		0xfff0707f
#define MATCH_VL1RE16V		0x02805007
#define MASK_VL1RE16V		0xfff0707f
#define MATCH_VL1RE32V		0x02806007
#define MASK_VL1RE32V		0xfff0707f
#define MATCH_VL1RE64V		0x02807007
#define MASK_VL1RE64V		0xfff0707f
#define MATCH_VL2RE8V		0x22800007
#define MASK_VL2RE8V		0xfff0707f
#define MATCH_VL2RE16V		0x22805007
#define MASK_VL2RE16V		0xfff0707f
#define MATCH_VL2RE32V		0x22806007
#define MASK_VL2RE32V		0xfff0707f
#define MATCH_VL2RE64V		0x22807007
#define MASK_VL2RE64V		0xfff0707f
#define MATCH_VL4RE8V		0x62800007
#define MASK_VL4RE8V		0xfff0707f
#define MATCH_VL4RE16V		0x62805007
#define MASK_VL4RE16V		0xfff0707f
#define MATCH_VL4RE32V		0x62806007
#define MASK_VL4RE32V		0xfff0707f
#define MATCH_VL4RE64V		0x62807007
#define MASK_VL4RE64V		0xfff0707f
#define MATCH_VL8RE8V		0xe2800007
#define MASK_VL8RE8V		0xfff0707f
#define MATCH_VL8RE16V		0xe2805007
#define MASK_VL8RE16V		0xfff0707f
#define MATCH_VL8RE32V		0xe2806007
#define MASK_VL8RE32V		0xfff0707f
#define MATCH_VL8RE64V		0xe2807007
#define MASK_VL8RE64V		0xfff0707f
#define MATCH_VS1RV		0x02800027
#define MASK_VS1RV		0xfff0707f
#define MATCH_VS2RV		0x22800027
#define MASK_VS2RV		0xfff0707f
#define MATCH_VS4RV		0x62800027
#define MASK_VS4RV		0xfff0707f
#define MATCH_VS8RV		0xe2800027
#define MASK_VS8RV		0xfff0707f
#define MATCH_VAMOADDEI8V	0x0000002f
#define MASK_VAMOADDEI8V	0xf800707f
#define MATCH_VAMOSWAPEI8V	0x0800002f
#define MASK_VAMOSWAPEI8V	0xf800707f
#define MATCH_VAMOXOREI8V	0x2000002f
#define MASK_VAMOXOREI8V	0xf800707f
#define MATCH_VAMOANDEI8V	0x6000002f
#define MASK_VAMOANDEI8V	0xf800707f
#define MATCH_VAMOOREI8V	0x4000002f
#define MASK_VAMOOREI8V		0xf800707f
#define MATCH_VAMOMINEI8V	0x8000002f
#define MASK_VAMOMINEI8V	0xf800707f
#define MATCH_VAMOMAXEI8V	0xa000002f
#define MASK_VAMOMAXEI8V	0xf800707f
#define MATCH_VAMOMINUEI8V	0xc000002f
#define MASK_VAMOMINUEI8V	0xf800707f
#define MATCH_VAMOMAXUEI8V	0xe000002f
#define MASK_VAMOMAXUEI8V	0xf800707f
#define MATCH_VAMOADDEI16V	0x0000502f
#define MASK_VAMOADDEI16V	0xf800707f
#define MATCH_VAMOSWAPEI16V	0x0800502f
#define MASK_VAMOSWAPEI16V	0xf800707f
#define MATCH_VAMOXOREI16V	0x2000502f
#define MASK_VAMOXOREI16V	0xf800707f
#define MATCH_VAMOANDEI16V	0x6000502f
#define MASK_VAMOANDEI16V	0xf800707f
#define MATCH_VAMOOREI16V	0x4000502f
#define MASK_VAMOOREI16V	0xf800707f
#define MATCH_VAMOMINEI16V	0x8000502f
#define MASK_VAMOMINEI16V	0xf800707f
#define MATCH_VAMOMAXEI16V	0xa000502f
#define MASK_VAMOMAXEI16V	0xf800707f
#define MATCH_VAMOMINUEI16V	0xc000502f
#define MASK_VAMOMINUEI16V	0xf800707f
#define MATCH_VAMOMAXUEI16V	0xe000502f
#define MASK_VAMOMAXUEI16V	0xf800707f
#define MATCH_VAMOADDEI32V	0x0000602f
#define MASK_VAMOADDEI32V	0xf800707f
#define MATCH_VAMOSWAPEI32V	0x0800602f
#define MASK_VAMOSWAPEI32V	0xf800707f
#define MATCH_VAMOXOREI32V	0x2000602f
#define MASK_VAMOXOREI32V	0xf800707f
#define MATCH_VAMOANDEI32V	0x6000602f
#define MASK_VAMOANDEI32V	0xf800707f
#define MATCH_VAMOOREI32V	0x4000602f
#define MASK_VAMOOREI32V	0xf800707f
#define MATCH_VAMOMINEI32V	0x8000602f
#define MASK_VAMOMINEI32V	0xf800707f
#define MATCH_VAMOMAXEI32V	0xa000602f
#define MASK_VAMOMAXEI32V	0xf800707f
#define MATCH_VAMOMINUEI32V	0xc000602f
#define MASK_VAMOMINUEI32V	0xf800707f
#define MATCH_VAMOMAXUEI32V	0xe000602f
#define MASK_VAMOMAXUEI32V	0xf800707f
#define MATCH_VAMOADDEI64V	0x0000702f
#define MASK_VAMOADDEI64V	0xf800707f
#define MATCH_VAMOSWAPEI64V	0x0800702f
#define MASK_VAMOSWAPEI64V	0xf800707f
#define MATCH_VAMOXOREI64V	0x2000702f
#define MASK_VAMOXOREI64V	0xf800707f
#define MATCH_VAMOANDEI64V	0x6000702f
#define MASK_VAMOANDEI64V	0xf800707f
#define MATCH_VAMOOREI64V	0x4000702f
#define MASK_VAMOOREI64V	0xf800707f
#define MATCH_VAMOMINEI64V	0x8000702f
#define MASK_VAMOMINEI64V	0xf800707f
#define MATCH_VAMOMAXEI64V	0xa000702f
#define MASK_VAMOMAXEI64V	0xf800707f
#define MATCH_VAMOMINUEI64V	0xc000702f
#define MASK_VAMOMINUEI64V	0xf800707f
#define MATCH_VAMOMAXUEI64V	0xe000702f
#define MASK_VAMOMAXUEI64V	0xf800707f
#define MATCH_VADDVV		0x00000057
#define MASK_VADDVV		0xfc00707f
#define MATCH_VADDVX		0x00004057
#define MASK_VADDVX		0xfc00707f
#define MATCH_VADDVI		0x00003057
#define MASK_VADDVI		0xfc00707f
#define MATCH_VSUBVV		0x08000057
#define MASK_VSUBVV		0xfc00707f
#define MATCH_VSUBVX		0x08004057
#define MASK_VSUBVX		0xfc00707f
#define MATCH_VRSUBVX		0x0c004057
#define MASK_VRSUBVX		0xfc00707f
#define MATCH_VRSUBVI		0x0c003057
#define MASK_VRSUBVI		0xfc00707f
#define MATCH_VWCVTXXV		0xc4006057
#define MASK_VWCVTXXV		0xfc0ff07f
#define MATCH_VWCVTUXXV		0xc0006057
#define MASK_VWCVTUXXV		0xfc0ff07f
#define MATCH_VWADDVV		0xc4002057
#define MASK_VWADDVV		0xfc00707f
#define MATCH_VWADDVX		0xc4006057
#define MASK_VWADDVX		0xfc00707f
#define MATCH_VWSUBVV		0xcc002057
#define MASK_VWSUBVV		0xfc00707f
#define MATCH_VWSUBVX		0xcc006057
#define MASK_VWSUBVX		0xfc00707f
#define MATCH_VWADDWV		0xd4002057
#define MASK_VWADDWV		0xfc00707f
#define MATCH_VWADDWX		0xd4006057
#define MASK_VWADDWX		0xfc00707f
#define MATCH_VWSUBWV		0xdc002057
#define MASK_VWSUBWV		0xfc00707f
#define MATCH_VWSUBWX		0xdc006057
#define MASK_VWSUBWX		0xfc00707f
#define MATCH_VWADDUVV		0xc0002057
#define MASK_VWADDUVV		0xfc00707f
#define MATCH_VWADDUVX		0xc0006057
#define MASK_VWADDUVX		0xfc00707f
#define MATCH_VWSUBUVV		0xc8002057
#define MASK_VWSUBUVV		0xfc00707f
#define MATCH_VWSUBUVX		0xc8006057
#define MASK_VWSUBUVX		0xfc00707f
#define MATCH_VWADDUWV		0xd0002057
#define MASK_VWADDUWV		0xfc00707f
#define MATCH_VWADDUWX		0xd0006057
#define MASK_VWADDUWX		0xfc00707f
#define MATCH_VWSUBUWV		0xd8002057
#define MASK_VWSUBUWV		0xfc00707f
#define MATCH_VWSUBUWX		0xd8006057
#define MASK_VWSUBUWX		0xfc00707f
#define MATCH_VZEXT_VF8		0x48012057
#define MASK_VZEXT_VF8		0xfc0ff07f
#define MATCH_VSEXT_VF8		0x4801a057
#define MASK_VSEXT_VF8		0xfc0ff07f
#define MATCH_VZEXT_VF4		0x48022057
#define MASK_VZEXT_VF4		0xfc0ff07f
#define MATCH_VSEXT_VF4		0x4802a057
#define MASK_VSEXT_VF4		0xfc0ff07f
#define MATCH_VZEXT_VF2		0x48032057
#define MASK_VZEXT_VF2		0xfc0ff07f
#define MATCH_VSEXT_VF2		0x4803a057
#define MASK_VSEXT_VF2		0xfc0ff07f
#define MATCH_VADCVVM		0x40000057
#define MASK_VADCVVM		0xfe00707f
#define MATCH_VADCVXM		0x40004057
#define MASK_VADCVXM		0xfe00707f
#define MATCH_VADCVIM		0x40003057
#define MASK_VADCVIM		0xfe00707f
#define MATCH_VMADCVVM		0x44000057
#define MASK_VMADCVVM		0xfe00707f
#define MATCH_VMADCVXM		0x44004057
#define MASK_VMADCVXM		0xfe00707f
#define MATCH_VMADCVIM		0x44003057
#define MASK_VMADCVIM		0xfe00707f
#define MATCH_VMADCVV		0x46000057
#define MASK_VMADCVV		0xfe00707f
#define MATCH_VMADCVX		0x46004057
#define MASK_VMADCVX		0xfe00707f
#define MATCH_VMADCVI		0x46003057
#define MASK_VMADCVI		0xfe00707f
#define MATCH_VSBCVVM		0x48000057
#define MASK_VSBCVVM		0xfe00707f
#define MATCH_VSBCVXM		0x48004057
#define MASK_VSBCVXM		0xfe00707f
#define MATCH_VMSBCVVM		0x4c000057
#define MASK_VMSBCVVM		0xfe00707f
#define MATCH_VMSBCVXM		0x4c004057
#define MASK_VMSBCVXM		0xfe00707f
#define MATCH_VMSBCVV		0x4e000057
#define MASK_VMSBCVV		0xfe00707f
#define MATCH_VMSBCVX		0x4e004057
#define MASK_VMSBCVX		0xfe00707f
#define MATCH_VNOTV		0x2c0fb057
#define MASK_VNOTV		0xfc0ff07f
#define MATCH_VANDVV		0x24000057
#define MASK_VANDVV		0xfc00707f
#define MATCH_VANDVX		0x24004057
#define MASK_VANDVX		0xfc00707f
#define MATCH_VANDVI		0x24003057
#define MASK_VANDVI		0xfc00707f
#define MATCH_VORVV		0x28000057
#define MASK_VORVV		0xfc00707f
#define MATCH_VORVX		0x28004057
#define MASK_VORVX		0xfc00707f
#define MATCH_VORVI		0x28003057
#define MASK_VORVI		0xfc00707f
#define MATCH_VXORVV		0x2c000057
#define MASK_VXORVV		0xfc00707f
#define MATCH_VXORVX		0x2c004057
#define MASK_VXORVX		0xfc00707f
#define MATCH_VXORVI		0x2c003057
#define MASK_VXORVI		0xfc00707f
#define MATCH_VSLLVV		0x94000057
#define MASK_VSLLVV		0xfc00707f
#define MATCH_VSLLVX		0x94004057
#define MASK_VSLLVX		0xfc00707f
#define MATCH_VSLLVI		0x94003057
#define MASK_VSLLVI		0xfc00707f
#define MATCH_VSRLVV		0xa0000057
#define MASK_VSRLVV		0xfc00707f
#define MATCH_VSRLVX		0xa0004057
#define MASK_VSRLVX		0xfc00707f
#define MATCH_VSRLVI		0xa0003057
#define MASK_VSRLVI		0xfc00707f
#define MATCH_VSRAVV		0xa4000057
#define MASK_VSRAVV		0xfc00707f
#define MATCH_VSRAVX		0xa4004057
#define MASK_VSRAVX		0xfc00707f
#define MATCH_VSRAVI		0xa4003057
#define MASK_VSRAVI		0xfc00707f
#define MATCH_VNCVTXXW		0xb0004057
#define MASK_VNCVTXXW		0xfc0ff07f
#define MATCH_VNSRLWV		0xb0000057
#define MASK_VNSRLWV		0xfc00707f
#define MATCH_VNSRLWX		0xb0004057
#define MASK_VNSRLWX		0xfc00707f
#define MATCH_VNSRLWI		0xb0003057
#define MASK_VNSRLWI		0xfc00707f
#define MATCH_VNSRAWV		0xb4000057
#define MASK_VNSRAWV		0xfc00707f
#define MATCH_VNSRAWX		0xb4004057
#define MASK_VNSRAWX		0xfc00707f
#define MATCH_VNSRAWI		0xb4003057
#define MASK_VNSRAWI		0xfc00707f
#define MATCH_VMSEQVV		0x60000057
#define MASK_VMSEQVV		0xfc00707f
#define MATCH_VMSEQVX		0x60004057
#define MASK_VMSEQVX		0xfc00707f
#define MATCH_VMSEQVI		0x60003057
#define MASK_VMSEQVI		0xfc00707f
#define MATCH_VMSNEVV		0x64000057
#define MASK_VMSNEVV		0xfc00707f
#define MATCH_VMSNEVX		0x64004057
#define MASK_VMSNEVX		0xfc00707f
#define MATCH_VMSNEVI		0x64003057
#define MASK_VMSNEVI		0xfc00707f
#define MATCH_VMSLTVV		0x6c000057
#define MASK_VMSLTVV		0xfc00707f
#define MATCH_VMSLTVX		0x6c004057
#define MASK_VMSLTVX		0xfc00707f
#define MATCH_VMSLTUVV		0x68000057
#define MASK_VMSLTUVV		0xfc00707f
#define MATCH_VMSLTUVX		0x68004057
#define MASK_VMSLTUVX		0xfc00707f
#define MATCH_VMSLEVV		0x74000057
#define MASK_VMSLEVV		0xfc00707f
#define MATCH_VMSLEVX		0x74004057
#define MASK_VMSLEVX		0xfc00707f
#define MATCH_VMSLEVI		0x74003057
#define MASK_VMSLEVI		0xfc00707f
#define MATCH_VMSLEUVV		0x70000057
#define MASK_VMSLEUVV		0xfc00707f
#define MATCH_VMSLEUVX		0x70004057
#define MASK_VMSLEUVX		0xfc00707f
#define MATCH_VMSLEUVI		0x70003057
#define MASK_VMSLEUVI		0xfc00707f
#define MATCH_VMSGTVX		0x7c004057
#define MASK_VMSGTVX		0xfc00707f
#define MATCH_VMSGTVI		0x7c003057
#define MASK_VMSGTVI		0xfc00707f
#define MATCH_VMSGTUVX		0x78004057
#define MASK_VMSGTUVX		0xfc00707f
#define MATCH_VMSGTUVI		0x78003057
#define MASK_VMSGTUVI		0xfc00707f
#define MATCH_VMINVV		0x14000057
#define MASK_VMINVV		0xfc00707f
#define MATCH_VMINVX		0x14004057
#define MASK_VMINVX		0xfc00707f
#define MATCH_VMAXVV		0x1c000057
#define MASK_VMAXVV		0xfc00707f
#define MATCH_VMAXVX		0x1c004057
#define MASK_VMAXVX		0xfc00707f
#define MATCH_VMINUVV		0x10000057
#define MASK_VMINUVV		0xfc00707f
#define MATCH_VMINUVX		0x10004057
#define MASK_VMINUVX		0xfc00707f
#define MATCH_VMAXUVV		0x18000057
#define MASK_VMAXUVV		0xfc00707f
#define MATCH_VMAXUVX		0x18004057
#define MASK_VMAXUVX		0xfc00707f
#define MATCH_VMULVV		0x94002057
#define MASK_VMULVV		0xfc00707f
#define MATCH_VMULVX		0x94006057
#define MASK_VMULVX		0xfc00707f
#define MATCH_VMULHVV		0x9c002057
#define MASK_VMULHVV		0xfc00707f
#define MATCH_VMULHVX		0x9c006057
#define MASK_VMULHVX		0xfc00707f
#define MATCH_VMULHUVV		0x90002057
#define MASK_VMULHUVV		0xfc00707f
#define MATCH_VMULHUVX		0x90006057
#define MASK_VMULHUVX		0xfc00707f
#define MATCH_VMULHSUVV		0x98002057
#define MASK_VMULHSUVV		0xfc00707f
#define MATCH_VMULHSUVX		0x98006057
#define MASK_VMULHSUVX		0xfc00707f
#define MATCH_VWMULVV		0xec002057
#define MASK_VWMULVV		0xfc00707f
#define MATCH_VWMULVX		0xec006057
#define MASK_VWMULVX		0xfc00707f
#define MATCH_VWMULUVV		0xe0002057
#define MASK_VWMULUVV		0xfc00707f
#define MATCH_VWMULUVX		0xe0006057
#define MASK_VWMULUVX		0xfc00707f
#define MATCH_VWMULSUVV		0xe8002057
#define MASK_VWMULSUVV		0xfc00707f
#define MATCH_VWMULSUVX		0xe8006057
#define MASK_VWMULSUVX		0xfc00707f
#define MATCH_VMACCVV		0xb4002057
#define MASK_VMACCVV		0xfc00707f
#define MATCH_VMACCVX		0xb4006057
#define MASK_VMACCVX		0xfc00707f
#define MATCH_VNMSACVV		0xbc002057
#define MASK_VNMSACVV		0xfc00707f
#define MATCH_VNMSACVX		0xbc006057
#define MASK_VNMSACVX		0xfc00707f
#define MATCH_VMADDVV		0xa4002057
#define MASK_VMADDVV		0xfc00707f
#define MATCH_VMADDVX		0xa4006057
#define MASK_VMADDVX		0xfc00707f
#define MATCH_VNMSUBVV		0xac002057
#define MASK_VNMSUBVV		0xfc00707f
#define MATCH_VNMSUBVX		0xac006057
#define MASK_VNMSUBVX		0xfc00707f
#define MATCH_VWMACCUVV		0xf0002057
#define MASK_VWMACCUVV		0xfc00707f
#define MATCH_VWMACCUVX		0xf0006057
#define MASK_VWMACCUVX		0xfc00707f
#define MATCH_VWMACCVV		0xf4002057
#define MASK_VWMACCVV		0xfc00707f
#define MATCH_VWMACCVX		0xf4006057
#define MASK_VWMACCVX		0xfc00707f
#define MATCH_VWMACCSUVV	0xfc002057
#define MASK_VWMACCSUVV		0xfc00707f
#define MATCH_VWMACCSUVX	0xfc006057
#define MASK_VWMACCSUVX		0xfc00707f
#define MATCH_VWMACCUSVX	0xf8006057
#define MASK_VWMACCUSVX		0xfc00707f
#define MATCH_VQMACCUVV		0xf0000057
#define MASK_VQMACCUVV		0xfc00707f
#define MATCH_VQMACCUVX		0xf0004057
#define MASK_VQMACCUVX		0xfc00707f
#define MATCH_VQMACCVV		0xf4000057
#define MASK_VQMACCVV		0xfc00707f
#define MATCH_VQMACCVX		0xf4004057
#define MASK_VQMACCVX		0xfc00707f
#define MATCH_VQMACCSUVV	0xfc000057
#define MASK_VQMACCSUVV		0xfc00707f
#define MATCH_VQMACCSUVX	0xfc004057
#define MASK_VQMACCSUVX		0xfc00707f
#define MATCH_VQMACCUSVX	0xf8004057
#define MASK_VQMACCUSVX		0xfc00707f
#define MATCH_VDIVVV		0x84002057
#define MASK_VDIVVV		0xfc00707f
#define MATCH_VDIVVX		0x84006057
#define MASK_VDIVVX		0xfc00707f
#define MATCH_VDIVUVV		0x80002057
#define MASK_VDIVUVV		0xfc00707f
#define MATCH_VDIVUVX		0x80006057
#define MASK_VDIVUVX		0xfc00707f
#define MATCH_VREMVV		0x8c002057
#define MASK_VREMVV		0xfc00707f
#define MATCH_VREMVX		0x8c006057
#define MASK_VREMVX		0xfc00707f
#define MATCH_VREMUVV		0x88002057
#define MASK_VREMUVV		0xfc00707f
#define MATCH_VREMUVX		0x88006057
#define MASK_VREMUVX		0xfc00707f
#define MATCH_VMERGEVVM		0x5c000057
#define MASK_VMERGEVVM		0xfe00707f
#define MATCH_VMERGEVXM		0x5c004057
#define MASK_VMERGEVXM		0xfe00707f
#define MATCH_VMERGEVIM		0x5c003057
#define MASK_VMERGEVIM		0xfe00707f
#define MATCH_VMVVV		0x5e000057
#define MASK_VMVVV		0xfff0707f
#define MATCH_VMVVX		0x5e004057
#define MASK_VMVVX		0xfff0707f
#define MATCH_VMVVI		0x5e003057
#define MASK_VMVVI		0xfff0707f
#define MATCH_VSADDUVV		0x80000057
#define MASK_VSADDUVV		0xfc00707f
#define MATCH_VSADDUVX		0x80004057
#define MASK_VSADDUVX		0xfc00707f
#define MATCH_VSADDUVI		0x80003057
#define MASK_VSADDUVI		0xfc00707f
#define MATCH_VSADDVV		0x84000057
#define MASK_VSADDVV		0xfc00707f
#define MATCH_VSADDVX		0x84004057
#define MASK_VSADDVX		0xfc00707f
#define MATCH_VSADDVI		0x84003057
#define MASK_VSADDVI		0xfc00707f
#define MATCH_VSSUBUVV		0x88000057
#define MASK_VSSUBUVV		0xfc00707f
#define MATCH_VSSUBUVX		0x88004057
#define MASK_VSSUBUVX		0xfc00707f
#define MATCH_VSSUBVV		0x8c000057
#define MASK_VSSUBVV		0xfc00707f
#define MATCH_VSSUBVX		0x8c004057
#define MASK_VSSUBVX		0xfc00707f
#define MATCH_VAADDUVV		0x20002057
#define MASK_VAADDUVV		0xfc00707f
#define MATCH_VAADDUVX		0x20006057
#define MASK_VAADDUVX		0xfc00707f
#define MATCH_VAADDVV		0x24002057
#define MASK_VAADDVV		0xfc00707f
#define MATCH_VAADDVX		0x24006057
#define MASK_VAADDVX		0xfc00707f
#define MATCH_VASUBUVV		0x28002057
#define MASK_VASUBUVV		0xfc00707f
#define MATCH_VASUBUVX		0x28006057
#define MASK_VASUBUVX		0xfc00707f
#define MATCH_VASUBVV		0x2c002057
#define MASK_VASUBVV		0xfc00707f
#define MATCH_VASUBVX		0x2c006057
#define MASK_VASUBVX		0xfc00707f
#define MATCH_VSMULVV		0x9c000057
#define MASK_VSMULVV		0xfc00707f
#define MATCH_VSMULVX		0x9c004057
#define MASK_VSMULVX		0xfc00707f
#define MATCH_VSSRLVV		0xa8000057
#define MASK_VSSRLVV		0xfc00707f
#define MATCH_VSSRLVX		0xa8004057
#define MASK_VSSRLVX		0xfc00707f
#define MATCH_VSSRLVI		0xa8003057
#define MASK_VSSRLVI		0xfc00707f
#define MATCH_VSSRAVV		0xac000057
#define MASK_VSSRAVV		0xfc00707f
#define MATCH_VSSRAVX		0xac004057
#define MASK_VSSRAVX		0xfc00707f
#define MATCH_VSSRAVI		0xac003057
#define MASK_VSSRAVI		0xfc00707f
#define MATCH_VNCLIPUWV		0xb8000057
#define MASK_VNCLIPUWV		0xfc00707f
#define MATCH_VNCLIPUWX		0xb8004057
#define MASK_VNCLIPUWX		0xfc00707f
#define MATCH_VNCLIPUWI		0xb8003057
#define MASK_VNCLIPUWI		0xfc00707f
#define MATCH_VNCLIPWV		0xbc000057
#define MASK_VNCLIPWV		0xfc00707f
#define MATCH_VNCLIPWX		0xbc004057
#define MASK_VNCLIPWX		0xfc00707f
#define MATCH_VNCLIPWI		0xbc003057
#define MASK_VNCLIPWI		0xfc00707f
#define MATCH_VFADDVV		0x00001057
#define MASK_VFADDVV		0xfc00707f
#define MATCH_VFADDVF		0x00005057
#define MASK_VFADDVF		0xfc00707f
#define MATCH_VFSUBVV		0x08001057
#define MASK_VFSUBVV		0xfc00707f
#define MATCH_VFSUBVF		0x08005057
#define MASK_VFSUBVF		0xfc00707f
#define MATCH_VFRSUBVF		0x9c005057
#define MASK_VFRSUBVF		0xfc00707f
#define MATCH_VFWADDVV		0xc0001057
#define MASK_VFWADDVV		0xfc00707f
#define MATCH_VFWADDVF		0xc0005057
#define MASK_VFWADDVF		0xfc00707f
#define MATCH_VFWSUBVV		0xc8001057
#define MASK_VFWSUBVV		0xfc00707f
#define MATCH_VFWSUBVF		0xc8005057
#define MASK_VFWSUBVF		0xfc00707f
#define MATCH_VFWADDWV		0xd0001057
#define MASK_VFWADDWV		0xfc00707f
#define MATCH_VFWADDWF		0xd0005057
#define MASK_VFWADDWF		0xfc00707f
#define MATCH_VFWSUBWV		0xd8001057
#define MASK_VFWSUBWV		0xfc00707f
#define MATCH_VFWSUBWF		0xd8005057
#define MASK_VFWSUBWF		0xfc00707f
#define MATCH_VFMULVV		0x90001057
#define MASK_VFMULVV		0xfc00707f
#define MATCH_VFMULVF		0x90005057
#define MASK_VFMULVF		0xfc00707f
#define MATCH_VFDIVVV		0x80001057
#define MASK_VFDIVVV		0xfc00707f
#define MATCH_VFDIVVF		0x80005057
#define MASK_VFDIVVF		0xfc00707f
#define MATCH_VFRDIVVF		0x84005057
#define MASK_VFRDIVVF		0xfc00707f
#define MATCH_VFWMULVV		0xe0001057
#define MASK_VFWMULVV		0xfc00707f
#define MATCH_VFWMULVF		0xe0005057
#define MASK_VFWMULVF		0xfc00707f
#define MATCH_VFMADDVV		0xa0001057
#define MASK_VFMADDVV		0xfc00707f
#define MATCH_VFMADDVF		0xa0005057
#define MASK_VFMADDVF		0xfc00707f
#define MATCH_VFNMADDVV		0xa4001057
#define MASK_VFNMADDVV		0xfc00707f
#define MATCH_VFNMADDVF		0xa4005057
#define MASK_VFNMADDVF		0xfc00707f
#define MATCH_VFMSUBVV		0xa8001057
#define MASK_VFMSUBVV		0xfc00707f
#define MATCH_VFMSUBVF		0xa8005057
#define MASK_VFMSUBVF		0xfc00707f
#define MATCH_VFNMSUBVV		0xac001057
#define MASK_VFNMSUBVV		0xfc00707f
#define MATCH_VFNMSUBVF		0xac005057
#define MASK_VFNMSUBVF		0xfc00707f
#define MATCH_VFMACCVV		0xb0001057
#define MASK_VFMACCVV		0xfc00707f
#define MATCH_VFMACCVF		0xb0005057
#define MASK_VFMACCVF		0xfc00707f
#define MATCH_VFNMACCVV		0xb4001057
#define MASK_VFNMACCVV		0xfc00707f
#define MATCH_VFNMACCVF		0xb4005057
#define MASK_VFNMACCVF		0xfc00707f
#define MATCH_VFMSACVV		0xb8001057
#define MASK_VFMSACVV		0xfc00707f
#define MATCH_VFMSACVF		0xb8005057
#define MASK_VFMSACVF		0xfc00707f
#define MATCH_VFNMSACVV		0xbc001057
#define MASK_VFNMSACVV		0xfc00707f
#define MATCH_VFNMSACVF		0xbc005057
#define MASK_VFNMSACVF		0xfc00707f
#define MATCH_VFWMACCVV		0xf0001057
#define MASK_VFWMACCVV		0xfc00707f
#define MATCH_VFWMACCVF		0xf0005057
#define MASK_VFWMACCVF		0xfc00707f
#define MATCH_VFWNMACCVV	0xf4001057
#define MASK_VFWNMACCVV		0xfc00707f
#define MATCH_VFWNMACCVF	0xf4005057
#define MASK_VFWNMACCVF		0xfc00707f
#define MATCH_VFWMSACVV		0xf8001057
#define MASK_VFWMSACVV		0xfc00707f
#define MATCH_VFWMSACVF		0xf8005057
#define MASK_VFWMSACVF		0xfc00707f
#define MATCH_VFWNMSACVV	0xfc001057
#define MASK_VFWNMSACVV		0xfc00707f
#define MATCH_VFWNMSACVF	0xfc005057
#define MASK_VFWNMSACVF		0xfc00707f
#define MATCH_VFSQRTV		0x4c001057
#define MASK_VFSQRTV		0xfc0ff07f
#define MATCH_VFRSQRT7V		0x4c021057
#define MASK_VFRSQRT7V		0xfc0ff07f
#define MATCH_VFREC7V		0x4c029057
#define MASK_VFREC7V		0xfc0ff07f
#define MATCH_VFCLASSV		0x4c081057
#define MASK_VFCLASSV		0xfc0ff07f
#define MATCH_VFMINVV		0x10001057
#define MASK_VFMINVV		0xfc00707f
#define MATCH_VFMINVF		0x10005057
#define MASK_VFMINVF		0xfc00707f
#define MATCH_VFMAXVV		0x18001057
#define MASK_VFMAXVV		0xfc00707f
#define MATCH_VFMAXVF		0x18005057
#define MASK_VFMAXVF		0xfc00707f
#define MATCH_VFSGNJVV		0x20001057
#define MASK_VFSGNJVV		0xfc00707f
#define MATCH_VFSGNJVF		0x20005057
#define MASK_VFSGNJVF		0xfc00707f
#define MATCH_VFSGNJNVV		0x24001057
#define MASK_VFSGNJNVV		0xfc00707f
#define MATCH_VFSGNJNVF		0x24005057
#define MASK_VFSGNJNVF		0xfc00707f
#define MATCH_VFSGNJXVV		0x28001057
#define MASK_VFSGNJXVV		0xfc00707f
#define MATCH_VFSGNJXVF		0x28005057
#define MASK_VFSGNJXVF		0xfc00707f
#define MATCH_VMFEQVV		0x60001057
#define MASK_VMFEQVV		0xfc00707f
#define MATCH_VMFEQVF		0x60005057
#define MASK_VMFEQVF		0xfc00707f
#define MATCH_VMFNEVV		0x70001057
#define MASK_VMFNEVV		0xfc00707f
#define MATCH_VMFNEVF		0x70005057
#define MASK_VMFNEVF		0xfc00707f
#define MATCH_VMFLTVV		0x6c001057
#define MASK_VMFLTVV		0xfc00707f
#define MATCH_VMFLTVF		0x6c005057
#define MASK_VMFLTVF		0xfc00707f
#define MATCH_VMFLEVV		0x64001057
#define MASK_VMFLEVV		0xfc00707f
#define MATCH_VMFLEVF		0x64005057
#define MASK_VMFLEVF		0xfc00707f
#define MATCH_VMFGTVF		0x74005057
#define MASK_VMFGTVF		0xfc00707f
#define MATCH_VMFGEVF		0x7c005057
#define MASK_VMFGEVF		0xfc00707f
#define MATCH_VFMERGEVFM	0x5c005057
#define MASK_VFMERGEVFM		0xfe00707f
#define MATCH_VFMVVF		0x5e005057
#define MASK_VFMVVF		0xfff0707f
#define MATCH_VFCVTXUFV		0x48001057
#define MASK_VFCVTXUFV		0xfc0ff07f
#define MATCH_VFCVTXFV		0x48009057
#define MASK_VFCVTXFV		0xfc0ff07f
#define MATCH_VFCVTFXUV		0x48011057
#define MASK_VFCVTFXUV		0xfc0ff07f
#define MATCH_VFCVTFXV		0x48019057
#define MASK_VFCVTFXV		0xfc0ff07f
#define MATCH_VFCVTRTZXUFV	0x48031057
#define MASK_VFCVTRTZXUFV	0xfc0ff07f
#define MATCH_VFCVTRTZXFV	0x48039057
#define MASK_VFCVTRTZXFV	0xfc0ff07f
#define MATCH_VFWCVTXUFV	0x48041057
#define MASK_VFWCVTXUFV		0xfc0ff07f
#define MATCH_VFWCVTXFV		0x48049057
#define MASK_VFWCVTXFV		0xfc0ff07f
#define MATCH_VFWCVTFXUV	0x48051057
#define MASK_VFWCVTFXUV		0xfc0ff07f
#define MATCH_VFWCVTFXV		0x48059057
#define MASK_VFWCVTFXV		0xfc0ff07f
#define MATCH_VFWCVTFFV		0x48061057
#define MASK_VFWCVTFFV		0xfc0ff07f
#define MATCH_VFWCVTRTZXUFV	0x48071057
#define MASK_VFWCVTRTZXUFV	0xfc0ff07f
#define MATCH_VFWCVTRTZXFV	0x48079057
#define MASK_VFWCVTRTZXFV	0xfc0ff07f
#define MATCH_VFNCVTXUFW	0x48081057
#define MASK_VFNCVTXUFW		0xfc0ff07f
#define MATCH_VFNCVTXFW		0x48089057
#define MASK_VFNCVTXFW		0xfc0ff07f
#define MATCH_VFNCVTFXUW	0x48091057
#define MASK_VFNCVTFXUW		0xfc0ff07f
#define MATCH_VFNCVTFXW		0x48099057
#define MASK_VFNCVTFXW		0xfc0ff07f
#define MATCH_VFNCVTFFW		0x480a1057
#define MASK_VFNCVTFFW		0xfc0ff07f
#define MATCH_VFNCVTRODFFW	0x480a9057
#define MASK_VFNCVTRODFFW	0xfc0ff07f
#define MATCH_VFNCVTRTZXUFW	0x480b1057
#define MASK_VFNCVTRTZXUFW	0xfc0ff07f
#define MATCH_VFNCVTRTZXFW	0x480b9057
#define MASK_VFNCVTRTZXFW	0xfc0ff07f
#define MATCH_VREDSUMVS		0x00002057
#define MASK_VREDSUMVS		0xfc00707f
#define MATCH_VREDMAXVS		0x1c002057
#define MASK_VREDMAXVS		0xfc00707f
#define MATCH_VREDMAXUVS	0x18002057
#define MASK_VREDMAXUVS		0xfc00707f
#define MATCH_VREDMINVS		0x14002057
#define MASK_VREDMINVS		0xfc00707f
#define MATCH_VREDMINUVS	0x10002057
#define MASK_VREDMINUVS		0xfc00707f
#define MATCH_VREDANDVS		0x04002057
#define MASK_VREDANDVS		0xfc00707f
#define MATCH_VREDORVS		0x08002057
#define MASK_VREDORVS		0xfc00707f
#define MATCH_VREDXORVS		0x0c002057
#define MASK_VREDXORVS		0xfc00707f
#define MATCH_VWREDSUMUVS	0xc0000057
#define MASK_VWREDSUMUVS	0xfc00707f
#define MATCH_VWREDSUMVS	0xc4000057
#define MASK_VWREDSUMVS		0xfc00707f
#define MATCH_VFREDOSUMVS	0x0c001057
#define MASK_VFREDOSUMVS	0xfc00707f
#define MATCH_VFREDUSUMVS	0x04001057
#define MASK_VFREDUSUMVS	0xfc00707f
#define MATCH_VFREDMAXVS	0x1c001057
#define MASK_VFREDMAXVS		0xfc00707f
#define MATCH_VFREDMINVS	0x14001057
#define MASK_VFREDMINVS		0xfc00707f
#define MATCH_VFWREDOSUMVS	0xcc001057
#define MASK_VFWREDOSUMVS	0xfc00707f
#define MATCH_VFWREDUSUMVS	0xc4001057
#define MASK_VFWREDUSUMVS	0xfc00707f
#define MATCH_VMANDMM		0x66002057
#define MASK_VMANDMM		0xfe00707f
#define MATCH_VMNANDMM		0x76002057
#define MASK_VMNANDMM		0xfe00707f
#define MATCH_VMANDNMM		0x62002057
#define MASK_VMANDNMM		0xfe00707f
#define MATCH_VMXORMM		0x6e002057
#define MASK_VMXORMM		0xfe00707f
#define MATCH_VMORMM		0x6a002057
#define MASK_VMORMM		0xfe00707f
#define MATCH_VMNORMM		0x7a002057
#define MASK_VMNORMM		0xfe00707f
#define MATCH_VMORNMM		0x72002057
#define MASK_VMORNMM		0xfe00707f
#define MATCH_VMXNORMM		0x7e002057
#define MASK_VMXNORMM		0xfe00707f
#define MATCH_VCPOPM		0x40082057
#define MASK_VCPOPM		0xfc0ff07f
#define MATCH_VFIRSTM		0x4008a057
#define MASK_VFIRSTM		0xfc0ff07f
#define MATCH_VMSBFM		0x5000a057
#define MASK_VMSBFM		0xfc0ff07f
#define MATCH_VMSIFM		0x5001a057
#define MASK_VMSIFM		0xfc0ff07f
#define MATCH_VMSOFM		0x50012057
#define MASK_VMSOFM		0xfc0ff07f
#define MATCH_VIOTAM		0x50082057
#define MASK_VIOTAM		0xfc0ff07f
#define MATCH_VIDV		0x5008a057
#define MASK_VIDV		0xfdfff07f
#define MATCH_VMVXS		0x42002057
#define MASK_VMVXS		0xfe0ff07f
#define MATCH_VMVSX		0x42006057
#define MASK_VMVSX		0xfff0707f
#define MATCH_VFMVFS		0x42001057
#define MASK_VFMVFS		0xfe0ff07f
#define MATCH_VFMVSF		0x42005057
#define MASK_VFMVSF		0xfff0707f
#define MATCH_VSLIDEUPVX	0x38004057
#define MASK_VSLIDEUPVX		0xfc00707f
#define MATCH_VSLIDEUPVI	0x38003057
#define MASK_VSLIDEUPVI		0xfc00707f
#define MATCH_VSLIDEDOWNVX	0x3c004057
#define MASK_VSLIDEDOWNVX	0xfc00707f
#define MATCH_VSLIDEDOWNVI	0x3c003057
#define MASK_VSLIDEDOWNVI	0xfc00707f
#define MATCH_VSLIDE1UPVX	0x38006057
#define MASK_VSLIDE1UPVX	0xfc00707f
#define MATCH_VSLIDE1DOWNVX	0x3c006057
#define MASK_VSLIDE1DOWNVX	0xfc00707f
#define MATCH_VFSLIDE1UPVF	0x38005057
#define MASK_VFSLIDE1UPVF	0xfc00707f
#define MATCH_VFSLIDE1DOWNVF	0x3c005057
#define MASK_VFSLIDE1DOWNVF	0xfc00707f
#define MATCH_VRGATHERVV	0x30000057
#define MASK_VRGATHERVV		0xfc00707f
#define MATCH_VRGATHERVX	0x30004057
#define MASK_VRGATHERVX		0xfc00707f
#define MATCH_VRGATHERVI	0x30003057
#define MASK_VRGATHERVI		0xfc00707f
#define MATCH_VRGATHEREI16VV	0x38000057
#define MASK_VRGATHEREI16VV	0xfc00707f
#define MATCH_VCOMPRESSVM	0x5e002057
#define MASK_VCOMPRESSVM	0xfe00707f
#define MATCH_VMV1RV		0x9e003057
#define MASK_VMV1RV		0xfe0ff07f
#define MATCH_VMV2RV		0x9e00b057
#define MASK_VMV2RV		0xfe0ff07f
#define MATCH_VMV4RV		0x9e01b057
#define MASK_VMV4RV		0xfe0ff07f
#define MATCH_VMV8RV		0x9e03b057
#define MASK_VMV8RV		0xfe0ff07f
#define MATCH_VDOTVV		0xe4000057
#define MASK_VDOTVV		0xfc00707f
#define MATCH_VDOTUVV		0xe0000057
#define MASK_VDOTUVV		0xfc00707f
#define MATCH_VFDOTVV		0xe4001057
#define MASK_VFDOTVV		0xfc00707f
/* Svinval instruction.  */
#define MATCH_SINVAL_VMA	0x16000073
#define MASK_SINVAL_VMA		0xfe007fff
#define MATCH_SFENCE_W_INVAL	0x18000073
#define MASK_SFENCE_W_INVAL	0xffffffff
#define MATCH_SFENCE_INVAL_IR	0x18100073
#define MASK_SFENCE_INVAL_IR	0xffffffff
#define MATCH_HINVAL_VVMA	0x36000073
#define MASK_HINVAL_VVMA	0xfe007fff
#define MATCH_HINVAL_GVMA	0x76000073
#define MASK_HINVAL_GVMA	0xfe007fff
#endif /* RISCV_EXTENDED_ENCODING_H */
#ifdef DECLARE_INSN
DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
DECLARE_INSN(fsub_h, MATCH_FSUB_D, MASK_FSUB_H)
DECLARE_INSN(fmul_h, MATCH_FMUL_D, MASK_FMUL_H)
DECLARE_INSN(fdiv_h, MATCH_FDIV_D, MASK_FDIV_H)
DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_D, MASK_FSGNJ_H)
DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_D, MASK_FSGNJN_H)
DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_D, MASK_FSGNJX_H)
DECLARE_INSN(fmin_h, MATCH_FMIN_D, MASK_FMIN_H)
DECLARE_INSN(fmax_h, MATCH_FMAX_D, MASK_FMAX_H)
DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_D, MASK_FCVT_S_H)
DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H)
DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q)
DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H)
DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA)
DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL)
DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR)
DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA)
DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA)
#endif /* DECLARE_INSN */
#ifdef DECLARE_CSR
/* Unprivileged extended CSR addresses.  */
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
#define CSR_VXRM 0x00a
#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
#define CSR_VLENB 0xc22
/* Unprivileged extended CSRs.  */
DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
#endif /* DECLARE_CSR */

#ifndef __RISCV_OPC_VENDOR_THEAD__
#define __RISCV_OPC_VENDOR_THEAD__
/* Opcodes for T-HEAD.  */
#define MATCH_DCACHE_CALL	0x0010000b
#define MASK_DCACHE_CALL	0xffffffff
#define MATCH_DCACHE_IALL	0x0020000b
#define MASK_DCACHE_IALL	0xffffffff
#define MATCH_DCACHE_CSW	0x0210000b
#define MASK_DCACHE_CSW		0xfff07fff
#define MATCH_DCACHE_ISW	0x0220000b
#define MASK_DCACHE_ISW		0xfff07fff
#define MATCH_DCACHE_CIALL	0x0030000b
#define MASK_DCACHE_CIALL	0xffffffff
#define MATCH_DCACHE_CISW	0x0230000b
#define MASK_DCACHE_CISW	0xfff07fff
#define MATCH_DCACHE_CVAL1	0x0240000b
#define MASK_DCACHE_CVAL1	0xfff07fff
#define MATCH_DCACHE_CVA	0x0250000b
#define MASK_DCACHE_CVA		0xfff07fff
#define MATCH_DCACHE_IVA	0x0260000b
#define MASK_DCACHE_IVA		0xfff07fff
#define MATCH_DCACHE_CIVA	0x0270000b
#define MASK_DCACHE_CIVA	0xfff07fff
#define MATCH_DCACHE_CPAL1	0x0280000b
#define MASK_DCACHE_CPAL1	0xfff07fff
#define MATCH_DCACHE_CPA	0x0290000b
#define MASK_DCACHE_CPA		0xfff07fff
#define MATCH_DCACHE_IPA	0x02a0000b
#define MASK_DCACHE_IPA		0xfff07fff
#define MATCH_DCACHE_CIPA	0x02b0000b
#define MASK_DCACHE_CIPA	0xfff07fff
#define MATCH_ICACHE_IALL	0x0100000b
#define MASK_ICACHE_IALL	0xffffffff
#define MATCH_ICACHE_IALLS	0x0110000b
#define MASK_ICACHE_IALLS	0xffffffff
#define MATCH_ICACHE_IVA	0x0300000b
#define MASK_ICACHE_IVA		0xfff07fff
#define MATCH_ICACHE_IPA	0x0380000b
#define MASK_ICACHE_IPA		0xfff07fff
#define MATCH_L2CACHE_CALL	0x0150000b
#define MASK_L2CACHE_CALL	0xffffffff
#define MATCH_L2CACHE_IALL	0x0160000b
#define MASK_L2CACHE_IALL	0xffffffff
#define MATCH_L2CACHE_CIALL	0x0170000b
#define MASK_L2CACHE_CIALL	0xffffffff
#define MATCH_SYNC		0x0180000b
#define MASK_SYNC		0xffffffff
#define MATCH_SYNC_S		0x0190000b
#define MASK_SYNC_S		0xffffffff
#define MATCH_SYNC_I		0x01a0000b
#define MASK_SYNC_I		0xffffffff
#define MATCH_SYNC_IS		0x01b0000b
#define MASK_SYNC_IS		0xffffffff
#define MATCH_SFENCE_VMAS	0x0400000b
#define MASK_SFENCE_VMAS	0xfe007fff
#define MATCH_TSTNBZ		0x8000100b
#define MASK_TSTNBZ		0xfff0707f
#define MATCH_MVEQZ		0x4000100b
#define MASK_MVEQZ		0xfe00707f
#define MATCH_MVNEZ		0x4200100b
#define MASK_MVNEZ		0xfe00707f
#define MATCH_MULA		0x2000100b
#define MASK_MULA		0xfe00707f
#define MATCH_MULS		0x2200100b
#define MASK_MULS		0xfe00707f
#define MATCH_MULAW		0x2400100b
#define MASK_MULAW		0xfe00707f
#define MATCH_MULSW		0x2600100b
#define MASK_MULSW		0xfe00707f
#define MATCH_MULAH		0x2800100b
#define MASK_MULAH		0xfe00707f
#define MATCH_MULSH		0x2a00100b
#define MASK_MULSH		0xfe00707f
#define MATCH_EXT		0x0000200b
#define MASK_EXT		0x0000707f
#define MATCH_EXTU		0x0000300b
#define MASK_EXTU		0x0000707f
#define MATCH_LRB		0x0000400b
#define MASK_LRB		0xf800707f
#define MATCH_LRH		0x2000400b
#define MASK_LRH		0xf800707f
#define MATCH_LRW		0x4000400b
#define MASK_LRW		0xf800707f
#define MATCH_LRD		0x6000400b
#define MASK_LRD		0xf800707f
#define MATCH_LRBU		0x8000400b
#define MASK_LRBU		0xf800707f
#define MATCH_LRHU		0xa000400b
#define MASK_LRHU		0xf800707f
#define MATCH_LRWU		0xc000400b
#define MASK_LRWU		0xf800707f
#define MATCH_LURB		0x1000400b
#define MASK_LURB		0xf800707f
#define MATCH_LURH		0x3000400b
#define MASK_LURH		0xf800707f
#define MATCH_LURW		0x5000400b
#define MASK_LURW		0xf800707f
#define MATCH_LURD		0x7000400b
#define MASK_LURD		0xf800707f
#define MATCH_LURBU		0x9000400b
#define MASK_LURBU		0xf800707f
#define MATCH_LURHU		0xb000400b
#define MASK_LURHU		0xf800707f
#define MATCH_LURWU		0xd000400b
#define MASK_LURWU		0xf800707f
#define MATCH_REV		0x8200100b
#define MASK_REV		0xfff0707f
#define MATCH_FF0		0x8400100b
#define MASK_FF0		0xfff0707f
#define MATCH_FF1		0x8600100b
#define MASK_FF1		0xfff0707f
#define MATCH_SRB		0x0000500b
#define MASK_SRB		0xf800707f
#define MATCH_SRH		0x2000500b
#define MASK_SRH		0xf800707f
#define MATCH_SRW		0x4000500b
#define MASK_SRW		0xf800707f
#define MATCH_SRD		0x6000500b
#define MASK_SRD		0xf800707f
#define MATCH_SURB		0x1000500b
#define MASK_SURB		0xf800707f
#define MATCH_SURH		0x3000500b
#define MASK_SURH		0xf800707f
#define MATCH_SURW		0x5000500b
#define MASK_SURW		0xf800707f
#define MATCH_SURD		0x7000500b
#define MASK_SURD		0xf800707f
#define MATCH_TST		0x8800100b
#define MASK_TST		0xfc00707f
#define MATCH_SRRIW		0x1400100b
#define MASK_SRRIW		0xfe00707f
#define MATCH_SRRI		0x1000100b
#define MASK_SRRI		0xfc00707f
#define MATCH_ADDSL		0x0000100b
#define MASK_ADDSL		0xf800707f
#define MATCH_SWD		0xe000500b
#define MASK_SWD		0xf800707f
#define MATCH_SDD		0xf800500b
#define MASK_SDD		0xf800707f
#define MATCH_SDIA		0x7800500b
#define MASK_SDIA		0xf800707f
#define MATCH_SDIB		0x6800500b
#define MASK_SDIB		0xf800707f
#define MATCH_SWIA		0x5800500b
#define MASK_SWIA		0xf800707f
#define MATCH_SWIB		0x4800500b
#define MASK_SWIB		0xf800707f
#define MATCH_SHIB		0x2800500b
#define MASK_SHIB		0xf800707f
#define MATCH_SHIA		0x3800500b
#define MASK_SHIA		0xf800707f
#define MATCH_SBIA		0x1800500b
#define MASK_SBIA		0xf800707f
#define MATCH_SBIB		0x0800500b
#define MASK_SBIB		0xf800707f
#define MATCH_LWUD		0xf000400b
#define MASK_LWUD		0xf800707f
#define MATCH_LWD		0xe000400b
#define MASK_LWD		0xf800707f
#define MATCH_LDD		0xf800400b
#define MASK_LDD		0xf800707f
#define MATCH_LWUIA		0xd800400b
#define MASK_LWUIA		0xf800707f
#define MATCH_LWUIB		0xc800400b
#define MASK_LWUIB		0xf800707f
#define MATCH_LHUIA		0xb800400b
#define MASK_LHUIA		0xf800707f
#define MATCH_LHUIB		0xa800400b
#define MASK_LHUIB		0xf800707f
#define MATCH_LBUIA		0x9800400b
#define MASK_LBUIA		0xf800707f
#define MATCH_LBUIB		0x8800400b
#define MASK_LBUIB		0xf800707f
#define MATCH_LDIA		0x7800400b
#define MASK_LDIA		0xf800707f
#define MATCH_LDIB		0x6800400b
#define MASK_LDIB		0xf800707f
#define MATCH_LWIA		0x5800400b
#define MASK_LWIA		0xf800707f
#define MATCH_LWIB		0x4800400b
#define MASK_LWIB		0xf800707f
#define MATCH_LHIA		0x3800400b
#define MASK_LHIA		0xf800707f
#define MATCH_LHIB		0x2800400b
#define MASK_LHIB		0xf800707f
#define MATCH_LBIA		0x1800400b
#define MASK_LBIA		0xf800707f
#define MATCH_LBIB		0x0800400b
#define MASK_LBIB		0xf800707f
#define MATCH_REVW		0x9000100b
#define MASK_REVW		0xfff0707f
#define MATCH_FSURD		0x7000700b
#define MASK_FSURD		0xf800707f
#define MATCH_FSURW		0x5000700b
#define MASK_FSURW		0xf800707f
#define MATCH_FSRD		0x6000700b
#define MASK_FSRD		0xf800707f
#define MATCH_FSRW		0x4000700b
#define MASK_FSRW		0xf800707f
#define MATCH_FLURD		0x7000600b
#define MASK_FLURD		0xf800707f
#define MATCH_FLURW		0x5000600b
#define MASK_FLURW		0xf800707f
#define MATCH_FLRD		0x6000600b
#define MASK_FLRD		0xf800707f
#define MATCH_FLRW		0x4000600b
#define MASK_FLRW		0xf800707f
#define MATCH_IPUSH		0x0040000b
#define MASK_IPUSH		0xffffffff
#define MATCH_IPOP		0x0050000b
#define MASK_IPOP		0xffffffff
/* T-HEAD security.  */
#define MATCH_WSC		0xcff01073
#define MASK_WSC 		0xffffffff
/* T-HEAD Float for rv32.  */
#define MATCH_FMV_X_HW		0xc000100b
#define MASK_FMV_X_HW 		0xfff0707f
#define MATCH_FMV_HW_X		0xa000100b
#define MASK_FMV_HW_X 		0xfff0707f
#endif /* __RISCV_OPC_VENDOR_THEAD__ */
#ifdef DECLARE_INSN
DECLARE_INSN(wsc, MATCH_WSC, MASK_WSC)
DECLARE_INSN(dcache.iall, MATCH_DCACHE_IALL, MASK_DCACHE_IALL)
DECLARE_INSN(dcache.call, MATCH_DCACHE_CALL, MASK_DCACHE_CALL)
DECLARE_INSN(dcache.ciall, MATCH_DCACHE_CIALL, MASK_DCACHE_CIALL)
DECLARE_INSN(dcache.isw, MATCH_DCACHE_ISW, MASK_DCACHE_ISW, match_opcode, 0)
DECLARE_INSN(dcache.csw, MATCH_DCACHE_CSW, MASK_DCACHE_CSW)
DECLARE_INSN(dcache.cisw, MATCH_DCACHE_CISW, MASK_DCACHE_CISW)
DECLARE_INSN(dcache.iva, MATCH_DCACHE_IVA, MASK_DCACHE_IVA)
DECLARE_INSN(dcache.cva, MATCH_DCACHE_CVA, MASK_DCACHE_CVA)
DECLARE_INSN(dcache.cval1, MATCH_DCACHE_CVAL1, MASK_DCACHE_CVAL1)
DECLARE_INSN(dcache.civa, MATCH_DCACHE_CIVA, MASK_DCACHE_CIVA)
DECLARE_INSN(dcache.ipa, MATCH_DCACHE_IPA, MASK_DCACHE_IPA)
DECLARE_INSN(dcache.cpa, MATCH_DCACHE_CPA, MASK_DCACHE_CPA)
DECLARE_INSN(dcache.cpal1, MATCH_DCACHE_CPAL1, MASK_DCACHE_CPAL1)
DECLARE_INSN(dcache.cipa, MATCH_DCACHE_CIPA, MASK_DCACHE_CIPA)
DECLARE_INSN(icache.iall, MATCH_ICACHE_IALL, MASK_ICACHE_IALL)
DECLARE_INSN(icache.iall, MATCH_ICACHE_IALL, MASK_ICACHE_IALL, match_opcode)
DECLARE_INSN(icache.ialls, MATCH_ICACHE_IALLS, MASK_ICACHE_IALLS)
DECLARE_INSN(icache.iva, MATCH_ICACHE_IVA, MASK_ICACHE_IVA)
DECLARE_INSN(icache.ipa, MATCH_ICACHE_IPA, MASK_ICACHE_IPA)
DECLARE_INSN(l2cache.iall, MATCH_L2CACHE_IALL, MASK_L2CACHE_IALL)
DECLARE_INSN(l2cache.call, MATCH_L2CACHE_CALL, MASK_L2CACHE_CALL)
DECLARE_INSN(l2cache.ciall, MATCH_L2CACHE_CIALL, MASK_L2CACHE_CIALL)
DECLARE_INSN(sync, MATCH_SYNC, MASK_SYNC)
DECLARE_INSN(sync.i, MATCH_SYNC_I, MASK_SYNC_I)
DECLARE_INSN(sync.s, MATCH_SYNC_S, MASK_SYNC_S)
DECLARE_INSN(sync.is, MATCH_SYNC_IS, MASK_SYNC_IS)
DECLARE_INSN(tstnbz, MATCH_TSTNBZ, MASK_TSTNBZ)
DECLARE_INSN(mula, MATCH_MULA, MASK_MULA)
DECLARE_INSN(muls, MATCH_MULS, MASK_MULS)
DECLARE_INSN(mulah, MATCH_MULAH, MASK_MULAH)
DECLARE_INSN(mulsh, MATCH_MULSH, MASK_MULSH)
DECLARE_INSN(sfence.vmas, MATCH_SFENCE_VMAS, MASK_SFENCE_VMAS)
DECLARE_INSN(mveqz, MATCH_MVEQZ, MASK_MVEQZ)
DECLARE_INSN(mvnez, MATCH_MVNEZ, MASK_MVNEZ)
DECLARE_INSN(mulaw, MATCH_MULAW, MASK_MULAW)
DECLARE_INSN(mulsw, MATCH_MULSW, MASK_MULSW)
DECLARE_INSN(ext, MATCH_EXT, MASK_EXT)
DECLARE_INSN(ext, MATCH_EXT, (MASK_EXT | (1U<<25) | (1U<<31)))
DECLARE_INSN(extu, MATCH_EXTU, MASK_EXTU)
DECLARE_INSN(extu, MATCH_EXTU, (MASK_EXTU | (1U<<25) | (1U<<31)))
DECLARE_INSN(ff1, MATCH_FF1, MASK_FF1)
DECLARE_INSN(ff0, MATCH_FF0, MASK_FF1)
DECLARE_INSN(rev, MATCH_REV, MASK_REV)
DECLARE_INSN(lrb, MATCH_LRB, MASK_LRB)
DECLARE_INSN(lrbu, MATCH_LRBU, MASK_LRBU)
DECLARE_INSN(lrh, MATCH_LRH, MASK_LRH)
DECLARE_INSN(lrhu, MATCH_LRHU, MASK_LRHU)
DECLARE_INSN(lrw, MATCH_LRW, MASK_LRW)
DECLARE_INSN(lrwu, MATCH_LRWU, MASK_LRWU)
DECLARE_INSN(srb, MATCH_SRB, MASK_SRB)
DECLARE_INSN(srh, MATCH_SRH, MASK_SRH)
DECLARE_INSN(srw, MATCH_SRW, MASK_SRW)
DECLARE_INSN(lrd, MATCH_LRD, MASK_LRD)
DECLARE_INSN(srd, MATCH_SRD, MASK_SRD)
DECLARE_INSN(lurb, MATCH_LURB, MASK_LURB)
DECLARE_INSN(lurbu, MATCH_LURBU, MASK_LURBU)
DECLARE_INSN(lurh, MATCH_LURH, MASK_LURH)
DECLARE_INSN(lurhu, MATCH_LURHU, MASK_LURHU)
DECLARE_INSN(lurw, MATCH_LURW, MASK_LURW)
DECLARE_INSN(lurwu, MATCH_LURWU, MASK_LURWU)
DECLARE_INSN(lurd, MATCH_LURD, MASK_LURD)
DECLARE_INSN(surb, MATCH_SURB, MASK_SURB)
DECLARE_INSN(surh, MATCH_SURH, MASK_SURH)
DECLARE_INSN(surw, MATCH_SURW, MASK_SURW)
DECLARE_INSN(surd, MATCH_SURD, MASK_SURD)
DECLARE_INSN(tst, MATCH_TST, MASK_TST)
DECLARE_INSN(tst, MATCH_TST, (MASK_TST | (1U << 25)), match_opcode)
DECLARE_INSN(srriw, MATCH_SRRIW, MASK_SRRIW)
DECLARE_INSN(srri, MATCH_SRRI, MASK_SRRI)
DECLARE_INSN(addsl, MATCH_ADDSL, MASK_ADDSL)
DECLARE_INSN(lwd, MATCH_LWD, MASK_LWD)
DECLARE_INSN(ldd, MATCH_LDD, MASK_LDD)
DECLARE_INSN(swd, MATCH_SWD, MASK_SWD)
DECLARE_INSN(sdd, MATCH_SDD, MASK_SDD)
DECLARE_INSN(sdia, MATCH_SDIA, MASK_SDIA)
DECLARE_INSN(sdib, MATCH_SDIB, MASK_SDIB)
DECLARE_INSN(lwud, MATCH_LWUD, MASK_LWUD)
DECLARE_INSN(lwud, MATCH_LWUD, MASK_LWUD)
DECLARE_INSN(swia, MATCH_SWIA, MASK_SWIA)
DECLARE_INSN(swib, MATCH_SWIB, MASK_SWIB)
DECLARE_INSN(shia, MATCH_SHIA, MASK_SHIA)
DECLARE_INSN(shib, MATCH_SHIB, MASK_SHIB)
DECLARE_INSN(sbia, MATCH_SBIA, MASK_SBIA)
DECLARE_INSN(sbib, MATCH_SBIB, MASK_SBIB)
DECLARE_INSN(lwuia, MATCH_LWUIA, MASK_LWUIA)
DECLARE_INSN(lwuib, MATCH_LWUIB, MASK_LWUIB)
DECLARE_INSN(lhuia, MATCH_LHUIA, MASK_LHUIA)
DECLARE_INSN(lhuib, MATCH_LHUIB, MASK_LHUIB)
DECLARE_INSN(lbuia, MATCH_LBUIA, MASK_LBUIA)
DECLARE_INSN(lbuib, MATCH_LBUIB, MASK_LBUIB)
DECLARE_INSN(ldia, MATCH_LDIA, MASK_LDIA)
DECLARE_INSN(ldib, MATCH_LDIB, MASK_LDIB)
DECLARE_INSN(lwia, MATCH_LWIA, MASK_LWIA)
DECLARE_INSN(lwib, MATCH_LWIB, MASK_LWIB)
DECLARE_INSN(lhia, MATCH_LHIA, MASK_LHIA)
DECLARE_INSN(lhib, MATCH_LHIB, MASK_LHIB)
DECLARE_INSN(lbia, MATCH_LBIA, MASK_LBIA)
DECLARE_INSN(lbib, MATCH_LBIB, MASK_LBIB)
DECLARE_INSN(fsurd, MATCH_FSURD, MASK_FSURD)
DECLARE_INSN(revw, MATCH_REVW, MASK_REVW)
DECLARE_INSN(fsurw, MATCH_FSURW, MASK_FSURW)
DECLARE_INSN(flurd, MATCH_FLURD, MASK_FLURD)
DECLARE_INSN(flurw, MATCH_FLURW, MASK_FLURW)
DECLARE_INSN(fsrd, MATCH_FSRD, MASK_FSRD)
DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
DECLARE_INSN(flrd, MATCH_FLRD, MASK_FLRD)
DECLARE_INSN(flrw, MATCH_FLRW, MASK_FLRW)
DECLARE_INSN(ipush, MATCH_IPUSH, MASK_IPUSH)
DECLARE_INSN(ipop, MATCH_IPOP, MASK_IPOP)
DECLARE_INSN(fmv.x.hw, MATCH_FMV_X_HW, MASK_FMV_X_HW)
DECLARE_INSN(fmv.hw.x, MATCH_FMV_HW_X, MASK_FMV_HW_X)
#endif /* DECLARE_INSN */
#ifdef DECLARE_CSR
/* T-HEAD M mode CSR.  */
#define CSR_MXSTATUS 0x7c0
#define CSR_MHCR 0x7c1
#define CSR_MCOR 0x7c2
#define CSR_MCCR2 0x7c3
#define CSR_MCER2 0x7c4
#define CSR_MHINT 0x7c5
#define CSR_MRMR 0x7c6
#define CSR_MRVBR 0x7c7
#define CSR_MCER 0x7c8
#define CSR_MCOUNTERWEN 0x7c9
#define CSR_MCOUNTERINTEN 0x7ca
#define CSR_MCOUNTEROF 0x7cb
#define CSR_MHINT2 0x7cc
#define CSR_MHINT3 0x7cd
#define CSR_MRADDR 0x7e0
#define CSR_MEXSTATUS 0x7e1
#define CSR_MNMICAUSE 0x7e2
#define CSR_MNMIPC 0x7e3
#define CSR_MHPMCR 0x7f0
#define CSR_MHPMSR 0x7f1
#define CSR_MHPMER 0x7f2
#define CSR_MSMPR 0x7f3
#define CSR_MTEECFG 0x7f4
#define CSR_MZONEID 0x7f5
#define CSR_ML2CPID 0x7f6
#define CSR_ML2WP 0x7f7
#define CSR_MDTCMCR 0x7f8
#define CSR_USP 0x7d1
#define CSR_MCINS 0x7d2
#define CSR_MCINDEX 0x7d3
#define CSR_MCDATA0 0x7d4
#define CSR_MCDATA1 0x7d5
#define CSR_MEICR 0x7d6
#define CSR_MEICR2 0x7d7
#define CSR_MBEADDR 0x7d8
#define CSR_MCPUID 0xfc0
#define CSR_MAPBADDR 0xfc1
#define CSR_MWMSR 0xfc2
#define CSR_MHALTCAUSE 0xfe0
#define CSR_MDBGINFO 0xfe1
#define CSR_MPCFIFO 0xfe2
/* T-HEAD S mode CSR.  */
#define CSR_SXSTATUS 0x5c0
#define CSR_SHCR 0x5c1
#define CSR_SCER2 0x5c2
#define CSR_SCER 0x5c3
#define CSR_SCOUNTERINTEN 0x5c4
#define CSR_SCOUNTEROF 0x5c5
#define CSR_SHINT 0x5c6
#define CSR_SHINT2 0x5c7
#define CSR_SHPMINHIBIT 0x5c8
#define CSR_SHPMCR 0x5c9
#define CSR_SHPMSR 0x5ca
#define CSR_SHPMER 0x5cb
#define CSR_SL2CPID 0x5cc
#define CSR_SL2WP 0x5cd
#define CSR_SBEADDR 0x5d0
#define CSR_SCYCLE 0x5e0
#define CSR_SHPMCOUNTER1 0x5e1
#define CSR_SHPMCOUNTER2 0x5e2
#define CSR_SHPMCOUNTER3 0x5e3
#define CSR_SHPMCOUNTER4 0x5e4
#define CSR_SHPMCOUNTER5 0x5e5
#define CSR_SHPMCOUNTER6 0x5e6
#define CSR_SHPMCOUNTER7 0x5e7
#define CSR_SHPMCOUNTER8 0x5e8
#define CSR_SHPMCOUNTER9 0x5e9
#define CSR_SHPMCOUNTER10 0x5ea
#define CSR_SHPMCOUNTER11 0x5eb
#define CSR_SHPMCOUNTER12 0x5ec
#define CSR_SHPMCOUNTER13 0x5ed
#define CSR_SHPMCOUNTER14 0x5ee
#define CSR_SHPMCOUNTER15 0x5ef
#define CSR_SHPMCOUNTER16 0x5f0
#define CSR_SHPMCOUNTER17 0x5f1
#define CSR_SHPMCOUNTER18 0x5f2
#define CSR_SHPMCOUNTER19 0x5f3
#define CSR_SHPMCOUNTER20 0x5f4
#define CSR_SHPMCOUNTER21 0x5f5
#define CSR_SHPMCOUNTER22 0x5f6
#define CSR_SHPMCOUNTER23 0x5f7
#define CSR_SHPMCOUNTER24 0x5f8
#define CSR_SHPMCOUNTER25 0x5f9
#define CSR_SHPMCOUNTER26 0x5fa
#define CSR_SHPMCOUNTER27 0x5fb
#define CSR_SHPMCOUNTER28 0x5fc
#define CSR_SHPMCOUNTER29 0x5fd
#define CSR_SHPMCOUNTER30 0x5fe
#define CSR_SHPMCOUNTER31 0x5ff
/* T-HEAD U mode CSR.  */
#define CSR_FXCR 0x800
/* T-HEAD MMU extentions.  */
#define CSR_SMIR 0x9c0
#define CSR_SMEL 0x9c1
#define CSR_SMEH 0x9c2
#define CSR_SMCIR 0x9c3
/* T-HEAD Security CSR(May be droped).  */
#define CSR_MEBR 0xbe0
#define CSR_NT_MSTATUS 0xbe1
#define CSR_NT_MIE 0xbe2
#define CSR_NT_MTVEC 0xbe3
#define CSR_NT_MTVT 0xbe4
#define CSR_NT_MEPC 0xbe5
#define CSR_NT_MCAUSE 0xbe6
#define CSR_NT_MIP 0xbe7
#define CSR_NT_MINTSTATE 0xbe8
#define CSR_NT_MXSTATUS 0xbe9
#define CSR_NT_MEBR 0xbea
#define CSR_NT_MSP 0xbeb
#define CSR_T_USP 0xbec
#define CSR_T_MDCR 0xbed
#define CSR_T_MPCR 0xbee
#define CSR_PMPTEECFG 0xbef
/* T-HEAD extentions.  */
DECLARE_CSR(mxstatus, CSR_MXSTATUS, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mhcr, CSR_MHCR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcor, CSR_MCOR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mccr2, CSR_MCCR2, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcer2, CSR_MCER2, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mhint, CSR_MHINT, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mrmr, CSR_MRMR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mrvbr, CSR_MRVBR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcer, CSR_MCER, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcounterwen, CSR_MCOUNTERWEN, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcounterinten, CSR_MCOUNTERINTEN, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcounterof, CSR_MCOUNTEROF, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mhint2, CSR_MHINT2, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mhint3, CSR_MHINT3, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mraddr, CSR_MRADDR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mexstatus, CSR_MEXSTATUS, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mnmicause, CSR_MNMICAUSE, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mnmipc, CSR_MNMIPC, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mhpmcr, CSR_MHPMCR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mhpmsr, CSR_MHPMSR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mhpmer, CSR_MHPMER, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(msmpr, CSR_MSMPR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mteecfg, CSR_MTEECFG, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mzoneid, CSR_MZONEID, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(ml2cpid, CSR_ML2CPID, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(ml2wp, CSR_ML2WP, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mdtcmcr, CSR_MDTCMCR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(usp, CSR_USP, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcins, CSR_MCINS, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcindex, CSR_MCINDEX, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcdata0, CSR_MCDATA0, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcdata1, CSR_MCDATA1, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(meicr, CSR_MEICR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(meicr2, CSR_MEICR2, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mbeaddr, CSR_MBEADDR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mebr, CSR_MEBR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mstatus, CSR_NT_MSTATUS, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mtvec, CSR_NT_MTVEC, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mie, CSR_NT_MIE, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mtvt, CSR_NT_MTVT, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mepc, CSR_NT_MEPC, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mcause, CSR_NT_MCAUSE, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mip, CSR_NT_MIP, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mintstate, CSR_NT_MINTSTATE, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mxstatus, CSR_NT_MXSTATUS, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_mebr, CSR_NT_MEBR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(nt_msp, CSR_NT_MSP, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(t_usp, CSR_T_USP, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(t_mdcr, CSR_T_MDCR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(t_mpcr, CSR_T_MPCR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(pmpteecfg, CSR_PMPTEECFG, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcpuid, CSR_MCPUID, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mapbaddr, CSR_MAPBADDR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mwmsr, CSR_MWMSR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(fxcr, CSR_FXCR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(smir, CSR_SMIR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(smel, CSR_SMEL, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(smeh, CSR_SMEH, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(smcir, CSR_SMCIR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(sxstatus, CSR_SXSTATUS, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shcr, CSR_SHCR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(scer2, CSR_SCER2, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(scer, CSR_SCER, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(scounterinten , CSR_SCOUNTERINTEN, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(scounterof, CSR_SCOUNTEROF, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shint, CSR_SHINT, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shint2, CSR_SHINT2, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpminhibit, CSR_SHPMINHIBIT, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcr, CSR_SHPMCR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmsr, CSR_SHPMSR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmer, CSR_SHPMER, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(sl2cpid, CSR_SL2CPID, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(sl2wp, CSR_SL2WP, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(sbeaddr, CSR_SBEADDR, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(scycle, CSR_SCYCLE, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter1, CSR_SHPMCOUNTER1, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter2, CSR_SHPMCOUNTER2, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter3, CSR_SHPMCOUNTER3, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter4, CSR_SHPMCOUNTER4, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter5, CSR_SHPMCOUNTER5, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter6, CSR_SHPMCOUNTER6, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter7, CSR_SHPMCOUNTER7, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter8, CSR_SHPMCOUNTER8, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter9, CSR_SHPMCOUNTER9, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter10, CSR_SHPMCOUNTER10, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter11, CSR_SHPMCOUNTER11, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter12, CSR_SHPMCOUNTER12, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter13, CSR_SHPMCOUNTER13, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter14, CSR_SHPMCOUNTER14, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter15, CSR_SHPMCOUNTER15, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter16, CSR_SHPMCOUNTER16, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter17, CSR_SHPMCOUNTER17, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter18, CSR_SHPMCOUNTER18, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter19, CSR_SHPMCOUNTER19, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter20, CSR_SHPMCOUNTER20, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter21, CSR_SHPMCOUNTER21, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter22, CSR_SHPMCOUNTER22, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter23, CSR_SHPMCOUNTER23, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter24, CSR_SHPMCOUNTER24, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter25, CSR_SHPMCOUNTER25, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter26, CSR_SHPMCOUNTER26, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter27, CSR_SHPMCOUNTER27, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter28, CSR_SHPMCOUNTER28, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter29, CSR_SHPMCOUNTER29, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter30, CSR_SHPMCOUNTER30, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter31, CSR_SHPMCOUNTER31, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
#endif /* DECLARE_CSR */

#ifndef __RISCV_OPC_SIFIVE_THEAD__
#define __RISCV_OPC_SIFIVE_THEAD__
/* SiFive cache control instructions.  */
#define MATCH_CFLUSH_D_L1	0xfc000073
#define MASK_CFLUSH_D_L1	0xfff07fff
#define MATCH_CDISCARD_D_L1	0xfc200073
#define MASK_CDISCARD_D_L1	0xfff07fff
#define MATCH_CFLUSH_I_L1	0xfc100073
#define MASK_CFLUSH_I_L1	0xffffffff
#endif /* __RISCV_OPC_SIFIVE_THEAD__ */