# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond # mach: frv fr500 fr400 .include "testutils.inc" start .global cmsubhss cmsubhss: set_spr_immed 0x1b1b,cccr set_fr_iimmed 0x0000,0x0000,fr10 set_fr_iimmed 0x0000,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc0,1 test_fr_limmed 0x0000,0x0000,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xdead,0x0000,fr10 set_fr_iimmed 0x0000,0xbeef,fr11 cmsubhss fr10,fr11,fr12,cc0,1 test_fr_limmed 0xdead,0x4111,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x0000,0xdead,fr10 set_fr_iimmed 0xbeef,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc0,1 test_fr_limmed 0x4111,0xdead,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0x1111,0x1111,fr11 cmsubhss fr10,fr11,fr12,cc0,1 test_fr_limmed 0x0123,0x4567,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0xffff,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc0,1 test_fr_limmed 0x1235,0x5679,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x7ffe,0x7ffe,fr10 set_fr_iimmed 0xfffe,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc4,1 test_fr_limmed 0x7fff,0x7fff,fr12 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set test_spr_bits 2,1,1,msr0 ; msr0.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0001,0x0002,fr11 cmsubhss fr10,fr11,fr12,cc4,1 test_fr_limmed 0x8000,0x8000,fr12 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set test_spr_bits 2,1,1,msr0 ; msr0.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0002,0x0001,fr11 cmsubhss fr10,fr11,fr12,cc4,1 test_fr_limmed 0x8000,0x8000,fr12 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set test_spr_bits 2,1,1,msr0 ; msr0.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0001,0x0001,fr10 set_fr_iimmed 0x8000,0x8000,fr11 cmsubhss.p fr10,fr10,fr12,cc4,1 cmsubhss fr11,fr10,fr13,cc4,1 test_fr_limmed 0x0000,0x0000,fr12 test_fr_limmed 0x8000,0x8000,fr13 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set test_spr_bits 2,1,1,msr1 ; msr1.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0000,0x0000,fr10 set_fr_iimmed 0x0000,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc1,0 test_fr_limmed 0x0000,0x0000,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xdead,0x0000,fr10 set_fr_iimmed 0x0000,0xbeef,fr11 cmsubhss fr10,fr11,fr12,cc1,0 test_fr_limmed 0xdead,0x4111,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x0000,0xdead,fr10 set_fr_iimmed 0xbeef,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc1,0 test_fr_limmed 0x4111,0xdead,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0x1111,0x1111,fr11 cmsubhss fr10,fr11,fr12,cc1,0 test_fr_limmed 0x0123,0x4567,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0xffff,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc1,0 test_fr_limmed 0x1235,0x5679,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x7ffe,0x7ffe,fr10 set_fr_iimmed 0xfffe,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc5,0 test_fr_limmed 0x7fff,0x7fff,fr12 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set test_spr_bits 2,1,1,msr0 ; msr0.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0001,0x0002,fr11 cmsubhss fr10,fr11,fr12,cc5,0 test_fr_limmed 0x8000,0x8000,fr12 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set test_spr_bits 2,1,1,msr0 ; msr0.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0002,0x0001,fr11 cmsubhss fr10,fr11,fr12,cc5,0 test_fr_limmed 0x8000,0x8000,fr12 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set test_spr_bits 2,1,1,msr0 ; msr0.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0001,0x0001,fr10 set_fr_iimmed 0x8000,0x8000,fr11 cmsubhss.p fr10,fr10,fr12,cc5,0 cmsubhss fr11,fr10,fr13,cc5,0 test_fr_limmed 0x0000,0x0000,fr12 test_fr_limmed 0x8000,0x8000,fr13 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set test_spr_bits 2,1,1,msr1 ; msr1.ovf set test_spr_bits 1,0,1,msr0 ; msr0.aovf set test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set set_fr_iimmed 0xdead,0xbeef,fr12 set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0000,0x0000,fr10 set_fr_iimmed 0x0000,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc0,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xdead,0x0000,fr10 set_fr_iimmed 0x0000,0xbeef,fr11 cmsubhss fr10,fr11,fr12,cc0,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x0000,0xdead,fr10 set_fr_iimmed 0xbeef,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc0,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0x1111,0x1111,fr11 cmsubhss fr10,fr11,fr12,cc0,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0xffff,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc0,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x7ffe,0x7ffe,fr10 set_fr_iimmed 0xfffe,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc4,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0001,0x0002,fr11 cmsubhss fr10,fr11,fr12,cc4,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0002,0x0001,fr11 cmsubhss fr10,fr11,fr12,cc4,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xbeef,0xdead,fr13 set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0001,0x0001,fr10 set_fr_iimmed 0x8000,0x8000,fr11 cmsubhss.p fr10,fr10,fr12,cc4,0 cmsubhss fr11,fr10,fr13,cc4,0 test_fr_limmed 0xdead,0xbeef,fr12 test_fr_limmed 0xbeef,0xdead,fr13 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xdead,0xbeef,fr12 set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0000,0x0000,fr10 set_fr_iimmed 0x0000,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc1,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xdead,0x0000,fr10 set_fr_iimmed 0x0000,0xbeef,fr11 cmsubhss fr10,fr11,fr12,cc1,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x0000,0xdead,fr10 set_fr_iimmed 0xbeef,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc1,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0x1111,0x1111,fr11 cmsubhss fr10,fr11,fr12,cc1,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0xffff,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc1,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x7ffe,0x7ffe,fr10 set_fr_iimmed 0xfffe,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc5,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0001,0x0002,fr11 cmsubhss fr10,fr11,fr12,cc5,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0002,0x0001,fr11 cmsubhss fr10,fr11,fr12,cc5,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xbeef,0xdead,fr13 set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0001,0x0001,fr10 set_fr_iimmed 0x8000,0x8000,fr11 cmsubhss.p fr10,fr10,fr12,cc5,1 cmsubhss fr11,fr10,fr13,cc5,1 test_fr_limmed 0xdead,0xbeef,fr12 test_fr_limmed 0xbeef,0xdead,fr13 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xdead,0xbeef,fr12 set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0000,0x0000,fr10 set_fr_iimmed 0x0000,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc2,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xdead,0x0000,fr10 set_fr_iimmed 0x0000,0xbeef,fr11 cmsubhss fr10,fr11,fr12,cc2,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x0000,0xdead,fr10 set_fr_iimmed 0xbeef,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc2,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0x1111,0x1111,fr11 cmsubhss fr10,fr11,fr12,cc2,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0xffff,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc2,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x7ffe,0x7ffe,fr10 set_fr_iimmed 0xfffe,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc6,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0001,0x0002,fr11 cmsubhss fr10,fr11,fr12,cc6,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0002,0x0001,fr11 cmsubhss fr10,fr11,fr12,cc6,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xbeef,0xdead,fr13 set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0001,0x0001,fr10 set_fr_iimmed 0x8000,0x8000,fr11 cmsubhss.p fr10,fr10,fr12,cc6,1 cmsubhss fr11,fr10,fr13,cc6,0 test_fr_limmed 0xdead,0xbeef,fr12 test_fr_limmed 0xbeef,0xdead,fr13 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set ; set_fr_iimmed 0xdead,0xbeef,fr12 set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0000,0x0000,fr10 set_fr_iimmed 0x0000,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc3,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xdead,0x0000,fr10 set_fr_iimmed 0x0000,0xbeef,fr11 cmsubhss fr10,fr11,fr12,cc3,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x0000,0xdead,fr10 set_fr_iimmed 0xbeef,0x0000,fr11 cmsubhss fr10,fr11,fr12,cc3,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0x1111,0x1111,fr11 cmsubhss fr10,fr11,fr12,cc3,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0x1234,0x5678,fr10 set_fr_iimmed 0xffff,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc3,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x7ffe,0x7ffe,fr10 set_fr_iimmed 0xfffe,0xffff,fr11 cmsubhss fr10,fr11,fr12,cc7,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0001,0x0002,fr11 cmsubhss fr10,fr11,fr12,cc7,1 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_spr_immed 0,msr0 set_fr_iimmed 0x8001,0x8001,fr10 set_fr_iimmed 0x0002,0x0001,fr11 cmsubhss fr10,fr11,fr12,cc7,0 test_fr_limmed 0xdead,0xbeef,fr12 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set set_fr_iimmed 0xbeef,0xdead,fr13 set_spr_immed 0,msr0 set_spr_immed 0,msr1 set_fr_iimmed 0x0001,0x0001,fr10 set_fr_iimmed 0x8000,0x8000,fr11 cmsubhss.p fr10,fr10,fr12,cc7,1 cmsubhss fr11,fr10,fr13,cc7,0 test_fr_limmed 0xdead,0xbeef,fr12 test_fr_limmed 0xbeef,0xdead,fr13 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear test_spr_bits 2,1,0,msr0 ; msr0.ovf not set test_spr_bits 1,0,0,msr0 ; msr0.aovf not set test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set pass