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../libiberty/libiberty.a BFD_LIB = ../bfd/libbfd.la OPCODES_LIB = ../opcodes/libopcodes.la SIM_COMMON_LIBS = \ $(BFD_LIB) \ $(OPCODES_LIB) \ $(LIBIBERTY_LIB) \ $(LIBGNU) \ $(LIBGNU_EXTRA_LIBS) GUILE = guile CGEN = "$(GUILE) -l $(cgendir)/guile.scm -s" CGENFLAGS = -v CGEN_CPU_DIR = $(cgendir)/cpu CPU_DIR = $(srcroot)/cpu CGEN_ARCHFILE = $(CPU_DIR)/$(@D).cpu CGEN_READ_SCM = $(cgendir)/sim.scm CGEN_ARCH_SCM = $(cgendir)/sim-arch.scm CGEN_CPU_SCM = $(cgendir)/sim-cpu.scm $(cgendir)/sim-model.scm CGEN_DECODE_SCM = $(cgendir)/sim-decode.scm CGEN_DESC_SCM = $(cgendir)/desc.scm $(cgendir)/desc-cpu.scm CGEN_CPU_EXTR = /extr/ CGEN_CPU_READ = /read/ CGEN_CPU_WRITE = /write/ CGEN_CPU_SEM = /sem/ CGEN_CPU_SEMSW = /semsw/ CGEN_WRAPPER = $(srccom)/cgen.sh CGEN_GEN_ARCH = \ $(SHELL) $(CGEN_WRAPPER) arch $(srcdir)/$(@D) \ $(CGEN) $(cgendir) "$(CGENFLAGS)" \ $(@D) "$$FLAGS" ignored "$$isa" $$mach ignored \ $(CGEN_ARCHFILE) ignored CGEN_GEN_CPU = \ $(SHELL) $(CGEN_WRAPPER) cpu $(srcdir)/$(@D) \ $(CGEN) $(cgendir) "$(CGENFLAGS)" \ $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ $(CGEN_ARCHFILE) "$$EXTRAFILES" CGEN_GEN_DEFS = \ $(SHELL) $(CGEN_WRAPPER) defs $(srcdir)/$(@D) \ $(CGEN) $(cgendir) "$(CGENFLAGS)" \ $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ $(CGEN_ARCHFILE) ignored CGEN_GEN_DECODE = \ $(SHELL) $(CGEN_WRAPPER) decode $(srcdir)/$(@D) \ $(CGEN) $(cgendir) "$(CGENFLAGS)" \ $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ $(CGEN_ARCHFILE) "$$EXTRAFILES" CGEN_GEN_CPU_DECODE = \ $(SHELL) $(CGEN_WRAPPER) cpu-decode $(srcdir)/$(@D) \ $(CGEN) $(cgendir) "$(CGENFLAGS)" \ $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ $(CGEN_ARCHFILE) "$$EXTRAFILES" CGEN_GEN_CPU_DESC = \ $(SHELL) $(CGEN_WRAPPER) desc $(srcdir)/$(@D) \ $(CGEN) $(cgendir) "$(CGENFLAGS)" \ $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ $(CGEN_ARCHFILE) ignored $$opcfile # igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable # leak detection while running it. IGEN = igen/igen$(EXEEXT) IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN) $(IGEN_FLAGS_SMP) igen_libigen_a_SOURCES = \ igen/table.c \ igen/lf.c \ igen/misc.c \ igen/filter_host.c \ igen/ld-decode.c \ igen/ld-cache.c \ igen/filter.c \ igen/ld-insn.c \ igen/gen-model.c \ igen/gen-itable.c \ igen/gen-icache.c \ igen/gen-semantics.c \ igen/gen-idecode.c \ igen/gen-support.c \ igen/gen-engine.c \ igen/gen.c igen_igen_SOURCES = igen/igen.c igen_igen_LDADD = igen/libigen.a igen_filter_SOURCES = igen_filter_LDADD = igen/filter-main.o igen/libigen.a igen_gen_SOURCES = igen_gen_LDADD = igen/gen-main.o igen/libigen.a igen_ld_cache_SOURCES = igen_ld_cache_LDADD = igen/ld-cache-main.o igen/libigen.a igen_ld_decode_SOURCES = igen_ld_decode_LDADD = igen/ld-decode-main.o igen/libigen.a igen_ld_insn_SOURCES = igen_ld_insn_LDADD = igen/ld-insn-main.o igen/libigen.a igen_table_SOURCES = igen_table_LDADD = igen/table-main.o igen/libigen.a igen_IGEN_TOOLS = \ $(IGEN) \ igen/filter \ igen/gen \ igen/ld-cache \ igen/ld-decode \ igen/ld-insn \ igen/table EXTRA_DEJAGNU_SITE_CONFIG = site-sim-config.exp # Custom verbose test variables that automake doesn't provide (yet?). AM_V_RUNTEST = $(AM_V_RUNTEST_@AM_V@) AM_V_RUNTEST_ = $(AM_V_RUNTEST_@AM_DEFAULT_V@) AM_V_RUNTEST_0 = @echo " RUNTEST $(RUNTESTFLAGS) $*"; AM_V_RUNTEST_1 = DO_RUNTEST = \ LC_ALL=C; export LC_ALL; \ EXPECT=${EXPECT} ; export EXPECT ; \ runtest=$(RUNTEST); \ $$runtest $(RUNTESTFLAGS) testsuite_common_CPPFLAGS = \ -I$(srcdir)/common \ -I$(srcroot)/include \ -I../bfd @SIM_ENABLE_ARCH_aarch64_TRUE@nodist_aarch64_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/modules.c @SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_aarch64_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_aarch64_TRUE@ $(patsubst %,aarch64/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_aarch64_TRUE@ $(patsubst %,aarch64/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/cpustate.o \ @SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/interp.o \ @SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/memory.o \ @SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/sim-resume.o \ @SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/simulator.o @SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_SOURCES = @SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_LDADD = \ @SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/nrun.o \ @SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/libsim.a \ @SIM_ENABLE_ARCH_aarch64_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_arm_TRUE@AM_CPPFLAGS_arm = -DMODET @SIM_ENABLE_ARCH_arm_TRUE@nodist_arm_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_arm_TRUE@ arm/modules.c @SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_arm_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_arm_TRUE@ arm/wrapper.o \ @SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu.o \ @SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu32.o arm/arminit.o arm/armos.o arm/armsupp.o \ @SIM_ENABLE_ARCH_arm_TRUE@ arm/armvirt.o arm/thumbemu.o \ @SIM_ENABLE_ARCH_arm_TRUE@ arm/armcopro.o arm/maverick.o arm/iwmmxt.o @SIM_ENABLE_ARCH_arm_TRUE@arm_run_SOURCES = @SIM_ENABLE_ARCH_arm_TRUE@arm_run_LDADD = \ @SIM_ENABLE_ARCH_arm_TRUE@ arm/nrun.o \ @SIM_ENABLE_ARCH_arm_TRUE@ arm/libsim.a \ @SIM_ENABLE_ARCH_arm_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_arm_TRUE@armdocdir = $(docdir)/arm @SIM_ENABLE_ARCH_arm_TRUE@armdoc_DATA = arm/README @SIM_ENABLE_ARCH_avr_TRUE@nodist_avr_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_avr_TRUE@ avr/modules.c @SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_avr_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_avr_TRUE@ avr/interp.o \ @SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst %,avr/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst %,avr/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_avr_TRUE@ avr/sim-resume.o @SIM_ENABLE_ARCH_avr_TRUE@avr_run_SOURCES = @SIM_ENABLE_ARCH_avr_TRUE@avr_run_LDADD = \ @SIM_ENABLE_ARCH_avr_TRUE@ avr/nrun.o \ @SIM_ENABLE_ARCH_avr_TRUE@ avr/libsim.a \ @SIM_ENABLE_ARCH_avr_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_bfin_TRUE@AM_CPPFLAGS_bfin = $(SDL_CFLAGS) @SIM_ENABLE_ARCH_bfin_TRUE@nodist_bfin_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin/modules.c @SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_bfin_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/dv-%.o,$(bfin_SIM_EXTRA_HW_DEVICES)) \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin/bfin-sim.o \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin/devices.o \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin/gui.o \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin/interp.o \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin/machs.o \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin/sim-resume.o @SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_SOURCES = @SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_LDADD = \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin/nrun.o \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin/libsim.a \ @SIM_ENABLE_ARCH_bfin_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_bfin_TRUE@bfin_SIM_EXTRA_HW_DEVICES = \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_cec \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ctimer \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_dma \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_dmac \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ebiu_amc \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ebiu_ddrc \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ebiu_sdc \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_emac \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_eppi \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_evt \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_gpio \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_gpio2 \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_gptimer \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_jtag \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_mmu \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_nfc \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_otp \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_pfmon \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_pint \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_pll \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ppi \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_rtc \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_sic \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_spi \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_trace \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_twi \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_uart \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_uart2 \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_wdog \ @SIM_ENABLE_ARCH_bfin_TRUE@ bfin_wp \ @SIM_ENABLE_ARCH_bfin_TRUE@ eth_phy @SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.c @SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_bpf_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-sim.o \ @SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-resume.o @SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES = @SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \ @SIM_ENABLE_ARCH_bpf_TRUE@ bpf/nrun.o \ @SIM_ENABLE_ARCH_bpf_TRUE@ bpf/libsim.a \ @SIM_ENABLE_ARCH_bpf_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_cr16_TRUE@nodist_cr16_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/modules.c @SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_cr16_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst %,cr16/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst %,cr16/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/interp.o \ @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/sim-resume.o \ @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/simops.o \ @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/table.o @SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_SOURCES = @SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_LDADD = \ @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/nrun.o \ @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/libsim.a \ @SIM_ENABLE_ARCH_cr16_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_cr16_TRUE@cr16_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/gencode$(EXEEXT) \ @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/table.c @SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c @SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o @SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv10f.o = -Wno-unused-but-set-variable @SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv32f.o = -Wno-unused-but-set-variable @SIM_ENABLE_ARCH_cris_TRUE@nodist_cris_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/modules.c @SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_cris_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/dv-%.o,$(cris_SIM_EXTRA_HW_DEVICES)) \ @SIM_ENABLE_ARCH_cris_TRUE@ \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-run.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-scache.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-trace.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-utils.o \ @SIM_ENABLE_ARCH_cris_TRUE@ \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/arch.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/crisv10f.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/cpuv10.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/decodev10.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/modelv10.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv10f.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/crisv32f.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/cpuv32.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/decodev32.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/modelv32.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.o \ @SIM_ENABLE_ARCH_cris_TRUE@ \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/sim-if.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/traps.o @SIM_ENABLE_ARCH_cris_TRUE@cris_run_SOURCES = @SIM_ENABLE_ARCH_cris_TRUE@cris_run_LDADD = \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/nrun.o \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/libsim.a \ @SIM_ENABLE_ARCH_cris_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_cris_TRUE@cris_SIM_EXTRA_HW_DEVICES = rv cris cris_900000xx @SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_SOURCES = cris/rvdummy.c @SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_LDADD = $(LIBIBERTY_LIB) @SIM_ENABLE_ARCH_cris_TRUE@cris_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv10f.c \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/stamp-mloop-v10f \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.c \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/stamp-mloop-v32f @SIM_ENABLE_ARCH_d10v_TRUE@nodist_d10v_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/modules.c @SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_d10v_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/interp.o \ @SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/endian.o \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/sim-resume.o \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/simops.o \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.o @SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_SOURCES = @SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_LDADD = \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/nrun.o \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/libsim.a \ @SIM_ENABLE_ARCH_d10v_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_d10v_TRUE@d10v_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/gencode$(EXEEXT) \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.c @SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_SOURCES = d10v/gencode.c @SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_LDADD = d10v/d10v-opc.o @SIM_ENABLE_ARCH_erc32_TRUE@READLINE_SRC = $(srcroot)/readline/readline @SIM_ENABLE_ARCH_erc32_TRUE@AM_CPPFLAGS_erc32 = $(READLINE_CFLAGS) \ @SIM_ENABLE_ARCH_erc32_TRUE@ -DFAST_UART @SIM_ENABLE_ARCH_erc32_TRUE@nodist_erc32_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/modules.c @SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_erc32_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/erc32.o \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/exec.o \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/float.o \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/func.o \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/help.o \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/interf.o @SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_SOURCES = @SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_LDADD = \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis.o \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/libsim.a \ @SIM_ENABLE_ARCH_erc32_TRUE@ $(SIM_COMMON_LIBS) $(READLINE_LIB) $(TERMCAP_LIB) @SIM_ENABLE_ARCH_erc32_TRUE@erc32docdir = $(docdir)/erc32 @SIM_ENABLE_ARCH_erc32_TRUE@erc32doc_DATA = erc32/README.erc32 erc32/README.gdb erc32/README.sis @SIM_ENABLE_ARCH_examples_TRUE@nodist_example_synacor_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/modules.c @SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_examples_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst %,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst %,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/interp.o \ @SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-main.o \ @SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-resume.o @SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_SOURCES = @SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_LDADD = \ @SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/nrun.o \ @SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/libsim.a \ @SIM_ENABLE_ARCH_examples_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_frv_TRUE@AM_CPPFLAGS_frv = $(SIM_FRV_TRAPDUMP_FLAGS) @SIM_ENABLE_ARCH_frv_TRUE@AM_CFLAGS_frv_memory.o = -Wno-error @SIM_ENABLE_ARCH_frv_TRUE@AM_CFLAGS_frv_sem.o = -Wno-error @SIM_ENABLE_ARCH_frv_TRUE@nodist_frv_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/modules.c @SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_frv_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst %,frv/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst %,frv/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_frv_TRUE@ \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-accfp.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-fpu.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-run.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-scache.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-trace.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-utils.o \ @SIM_ENABLE_ARCH_frv_TRUE@ \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/arch.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-par.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/cpu.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/decode.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/frv.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/mloop.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/model.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/sem.o \ @SIM_ENABLE_ARCH_frv_TRUE@ \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/cache.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/interrupts.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/memory.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/options.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/pipeline.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/profile.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr400.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr450.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr500.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr550.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/registers.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/reset.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/sim-if.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/traps.o @SIM_ENABLE_ARCH_frv_TRUE@frv_run_SOURCES = @SIM_ENABLE_ARCH_frv_TRUE@frv_run_LDADD = \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/nrun.o \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/libsim.a \ @SIM_ENABLE_ARCH_frv_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_frv_TRUE@frvdocdir = $(docdir)/frv @SIM_ENABLE_ARCH_frv_TRUE@frvdoc_DATA = frv/README @SIM_ENABLE_ARCH_frv_TRUE@frv_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/mloop.c \ @SIM_ENABLE_ARCH_frv_TRUE@ frv/stamp-mloop @SIM_ENABLE_ARCH_ft32_TRUE@nodist_ft32_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_ft32_TRUE@ ft32/modules.c @SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_ft32_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst %,ft32/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst %,ft32/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_ft32_TRUE@ ft32/interp.o \ @SIM_ENABLE_ARCH_ft32_TRUE@ ft32/sim-resume.o @SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_SOURCES = @SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_LDADD = \ @SIM_ENABLE_ARCH_ft32_TRUE@ ft32/nrun.o \ @SIM_ENABLE_ARCH_ft32_TRUE@ ft32/libsim.a \ @SIM_ENABLE_ARCH_ft32_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_h8300_TRUE@nodist_h8300_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_h8300_TRUE@ h8300/modules.c @SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_h8300_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_h8300_TRUE@ h8300/compile.o \ @SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst %,h8300/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst %,h8300/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_h8300_TRUE@ h8300/sim-resume.o @SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_SOURCES = @SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_LDADD = \ @SIM_ENABLE_ARCH_h8300_TRUE@ h8300/nrun.o \ @SIM_ENABLE_ARCH_h8300_TRUE@ h8300/libsim.a \ @SIM_ENABLE_ARCH_h8300_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_iq2000_TRUE@nodist_iq2000_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/modules.c @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_iq2000_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst %,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst %,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_iq2000_TRUE@ \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-run.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-scache.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-trace.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-utils.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/arch.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cpu.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/decode.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/iq2000.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sem.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/model.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sim-if.o @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_SOURCES = @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_LDADD = \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/nrun.o \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/libsim.a \ @SIM_ENABLE_ARCH_iq2000_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.c \ @SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/stamp-mloop @SIM_ENABLE_ARCH_lm32_TRUE@nodist_lm32_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/modules.c @SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_lm32_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \ @SIM_ENABLE_ARCH_lm32_TRUE@ \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-run.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-scache.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-trace.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-utils.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/arch.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cpu.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/decode.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sem.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/model.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/lm32.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sim-if.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/traps.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/user.o @SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_SOURCES = @SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_LDADD = \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/nrun.o \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/libsim.a \ @SIM_ENABLE_ARCH_lm32_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_lm32_TRUE@lm32_SIM_EXTRA_HW_DEVICES = lm32cpu lm32timer lm32uart @SIM_ENABLE_ARCH_lm32_TRUE@lm32_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.c \ @SIM_ENABLE_ARCH_lm32_TRUE@ lm32/stamp-mloop @SIM_ENABLE_ARCH_m32c_TRUE@AM_CPPFLAGS_m32c = -DTIMER_A @SIM_ENABLE_ARCH_m32c_TRUE@nodist_m32c_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/modules.c @SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_m32c_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/gdb-if.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/int.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/load.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/mem.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/misc.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/reg.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/srcdest.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/syscalls.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/trace.o @SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_SOURCES = @SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_LDADD = \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/main.o \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/libsim.a \ @SIM_ENABLE_ARCH_m32c_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_m32c_TRUE@m32c_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/opc2c$(EXEEXT) \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c @SIM_ENABLE_ARCH_m32c_TRUE@m32c_opc2c_SOURCES = m32c/opc2c.c # opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disable # leak detection while running it. @SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT) @SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_traps.o = -Wno-error @SIM_ENABLE_ARCH_m32r_TRUE@nodist_m32r_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.c @SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_m32r_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \ @SIM_ENABLE_ARCH_m32r_TRUE@ \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-run.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-scache.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-trace.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-utils.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/arch.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sem.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32rx.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpux.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decodex.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modelx.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r2.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu2.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode2.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model2.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sim-if.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/traps.o @SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_SOURCES = @SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_LDADD = \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/nrun.o \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/libsim.a \ @SIM_ENABLE_ARCH_m32r_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_m32r_TRUE@m32r_SIM_EXTRA_HW_DEVICES = m32r_cache m32r_uart @SIM_ENABLE_ARCH_m32r_TRUE@m32r_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.c \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.c \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop-x \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.c \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop-2 @SIM_ENABLE_ARCH_m68hc11_TRUE@AM_CPPFLAGS_m68hc11 = \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_WORD_BITSIZE=32 \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_CELL_BITSIZE=32 \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_ADDRESS_BITSIZE=32 \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_WORD_MSB=31 @SIM_ENABLE_ARCH_m68hc11_TRUE@nodist_m68hc11_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/modules.c @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interp.o \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.o \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.o \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/emulos.o \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interrupts.o \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11_sim.o \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/sim-resume.o @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_SOURCES = @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_LDADD = \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/nrun.o \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/libsim.a \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_SIM_EXTRA_HW_DEVICES = m68hc11 m68hc11sio m68hc11eepr m68hc11tim m68hc11spi nvram @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/gencode$(EXEEXT) \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.c \ @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.c @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c @SIM_ENABLE_ARCH_mcore_TRUE@nodist_mcore_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.c @SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_mcore_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o \ @SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_mcore_TRUE@ mcore/sim-resume.o @SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_SOURCES = @SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_LDADD = \ @SIM_ENABLE_ARCH_mcore_TRUE@ mcore/nrun.o \ @SIM_ENABLE_ARCH_mcore_TRUE@ mcore/libsim.a \ @SIM_ENABLE_ARCH_mcore_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_microblaze_TRUE@nodist_microblaze_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/modules.c @SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_microblaze_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/interp.o \ @SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/sim-resume.o @SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_SOURCES = @SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_LDADD = \ @SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/nrun.o \ @SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/libsim.a \ @SIM_ENABLE_ARCH_microblaze_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_mips_TRUE@AM_CPPFLAGS_mips = \ @SIM_ENABLE_ARCH_mips_TRUE@ @SIM_MIPS_SUBTARGET@ \ @SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \ @SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@ @SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_66) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_67) $(am__append_68) @SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.c @SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_mips_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/interp.o \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_GEN_OBJ) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/cp1.o \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp.o \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/mdmx.o \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-main.o \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-resume.o @SIM_ENABLE_ARCH_mips_TRUE@EXTRA_mips_libsim_a_DEPENDENCIES = $(SIM_MIPS_MULTI_OBJ) @SIM_ENABLE_ARCH_mips_TRUE@mips_run_SOURCES = @SIM_ENABLE_ARCH_mips_TRUE@mips_run_LDADD = \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/nrun.o \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/libsim.a \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_mips_TRUE@mips_SIM_EXTRA_HW_DEVICES = tx3904cpu tx3904irc tx3904tmr tx3904sio @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_IGEN_ITABLE = \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/itable.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/itable.c @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_SINGLE = \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/icache.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/icache.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/idecode.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/idecode.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/semantics.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/semantics.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/model.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/model.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/support.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/support.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/engine.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/engine.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/irun.c @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M16 = \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_icache.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_icache.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_idecode.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_idecode.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_semantics.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_semantics.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_model.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_model.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_support.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_support.c \ @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M32 = \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_icache.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_icache.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_idecode.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_idecode.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_semantics.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_semantics.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_model.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_model.c \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_support.h \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_support.c @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \ @SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) $(am__append_73) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp2.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/m16e.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/mdmx.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/micromipsdsp.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/micromips.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/mips3264r2.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/mips3264r6.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/mips3d.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/sb1.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/tx.igen \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/vr.igen @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_DC = $(srcdir)/mips/mips.dc @SIM_ENABLE_ARCH_mips_TRUE@mips_M16_DC = $(srcdir)/mips/m16.dc @SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS32_DC = $(srcdir)/mips/micromips.dc @SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS16_DC = $(srcdir)/mips/micromips16.dc @SIM_ENABLE_ARCH_mn10300_TRUE@AM_CPPFLAGS_mn10300 = \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -DPOLL_QUIT_INTERVAL=0x20 \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31 @SIM_ENABLE_ARCH_mn10300_TRUE@nodist_mn10300_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/modules.c @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_mn10300_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/irun.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(mn10300_SIM_EXTRA_HW_DEVICES)) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/interp.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/op_utils.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/sim-resume.o @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_SOURCES = @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_LDADD = \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/nrun.o \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/libsim.a \ @SIM_ENABLE_ARCH_mn10300_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_SIM_EXTRA_HW_DEVICES = mn103cpu mn103int mn103tim mn103ser mn103iop @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILT_SRC_FROM_IGEN = \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/model.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/model.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/irun.c @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_mn10300_TRUE@ $(mn10300_BUILT_SRC_FROM_IGEN) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/stamp-igen @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN = $(srcdir)/mn10300/mn10300.igen @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN_INC = mn10300/am33.igen mn10300/am33-2.igen @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_DC = $(srcdir)/mn10300/mn10300.dc @SIM_ENABLE_ARCH_moxie_TRUE@AM_CPPFLAGS_moxie = -DDTB="\"$(dtbdir)/moxie-gdb.dtb\"" @SIM_ENABLE_ARCH_moxie_TRUE@nodist_moxie_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_moxie_TRUE@ moxie/modules.c @SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_moxie_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst %,moxie/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst %,moxie/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_moxie_TRUE@ moxie/interp.o \ @SIM_ENABLE_ARCH_moxie_TRUE@ moxie/sim-resume.o @SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_SOURCES = @SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_LDADD = \ @SIM_ENABLE_ARCH_moxie_TRUE@ moxie/nrun.o \ @SIM_ENABLE_ARCH_moxie_TRUE@ moxie/libsim.a \ @SIM_ENABLE_ARCH_moxie_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_moxie_TRUE@dtbdir = $(datadir)/gdb/dtb @SIM_ENABLE_ARCH_moxie_TRUE@dtb_DATA = moxie/moxie-gdb.dtb @SIM_ENABLE_ARCH_msp430_TRUE@nodist_msp430_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_msp430_TRUE@ msp430/modules.c @SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_msp430_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst %,msp430/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst %,msp430/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_msp430_TRUE@ msp430/msp430-sim.o \ @SIM_ENABLE_ARCH_msp430_TRUE@ msp430/sim-resume.o @SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_SOURCES = @SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_LDADD = \ @SIM_ENABLE_ARCH_msp430_TRUE@ msp430/nrun.o \ @SIM_ENABLE_ARCH_msp430_TRUE@ msp430/libsim.a \ @SIM_ENABLE_ARCH_msp430_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_or1k_TRUE@AM_CPPFLAGS_or1k = -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31 @SIM_ENABLE_ARCH_or1k_TRUE@nodist_or1k_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/modules.c @SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_or1k_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_or1k_TRUE@ $(patsubst %,or1k/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_or1k_TRUE@ $(patsubst %,or1k/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_or1k_TRUE@ \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-accfp.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-fpu.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-run.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-scache.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-trace.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-utils.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/arch.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cpu.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/decode.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/mloop.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/model.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sem.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/or1k.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sim-if.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/traps.o @SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_SOURCES = @SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_LDADD = \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/nrun.o \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/libsim.a \ @SIM_ENABLE_ARCH_or1k_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_or1k_TRUE@or1kdocdir = $(docdir)/or1k @SIM_ENABLE_ARCH_or1k_TRUE@or1kdoc_DATA = or1k/README @SIM_ENABLE_ARCH_or1k_TRUE@or1k_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/mloop.c \ @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/stamp-mloop @SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_SOURCES = @SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_LDADD = \ @SIM_ENABLE_ARCH_ppc_TRUE@ ppc/main.o \ @SIM_ENABLE_ARCH_ppc_TRUE@ ppc/libsim.a \ @SIM_ENABLE_ARCH_ppc_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_ppc_TRUE@ppcdocdir = $(docdir)/ppc @SIM_ENABLE_ARCH_ppc_TRUE@ppcdoc_DATA = ppc/BUGS ppc/INSTALL ppc/README ppc/RUN @SIM_ENABLE_ARCH_pru_TRUE@nodist_pru_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_pru_TRUE@ pru/modules.c @SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_pru_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_pru_TRUE@ pru/interp.o \ @SIM_ENABLE_ARCH_pru_TRUE@ pru/sim-resume.o @SIM_ENABLE_ARCH_pru_TRUE@pru_run_SOURCES = @SIM_ENABLE_ARCH_pru_TRUE@pru_run_LDADD = \ @SIM_ENABLE_ARCH_pru_TRUE@ pru/nrun.o \ @SIM_ENABLE_ARCH_pru_TRUE@ pru/libsim.a \ @SIM_ENABLE_ARCH_pru_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_riscv_TRUE@AM_CPPFLAGS_riscv = -DWITH_TARGET_WORD_BITSIZE=$(SIM_RISCV_BITSIZE) @SIM_ENABLE_ARCH_riscv_TRUE@nodist_riscv_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_riscv_TRUE@ riscv/modules.c @SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_riscv_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_riscv_TRUE@ riscv/interp.o \ @SIM_ENABLE_ARCH_riscv_TRUE@ riscv/machs.o \ @SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-main.o \ @SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-resume.o @SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_SOURCES = @SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_LDADD = \ @SIM_ENABLE_ARCH_riscv_TRUE@ riscv/nrun.o \ @SIM_ENABLE_ARCH_riscv_TRUE@ riscv/libsim.a \ @SIM_ENABLE_ARCH_riscv_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_rl78_TRUE@nodist_rl78_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_rl78_TRUE@ rl78/modules.c @SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_rl78_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_rl78_TRUE@ rl78/load.o \ @SIM_ENABLE_ARCH_rl78_TRUE@ rl78/mem.o \ @SIM_ENABLE_ARCH_rl78_TRUE@ rl78/cpu.o \ @SIM_ENABLE_ARCH_rl78_TRUE@ rl78/rl78.o \ @SIM_ENABLE_ARCH_rl78_TRUE@ rl78/gdb-if.o \ @SIM_ENABLE_ARCH_rl78_TRUE@ rl78/trace.o @SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_SOURCES = @SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_LDADD = \ @SIM_ENABLE_ARCH_rl78_TRUE@ rl78/main.o \ @SIM_ENABLE_ARCH_rl78_TRUE@ rl78/libsim.a \ @SIM_ENABLE_ARCH_rl78_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_rx_TRUE@AM_CPPFLAGS_rx = $(SIM_RX_CYCLE_ACCURATE_FLAGS) @SIM_ENABLE_ARCH_rx_TRUE@nodist_rx_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/modules.c @SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_rx_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/fpu.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/load.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/mem.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/misc.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/reg.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/rx.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/syscalls.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/trace.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/gdb-if.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/err.o @SIM_ENABLE_ARCH_rx_TRUE@rx_run_SOURCES = @SIM_ENABLE_ARCH_rx_TRUE@rx_run_LDADD = \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/main.o \ @SIM_ENABLE_ARCH_rx_TRUE@ rx/libsim.a \ @SIM_ENABLE_ARCH_rx_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_rx_TRUE@rxdocdir = $(docdir)/rx @SIM_ENABLE_ARCH_rx_TRUE@rxdoc_DATA = rx/README.txt @SIM_ENABLE_ARCH_sh_TRUE@nodist_sh_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/modules.c @SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_sh_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/interp.o \ @SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst %,sh/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst %,sh/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/table.o @SIM_ENABLE_ARCH_sh_TRUE@sh_run_SOURCES = @SIM_ENABLE_ARCH_sh_TRUE@sh_run_LDADD = \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/nrun.o \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/libsim.a \ @SIM_ENABLE_ARCH_sh_TRUE@ $(SIM_COMMON_LIBS) @SIM_ENABLE_ARCH_sh_TRUE@sh_BUILD_OUTPUTS = \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/gencode$(EXEEXT) \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/table.c @SIM_ENABLE_ARCH_sh_TRUE@sh_gencode_SOURCES = sh/gencode.c @SIM_ENABLE_ARCH_v850_TRUE@AM_CPPFLAGS_v850 = -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31 @SIM_ENABLE_ARCH_v850_TRUE@nodist_v850_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/modules.c @SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_v850_TRUE@ $(common_libcommon_a_SOURCES) @SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_LIBADD = \ @SIM_ENABLE_ARCH_v850_TRUE@ $(patsubst %,v850/%,$(SIM_NEW_COMMON_OBJS)) \ @SIM_ENABLE_ARCH_v850_TRUE@ $(patsubst %,v850/dv-%.o,$(SIM_HW_DEVICES)) \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/simops.o \ @SIM_ENABLE_ARCH_v850_TRUE@ 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@true @SIM_ENABLE_ARCH_frv_TRUE@frv/stamp-mloop: $(srccom)/genmloop.sh frv/mloop.in @SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \ @SIM_ENABLE_ARCH_frv_TRUE@ -mono -scache -parallel-generic-write -parallel-only \ @SIM_ENABLE_ARCH_frv_TRUE@ -cpu frvbf \ @SIM_ENABLE_ARCH_frv_TRUE@ -infile $(srcdir)/frv/mloop.in -outfile-prefix frv/ @SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/eng.hin frv/eng.h @SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/mloop.cin frv/mloop.c @SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_frv_TRUE@frv/cgen: frv/cgen-arch frv/cgen-cpu-decode @SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-arch: @SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache"; $(CGEN_GEN_ARCH) @SIM_ENABLE_ARCH_frv_TRUE@$(srcdir)/frv/arch.h $(srcdir)/frv/arch.c $(srcdir)/frv/cpuall.h: @CGEN_MAINT@ frv/cgen-arch @SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode: @SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE) @SIM_ENABLE_ARCH_frv_TRUE@$(srcdir)/frv/cpu.h $(srcdir)/frv/sem.c $(srcdir)/frv/model.c $(srcdir)/frv/decode.c $(srcdir)/frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode @SIM_ENABLE_ARCH_ft32_TRUE@$(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD): ft32/hw-config.h @SIM_ENABLE_ARCH_ft32_TRUE@ft32/modules.o: ft32/modules.c @SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_ft32_TRUE@-@am__include@ ft32/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_h8300_TRUE@$(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIBADD): h8300/hw-config.h @SIM_ENABLE_ARCH_h8300_TRUE@h8300/modules.o: h8300/modules.c @SIM_ENABLE_ARCH_h8300_TRUE@h8300/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_h8300_TRUE@-@am__include@ h8300/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_iq2000_TRUE@$(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_LIBADD): iq2000/hw-config.h @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.o: iq2000/modules.c @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_iq2000_TRUE@-@am__include@ iq2000/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c: | $(iq2000_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop: $(srccom)/genmloop.sh iq2000/mloop.in @SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \ @SIM_ENABLE_ARCH_iq2000_TRUE@ -mono -fast -pbb -switch sem-switch.c \ @SIM_ENABLE_ARCH_iq2000_TRUE@ -cpu iq2000bf \ @SIM_ENABLE_ARCH_iq2000_TRUE@ -infile $(srcdir)/iq2000/mloop.in -outfile-prefix iq2000/ @SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/eng.hin iq2000/eng.h @SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/mloop.cin iq2000/mloop.c @SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen: iq2000/cgen-arch iq2000/cgen-cpu-decode @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-arch: @SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)mach=iq2000 FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH) @SIM_ENABLE_ARCH_iq2000_TRUE@$(srcdir)/iq2000/arch.h $(srcdir)/iq2000/arch.c $(srcdir)/iq2000/cpuall.h: @CGEN_MAINT@ iq2000/cgen-arch @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-cpu-decode: @SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)cpu=iq2000bf mach=iq2000 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) @SIM_ENABLE_ARCH_iq2000_TRUE@$(srcdir)/iq2000/cpu.h $(srcdir)/iq2000/sem.c $(srcdir)/iq2000/sem-switch.c $(srcdir)/iq2000/model.c $(srcdir)/iq2000/decode.c $(srcdir)/iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-cpu-decode @SIM_ENABLE_ARCH_lm32_TRUE@$(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD): lm32/hw-config.h @SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.o: lm32/modules.c @SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_lm32_TRUE@-@am__include@ lm32/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.c: | $(lm32_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_lm32_TRUE@lm32/mloop.c lm32/eng.h: lm32/stamp-mloop ; @true @SIM_ENABLE_ARCH_lm32_TRUE@lm32/stamp-mloop: $(srccom)/genmloop.sh lm32/mloop.in @SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \ @SIM_ENABLE_ARCH_lm32_TRUE@ -mono -fast -pbb -switch sem-switch.c \ @SIM_ENABLE_ARCH_lm32_TRUE@ -cpu lm32bf \ @SIM_ENABLE_ARCH_lm32_TRUE@ -infile $(srcdir)/lm32/mloop.in -outfile-prefix lm32/ @SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/eng.hin lm32/eng.h @SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/mloop.cin lm32/mloop.c @SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen: lm32/cgen-arch lm32/cgen-cpu-decode @SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-arch: @SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH) @SIM_ENABLE_ARCH_lm32_TRUE@$(srcdir)/lm32/arch.h $(srcdir)/lm32/arch.c $(srcdir)/lm32/cpuall.h: @CGEN_MAINT@ lm32/cgen-arch @SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-cpu-decode: @SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)cpu=lm32bf mach=lm32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) @SIM_ENABLE_ARCH_lm32_TRUE@$(srcdir)/lm32/cpu.h $(srcdir)/lm32/sem.c $(srcdir)/lm32/sem-switch.c $(srcdir)/lm32/model.c $(srcdir)/lm32/decode.c $(srcdir)/lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode @SIM_ENABLE_ARCH_m32c_TRUE@$(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD): m32c/hw-config.h @SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.o: m32c/modules.c @SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_m32c_TRUE@-@am__include@ m32c/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.c: | $(m32c_BUILD_OUTPUTS) # These rules are copied from automake, but tweaked to use FOR_BUILD variables. @SIM_ENABLE_ARCH_m32c_TRUE@m32c/opc2c$(EXEEXT): $(m32c_opc2c_OBJECTS) $(m32c_opc2c_DEPENDENCIES) m32c/$(am__dirstamp) @SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(m32c_opc2c_OBJECTS) $(m32c_opc2c_LDADD) # opc2c is a build-time only tool. Override the default rules for it. @SIM_ENABLE_ARCH_m32c_TRUE@m32c/opc2c.o: m32c/opc2c.c @SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ @SIM_ENABLE_ARCH_m32c_TRUE@m32c/m32c.c: m32c/m32c.opc m32c/opc2c$(EXEEXT) @SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_GEN)$(m32c_OPC2C_RUN) -l $@.log $< > $@.tmp @SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)mv $@.tmp $@ @SIM_ENABLE_ARCH_m32c_TRUE@m32c/r8c.c: m32c/r8c.opc m32c/opc2c$(EXEEXT) @SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_GEN)$(m32c_OPC2C_RUN) -l $@.log $< > $@.tmp @SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)mv $@.tmp $@ @SIM_ENABLE_ARCH_m32r_TRUE@$(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD): m32r/hw-config.h @SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.o: m32r/modules.c @SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_m32r_TRUE@-@am__include@ m32r/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c: | $(m32r_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h: m32r/stamp-mloop ; @true @SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop: $(srccom)/genmloop.sh m32r/mloop.in @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \ @SIM_ENABLE_ARCH_m32r_TRUE@ -mono -fast -pbb -switch sem-switch.c \ @SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rbf \ @SIM_ENABLE_ARCH_m32r_TRUE@ -infile $(srcdir)/m32r/mloop.in -outfile-prefix m32r/ @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng.hin m32r/eng.h @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop.cin m32r/mloop.c @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloopx.c m32r/engx.h: m32r/stamp-mloop-x ; @true @SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-x: $(srccom)/genmloop.sh m32r/mloop.in @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \ @SIM_ENABLE_ARCH_m32r_TRUE@ -mono -no-fast -pbb -parallel-write -switch semx-switch.c \ @SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rxf \ @SIM_ENABLE_ARCH_m32r_TRUE@ -infile $(srcdir)/m32r/mloopx.in -outfile-prefix m32r/ -outfile-suffix x @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/engx.hin m32r/engx.h @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloopx.cin m32r/mloopx.c @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop2.c m32r/eng2.h: m32r/stamp-mloop-2 ; @true @SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-2: $(srccom)/genmloop.sh m32r/mloop.in @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \ @SIM_ENABLE_ARCH_m32r_TRUE@ -mono -no-fast -pbb -parallel-write -switch sem2-switch.c \ @SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32r2f \ @SIM_ENABLE_ARCH_m32r_TRUE@ -infile $(srcdir)/m32r/mloop2.in -outfile-prefix m32r/ -outfile-suffix 2 @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng2.hin m32r/eng2.h @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop2.cin m32r/mloop2.c @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen: m32r/cgen-arch m32r/cgen-cpu-decode m32r/cgen-cpu-decode-x m32r/cgen-cpu-decode-2 @SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-arch: @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH) @SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/arch.h $(srcdir)/m32r/arch.c $(srcdir)/m32r/cpuall.h: @CGEN_MAINT@ m32r/cgen-arch @SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode: @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32rbf mach=m32r FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) @SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpu.h $(srcdir)/m32r/sem.c $(srcdir)/m32r/sem-switch.c $(srcdir)/m32r/model.c $(srcdir)/m32r/decode.c $(srcdir)/m32r/decode.h: @CGEN_MAINT@ m32r/cgen-cpu-decode @SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-x: @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) @SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpux.h $(srcdir)/m32r/semx-switch.c $(srcdir)/m32r/modelx.c $(srcdir)/m32r/decodex.c $(srcdir)/m32r/decodex.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-x @SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-2: @SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32r2f mach=m32r2 SUFFIX=2 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) @SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpu2.h $(srcdir)/m32r/sem2-switch.c $(srcdir)/m32r/model2.c $(srcdir)/m32r/decode2.c $(srcdir)/m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2 @SIM_ENABLE_ARCH_m68hc11_TRUE@$(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD): m68hc11/hw-config.h @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.o: m68hc11/modules.c @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_m68hc11_TRUE@-@am__include@ m68hc11/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.c: | $(m68hc11_BUILD_OUTPUTS) # These rules are copied from automake, but tweaked to use FOR_BUILD variables. @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/gencode$(EXEEXT): $(m68hc11_gencode_OBJECTS) $(m68hc11_gencode_DEPENDENCIES) m68hc11/$(am__dirstamp) @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(m68hc11_gencode_OBJECTS) $(m68hc11_gencode_LDADD) # gencode is a build-time only tool. Override the default rules for it. @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/gencode.o: m68hc11/gencode.c @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc11int.c: m68hc11/gencode$(EXEEXT) @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_GEN)$< -m6811 >$@ @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc12int.c: m68hc11/gencode$(EXEEXT) @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_GEN)$< -m6812 >$@ @SIM_ENABLE_ARCH_mcore_TRUE@$(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD): mcore/hw-config.h @SIM_ENABLE_ARCH_mcore_TRUE@mcore/modules.o: mcore/modules.c @SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_mcore_TRUE@-@am__include@ mcore/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_microblaze_TRUE@$(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_LIBADD): microblaze/hw-config.h @SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/modules.o: microblaze/modules.c @SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_microblaze_TRUE@-@am__include@ microblaze/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_mips_TRUE@$(mips_libsim_a_OBJECTS) $(mips_libsim_a_LIBADD): mips/hw-config.h @SIM_ENABLE_ARCH_mips_TRUE@mips/modules.o: mips/modules.c @SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_mips_TRUE@-@am__include@ mips/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_mips_TRUE@mips/modules.c: | $(mips_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_IGEN_ITABLE): mips/stamp-igen-itable @SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE): mips/stamp-gen-mode-single @SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16): mips/stamp-gen-mode-m16-m16 @SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32): mips/stamp-gen-mode-m16-m32 @SIM_ENABLE_ARCH_mips_TRUE@$(SIM_MIPS_MULTI_SRC): mips/stamp-gen-mode-multi-igen mips/stamp-gen-mode-multi-run @SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-igen-itable: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(IGEN) @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ @SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ @SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ @SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ @SIM_ENABLE_ARCH_mips_TRUE@ -Wnowidth \ @SIM_ENABLE_ARCH_mips_TRUE@ -Wnounimplemented \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_IGEN_ITABLE_FLAGS) \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ @SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ @SIM_ENABLE_ARCH_mips_TRUE@ -n itable.h -ht mips/itable.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n itable.c -t mips/itable.c @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-single: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(IGEN) @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ @SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ @SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ @SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_SINGLE_FLAGS) \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ @SIM_ENABLE_ARCH_mips_TRUE@ -B 32 \ @SIM_ENABLE_ARCH_mips_TRUE@ -H 31 \ @SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ @SIM_ENABLE_ARCH_mips_TRUE@ -o $(mips_IGEN_DC) \ @SIM_ENABLE_ARCH_mips_TRUE@ -x \ @SIM_ENABLE_ARCH_mips_TRUE@ -n icache.h -hc mips/icache.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n icache.c -c mips/icache.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n semantics.h -hs mips/semantics.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n semantics.c -s mips/semantics.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n idecode.h -hd mips/idecode.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n idecode.c -d mips/idecode.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n model.h -hm mips/model.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n model.c -m mips/model.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n support.h -hf mips/support.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n support.c -f mips/support.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n engine.h -he mips/engine.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n engine.c -e mips/engine.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n irun.c -r mips/irun.c @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-m16-m16: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_M16_DC) $(IGEN) @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ @SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ @SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ @SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_M16_FLAGS) \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ @SIM_ENABLE_ARCH_mips_TRUE@ -B 16 \ @SIM_ENABLE_ARCH_mips_TRUE@ -H 15 \ @SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ @SIM_ENABLE_ARCH_mips_TRUE@ -o $(mips_M16_DC) \ @SIM_ENABLE_ARCH_mips_TRUE@ -P m16_ \ @SIM_ENABLE_ARCH_mips_TRUE@ -x \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_icache.h -hc mips/m16_icache.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_icache.c -c mips/m16_icache.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_semantics.h -hs mips/m16_semantics.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_semantics.c -s mips/m16_semantics.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_idecode.h -hd mips/m16_idecode.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_idecode.c -d mips/m16_idecode.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_model.h -hm mips/m16_model.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_model.c -m mips/m16_model.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_support.h -hf mips/m16_support.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m16_support.c -f mips/m16_support.c @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-m16-m32: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(IGEN) @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ @SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ @SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ @SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_SINGLE_FLAGS) \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ @SIM_ENABLE_ARCH_mips_TRUE@ -B 32 \ @SIM_ENABLE_ARCH_mips_TRUE@ -H 31 \ @SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ @SIM_ENABLE_ARCH_mips_TRUE@ -o $(mips_IGEN_DC) \ @SIM_ENABLE_ARCH_mips_TRUE@ -P m32_ \ @SIM_ENABLE_ARCH_mips_TRUE@ -x \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_icache.h -hc mips/m32_icache.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_icache.c -c mips/m32_icache.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_semantics.h -hs mips/m32_semantics.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_semantics.c -s mips/m32_semantics.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_idecode.h -hd mips/m32_idecode.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_idecode.c -d mips/m32_idecode.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_model.h -hm mips/m32_model.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_model.c -m mips/m32_model.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_support.h -hf mips/m32_support.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n m32_support.c -f mips/m32_support.c @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-multi-igen: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(mips_M16_DC) $(mips_MICROMIPS32_DC) $(mips_MICROMIPS16_DC) $(IGEN) @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)\ @SIM_ENABLE_ARCH_mips_TRUE@ for t in $(SIM_MIPS_MULTI_IGEN_CONFIGS); do \ @SIM_ENABLE_ARCH_mips_TRUE@ p=`echo $${t} | sed -e 's/:.*//'` ; \ @SIM_ENABLE_ARCH_mips_TRUE@ m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \ @SIM_ENABLE_ARCH_mips_TRUE@ f=`echo $${t} | sed -e 's/.*://'` ; \ @SIM_ENABLE_ARCH_mips_TRUE@ case $${p} in \ @SIM_ENABLE_ARCH_mips_TRUE@ micromips16*) \ @SIM_ENABLE_ARCH_mips_TRUE@ e="-B 16 -H 15 -o $(mips_MICROMIPS16_DC) -F 16" ;; \ @SIM_ENABLE_ARCH_mips_TRUE@ micromips32* | micromips64*) \ @SIM_ENABLE_ARCH_mips_TRUE@ e="-B 32 -H 31 -o $(mips_MICROMIPS32_DC) -F $${f}" ;; \ @SIM_ENABLE_ARCH_mips_TRUE@ micromips_m32*) \ @SIM_ENABLE_ARCH_mips_TRUE@ e="-B 32 -H 31 -o $(mips_IGEN_DC) -F $${f}"; \ @SIM_ENABLE_ARCH_mips_TRUE@ m="mips32r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \ @SIM_ENABLE_ARCH_mips_TRUE@ micromips_m64*) \ @SIM_ENABLE_ARCH_mips_TRUE@ e="-B 32 -H 31 -o $(mips_IGEN_DC) -F $${f}"; \ @SIM_ENABLE_ARCH_mips_TRUE@ m="mips64r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \ @SIM_ENABLE_ARCH_mips_TRUE@ m16*) \ @SIM_ENABLE_ARCH_mips_TRUE@ e="-B 16 -H 15 -o $(mips_M16_DC) -F 16" ;; \ @SIM_ENABLE_ARCH_mips_TRUE@ *) \ @SIM_ENABLE_ARCH_mips_TRUE@ e="-B 32 -H 31 -o $(mips_IGEN_DC) -F $${f}" ;; \ @SIM_ENABLE_ARCH_mips_TRUE@ esac; \ @SIM_ENABLE_ARCH_mips_TRUE@ $(IGEN_RUN) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ @SIM_ENABLE_ARCH_mips_TRUE@ $${e} \ @SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ @SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ @SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ @SIM_ENABLE_ARCH_mips_TRUE@ -M $${m} \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ @SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ @SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ @SIM_ENABLE_ARCH_mips_TRUE@ -P $${p}_ \ @SIM_ENABLE_ARCH_mips_TRUE@ -x \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_icache.h -hc mips/$${p}_icache.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_icache.c -c mips/$${p}_icache.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_semantics.h -hs mips/$${p}_semantics.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_semantics.c -s mips/$${p}_semantics.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_idecode.h -hd mips/$${p}_idecode.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_idecode.c -d mips/$${p}_idecode.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_model.h -hm mips/$${p}_model.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_model.c -m mips/$${p}_model.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_support.h -hf mips/$${p}_support.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_support.c -f mips/$${p}_support.c \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_engine.h -he mips/$${p}_engine.h \ @SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_engine.c -e mips/$${p}_engine.c \ @SIM_ENABLE_ARCH_mips_TRUE@ || exit; \ @SIM_ENABLE_ARCH_mips_TRUE@ done @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-multi-run: mips/m16run.c mips/micromipsrun.c @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)\ @SIM_ENABLE_ARCH_mips_TRUE@ for t in $(SIM_MIPS_MULTI_IGEN_CONFIGS); do \ @SIM_ENABLE_ARCH_mips_TRUE@ case $${t} in \ @SIM_ENABLE_ARCH_mips_TRUE@ m16*) \ @SIM_ENABLE_ARCH_mips_TRUE@ m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \ @SIM_ENABLE_ARCH_mips_TRUE@ o=mips/m16$${m}_run.c; \ @SIM_ENABLE_ARCH_mips_TRUE@ sed < $(srcdir)/mips/m16run.c > $$o.tmp \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/^sim_/m16$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "/include/s/sim-engine/m16$${m}_engine/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/m16_/m16$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/m32_/m32$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ || exit 1; \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SHELL) $(srcroot)/move-if-change $$o.tmp $$o; \ @SIM_ENABLE_ARCH_mips_TRUE@ ;;\ @SIM_ENABLE_ARCH_mips_TRUE@ micromips32*) \ @SIM_ENABLE_ARCH_mips_TRUE@ m=`echo $${t} | sed -e 's/^micromips32//' -e 's/:.*//'`; \ @SIM_ENABLE_ARCH_mips_TRUE@ o=mips/micromips$${m}_run.c; \ @SIM_ENABLE_ARCH_mips_TRUE@ sed < $(srcdir)/mips/micromipsrun.c > $$o.tmp \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/^sim_/micromips32$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "/include/s/sim-engine/micromips32$${m}_engine/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/micromips16_/micromips16$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/micromips32_/micromips32$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/m32_/m32$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ || exit 1; \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SHELL) $(srcroot)/move-if-change $$o.tmp $$o; \ @SIM_ENABLE_ARCH_mips_TRUE@ ;;\ @SIM_ENABLE_ARCH_mips_TRUE@ micromips64*) \ @SIM_ENABLE_ARCH_mips_TRUE@ m=`echo $${t} | sed -e 's/^micromips64//' -e 's/:.*//'`; \ @SIM_ENABLE_ARCH_mips_TRUE@ o=mips/micromips$${m}_run.c; \ @SIM_ENABLE_ARCH_mips_TRUE@ sed < $(srcdir)/mips/micromipsrun.c > $$o.tmp \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/^sim_/micromips64$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "/include/s/sim-engine/micromips64$${m}_engine/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/micromips16_/micromips16$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/micromips32_/micromips64$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ -e "s/m32_/m64$${m}_/" \ @SIM_ENABLE_ARCH_mips_TRUE@ || exit 1; \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SHELL) $(srcroot)/move-if-change $$o.tmp $$o; \ @SIM_ENABLE_ARCH_mips_TRUE@ ;;\ @SIM_ENABLE_ARCH_mips_TRUE@ esac \ @SIM_ENABLE_ARCH_mips_TRUE@ done @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_libsim_a_OBJECTS) $(mn10300_libsim_a_LIBADD): mn10300/hw-config.h @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.o: mn10300/modules.c @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_mn10300_TRUE@-@am__include@ mn10300/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.c: | $(mn10300_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_BUILT_SRC_FROM_IGEN): mn10300/stamp-igen @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/stamp-igen: $(mn10300_IGEN_INSN) $(mn10300_IGEN_INSN_INC) $(mn10300_IGEN_DC) $(IGEN) @SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ $(mn10300_IGEN_TRACE) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -G gen-direct-access \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -M mn10300,am33 -G gen-multi-sim=am33 \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -M am33_2 \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -I $(srcdir)/mn10300 \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -i $(mn10300_IGEN_INSN) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -o $(mn10300_IGEN_DC) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -x \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n icache.h -hc mn10300/icache.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n icache.c -c mn10300/icache.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n semantics.h -hs mn10300/semantics.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n semantics.c -s mn10300/semantics.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n idecode.h -hd mn10300/idecode.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n idecode.c -d mn10300/idecode.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n model.h -hm mn10300/model.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n model.c -m mn10300/model.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n support.h -hf mn10300/support.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n support.c -f mn10300/support.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n itable.h -ht mn10300/itable.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n itable.c -t mn10300/itable.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n engine.h -he mn10300/engine.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n engine.c -e mn10300/engine.c \ @SIM_ENABLE_ARCH_mn10300_TRUE@ -n irun.c -r mn10300/irun.c @SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_moxie_TRUE@$(moxie_libsim_a_OBJECTS) $(moxie_libsim_a_LIBADD): moxie/hw-config.h @SIM_ENABLE_ARCH_moxie_TRUE@moxie/modules.o: moxie/modules.c @SIM_ENABLE_ARCH_moxie_TRUE@moxie/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_moxie_TRUE@-@am__include@ moxie/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_moxie_TRUE@moxie/moxie-gdb.dtb: @MAINT@ moxie/moxie-gdb.dts moxie/$(am__dirstamp) @SIM_ENABLE_ARCH_moxie_TRUE@ $(AM_V_GEN) \ @SIM_ENABLE_ARCH_moxie_TRUE@ if test "x$(DTC)" != x; then \ @SIM_ENABLE_ARCH_moxie_TRUE@ $(DTC) -O dtb -o $@.tmp ${srcdir}/moxie/moxie-gdb.dts || exit 1; \ @SIM_ENABLE_ARCH_moxie_TRUE@ $(SHELL) $(srcroot)/move-if-change $@.tmp ${srcdir}/moxie/moxie-gdb.dtb || exit 1; \ @SIM_ENABLE_ARCH_moxie_TRUE@ touch ${srcdir}/moxie/moxie-gdb.dtb; \ @SIM_ENABLE_ARCH_moxie_TRUE@ else \ @SIM_ENABLE_ARCH_moxie_TRUE@ echo "Could not update the moxie-gdb.dtb file because the device "; \ @SIM_ENABLE_ARCH_moxie_TRUE@ echo "tree compiler tool (dtc) is missing. Install the tool to "; \ @SIM_ENABLE_ARCH_moxie_TRUE@ echo "update the device tree blob."; \ @SIM_ENABLE_ARCH_moxie_TRUE@ fi @SIM_ENABLE_ARCH_msp430_TRUE@$(msp430_libsim_a_OBJECTS) $(msp430_libsim_a_LIBADD): msp430/hw-config.h @SIM_ENABLE_ARCH_msp430_TRUE@msp430/modules.o: msp430/modules.c @SIM_ENABLE_ARCH_msp430_TRUE@msp430/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_msp430_TRUE@-@am__include@ msp430/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_or1k_TRUE@$(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_LIBADD): or1k/hw-config.h @SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.o: or1k/modules.c @SIM_ENABLE_ARCH_or1k_TRUE@or1k/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_or1k_TRUE@-@am__include@ or1k/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.c: | $(or1k_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_or1k_TRUE@or1k/mloop.c or1k/eng.h: or1k/stamp-mloop ; @true @SIM_ENABLE_ARCH_or1k_TRUE@or1k/stamp-mloop: $(srccom)/genmloop.sh or1k/mloop.in @SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \ @SIM_ENABLE_ARCH_or1k_TRUE@ -mono -fast -pbb -switch sem-switch.c \ @SIM_ENABLE_ARCH_or1k_TRUE@ -cpu or1k32bf \ @SIM_ENABLE_ARCH_or1k_TRUE@ -infile $(srcdir)/or1k/mloop.in -outfile-prefix or1k/ @SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/eng.hin or1k/eng.h @SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/mloop.cin or1k/mloop.c @SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen: or1k/cgen-arch or1k/cgen-cpu-decode @SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-arch: @SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)mach=or32,or32nd FLAGS="with-scache"; $(CGEN_GEN_ARCH) @SIM_ENABLE_ARCH_or1k_TRUE@$(srcdir)/or1k/arch.h $(srcdir)/or1k/arch.c $(srcdir)/or1k/cpuall.h: @CGEN_MAINT@ or1k/cgen-arch @SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-cpu-decode: @SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)cpu=or1k32bf mach=or32,or32nd FLAGS="with-scache" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) @SIM_ENABLE_ARCH_or1k_TRUE@$(srcdir)/or1k/cpu.h $(srcdir)/or1k/cpu.c $(srcdir)/or1k/model.c $(srcdir)/or1k/sem.c $(srcdir)/or1k/sem-switch.c $(srcdir)/or1k/decode.c $(srcdir)/or1k/decode.h: @CGEN_MAINT@ or1k/cgen-cpu-decode @SIM_ENABLE_ARCH_ppc_TRUE@ppc/libsim.a: common/libcommon.a @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) @SIM_ENABLE_ARCH_ppc_TRUE@ppc/%.o: ppc/%.c | ppc/libsim.a $(SIM_ALL_RECURSIVE_DEPS) @SIM_ENABLE_ARCH_ppc_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) @SIM_ENABLE_ARCH_ppc_TRUE@ppc/spreg.c: @MAINT@ ppc/ppc-spr-table ppc/spreg-gen.py ppc/$(am__dirstamp) @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --source $@.tmp @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/ppc/spreg.c @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $(srcdir)/ppc/spreg.c @SIM_ENABLE_ARCH_ppc_TRUE@ppc/spreg.h: @MAINT@ ppc/ppc-spr-table ppc/spreg-gen.py ppc/$(am__dirstamp) @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --header $@.tmp @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/ppc/spreg.h @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $(srcdir)/ppc/spreg.h @SIM_ENABLE_ARCH_pru_TRUE@$(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD): pru/hw-config.h @SIM_ENABLE_ARCH_pru_TRUE@pru/modules.o: pru/modules.c @SIM_ENABLE_ARCH_pru_TRUE@pru/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_pru_TRUE@-@am__include@ pru/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_riscv_TRUE@$(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_LIBADD): riscv/hw-config.h @SIM_ENABLE_ARCH_riscv_TRUE@riscv/modules.o: riscv/modules.c @SIM_ENABLE_ARCH_riscv_TRUE@riscv/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_riscv_TRUE@-@am__include@ riscv/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_rl78_TRUE@$(rl78_libsim_a_OBJECTS) $(rl78_libsim_a_LIBADD): rl78/hw-config.h @SIM_ENABLE_ARCH_rl78_TRUE@rl78/modules.o: rl78/modules.c @SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_rl78_TRUE@-@am__include@ rl78/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_rx_TRUE@$(rx_libsim_a_OBJECTS) $(rx_libsim_a_LIBADD): rx/hw-config.h @SIM_ENABLE_ARCH_rx_TRUE@rx/modules.o: rx/modules.c @SIM_ENABLE_ARCH_rx_TRUE@rx/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_rx_TRUE@-@am__include@ rx/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_sh_TRUE@$(sh_libsim_a_OBJECTS) $(sh_libsim_a_LIBADD): sh/hw-config.h @SIM_ENABLE_ARCH_sh_TRUE@sh/modules.o: sh/modules.c @SIM_ENABLE_ARCH_sh_TRUE@sh/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_sh_TRUE@-@am__include@ sh/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_sh_TRUE@sh/modules.c: | $(sh_BUILD_OUTPUTS) # These rules are copied from automake, but tweaked to use FOR_BUILD variables. @SIM_ENABLE_ARCH_sh_TRUE@sh/gencode$(EXEEXT): $(sh_gencode_OBJECTS) $(sh_gencode_DEPENDENCIES) sh/$(am__dirstamp) @SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(sh_gencode_OBJECTS) $(sh_gencode_LDADD) # gencode is a build-time only tool. Override the default rules for it. @SIM_ENABLE_ARCH_sh_TRUE@sh/gencode.o: sh/gencode.c @SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ @SIM_ENABLE_ARCH_sh_TRUE@sh/code.c: sh/gencode$(EXEEXT) @SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_GEN)$< -x >$@ @SIM_ENABLE_ARCH_sh_TRUE@sh/ppi.c: sh/gencode$(EXEEXT) @SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_GEN)$< -p >$@ @SIM_ENABLE_ARCH_sh_TRUE@sh/table.c: sh/gencode$(EXEEXT) @SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_GEN)$< -s >$@ @SIM_ENABLE_ARCH_v850_TRUE@$(v850_libsim_a_OBJECTS) $(v850_libsim_a_LIBADD): v850/hw-config.h @SIM_ENABLE_ARCH_v850_TRUE@v850/modules.o: v850/modules.c @SIM_ENABLE_ARCH_v850_TRUE@v850/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_v850_TRUE@-@am__include@ v850/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_v850_TRUE@v850/modules.c: | $(v850_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_v850_TRUE@$(v850_BUILT_SRC_FROM_IGEN): v850/stamp-igen @SIM_ENABLE_ARCH_v850_TRUE@v850/stamp-igen: $(v850_IGEN_INSN) $(v850_IGEN_DC) $(IGEN) @SIM_ENABLE_ARCH_v850_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ @SIM_ENABLE_ARCH_v850_TRUE@ $(v850_IGEN_TRACE) \ @SIM_ENABLE_ARCH_v850_TRUE@ -G gen-direct-access \ @SIM_ENABLE_ARCH_v850_TRUE@ -G gen-zero-r0 \ @SIM_ENABLE_ARCH_v850_TRUE@ -i $(v850_IGEN_INSN) \ @SIM_ENABLE_ARCH_v850_TRUE@ -o $(v850_IGEN_DC) \ @SIM_ENABLE_ARCH_v850_TRUE@ -x \ @SIM_ENABLE_ARCH_v850_TRUE@ -n icache.h -hc v850/icache.h \ @SIM_ENABLE_ARCH_v850_TRUE@ -n icache.c -c v850/icache.c \ @SIM_ENABLE_ARCH_v850_TRUE@ -n semantics.h -hs v850/semantics.h \ @SIM_ENABLE_ARCH_v850_TRUE@ -n semantics.c -s v850/semantics.c \ @SIM_ENABLE_ARCH_v850_TRUE@ -n idecode.h -hd v850/idecode.h \ @SIM_ENABLE_ARCH_v850_TRUE@ -n idecode.c -d v850/idecode.c \ @SIM_ENABLE_ARCH_v850_TRUE@ -n model.h -hm v850/model.h \ @SIM_ENABLE_ARCH_v850_TRUE@ -n model.c -m v850/model.c \ @SIM_ENABLE_ARCH_v850_TRUE@ -n support.h -hf v850/support.h \ @SIM_ENABLE_ARCH_v850_TRUE@ -n support.c -f v850/support.c \ @SIM_ENABLE_ARCH_v850_TRUE@ -n itable.h -ht v850/itable.h \ @SIM_ENABLE_ARCH_v850_TRUE@ -n itable.c -t v850/itable.c \ @SIM_ENABLE_ARCH_v850_TRUE@ -n engine.h -he v850/engine.h \ @SIM_ENABLE_ARCH_v850_TRUE@ -n engine.c -e v850/engine.c \ @SIM_ENABLE_ARCH_v850_TRUE@ -n irun.c -r v850/irun.c @SIM_ENABLE_ARCH_v850_TRUE@ $(AM_V_at)touch $@ all-recursive: $(SIM_ALL_RECURSIVE_DEPS) install-data-local: installdirs $(SIM_INSTALL_DATA_LOCAL_DEPS) $(AM_V_at)$(MKDIR_P) $(DESTDIR)$(libdir) lib=`echo sim | sed '$(program_transform_name)'`; \ for d in $(SIM_ENABLED_ARCHES); do \ n="$$lib"; \ [ "$(SIM_PRIMARY_TARGET)" = "$$d" ] || n="$$n-$$d"; \ n="lib$$n.a"; \ $(INSTALL_DATA) $$d/libsim.a $(DESTDIR)$(libdir)/$$n || exit 1; \ done install-exec-local: installdirs $(SIM_INSTALL_EXEC_LOCAL_DEPS) $(AM_V_at)$(MKDIR_P) $(DESTDIR)$(bindir) run=`echo run | sed '$(program_transform_name)'`; \ for d in $(SIM_ENABLED_ARCHES); do \ n="$$run"; \ [ "$(SIM_PRIMARY_TARGET)" = "$$d" ] || n="$$n-$$d"; \ $(LIBTOOL) --mode=install \ $(INSTALL_PROGRAM) $$d/run$(EXEEXT) $(DESTDIR)$(bindir)/$$n$(EXEEXT) || exit 1; \ done uninstall-local: $(SIM_UNINSTALL_LOCAL_DEPS) rm -f $(DESTDIR)$(bindir)/run $(DESTDIR)$(libdir)/libsim.a for d in $(SIM_ENABLED_ARCHES); do \ rm -f $(DESTDIR)$(bindir)/run-$$d $(DESTDIR)$(libdir)/libsim-$$d.a; \ done # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: