From a7b0384d541b6124e55c8d19e2855e91f03fc1b4 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 9 Aug 2024 08:32:54 +1000 Subject: gas: sparc: Fix faligndatai assembly and disassembly The first operand is a general register, not an fp register; the third operand is encoded into RS2, not RS3; the second operand must match the destination operand. --- opcodes/sparc-opc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'opcodes') diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c index fb7ebe3..19f7f62 100644 --- a/opcodes/sparc-opc.c +++ b/opcodes/sparc-opc.c @@ -2016,7 +2016,7 @@ SLCBCC("cbnefr", 15), { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, 0, v9a }, { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, 0, v9a }, { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a }, /* faligndatag */ -{ "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9m }, /* faligndatai */ +{ "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "1,H,B,}", 0, 0, HWCAP2_SPARC5, v9m }, /* faligndatai */ { "fzerod", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, 0, v9a }, { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, 0, v9a }, -- cgit v1.1