From d9c14a8744b01b0d3d03a661c732a4d4d5740fbc Mon Sep 17 00:00:00 2001 From: Xiao Zeng Date: Thu, 6 Jun 2024 15:59:52 +0800 Subject: RISC-V: Add support for Zvfbfmin extension This implements the Zvfbfmin extension, as of version 1.0. View detailed information in: Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfmin.d: New test. * testsuite/gas/riscv/zvfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define. (MASK_VFNCVTBF16_F_F_W): Ditto. (MATCH_VFWCVTBF16_F_F_V): Ditto. (MASK_VFWCVTBF16_F_F_V): Ditto. (DECLARE_INSN): New declarations for Zvfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFMIN opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfmin instructions. --- include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + 2 files changed, 9 insertions(+) (limited to 'include') diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ef33aeb..c5270d0 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2370,6 +2370,11 @@ #define MASK_FCVT_BF16_S 0xfff0007f #define MATCH_FCVT_S_BF16 0x40600053 #define MASK_FCVT_S_BF16 0xfff0007f +/* Zvfbfmin intructions. */ +#define MATCH_VFNCVTBF16_F_F_W 0x480e9057 +#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f +#define MATCH_VFWCVTBF16_F_F_V 0x48069057 +#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f /* Vendor-specific (CORE-V) Xcvmac instructions. */ #define MATCH_CV_MAC 0x9000302b #define MASK_CV_MAC 0xfe00707f @@ -3977,6 +3982,9 @@ DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) /* Zfbfmin instructions. */ DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S) DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) +/* Zvfbfmin instructions. */ +DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W) +DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) /* Zvbb/Zvkb instructions. */ DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index dfb8696..0641563 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -474,6 +474,7 @@ enum riscv_insn_class INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, + INSN_CLASS_ZVFBFMIN, INSN_CLASS_ZVKB, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, -- cgit v1.1