From b33f1bcd152c756c6975f874dbcf58ed3fcc9bdf Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Mon, 15 Jan 2024 09:40:11 +0000 Subject: aarch64: Add SVE2.1 Contiguous load/store instructions. Hi, This patch add support for SVE2.1 instructions ld1q, ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath. --- include/opcode/aarch64.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index de161db..189bab5 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -797,6 +797,9 @@ enum aarch64_opnd AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ + AARCH64_OPND_SME_Zt2, /* Qobule SVE vector register list. */ + AARCH64_OPND_SME_Zt3, /* Trible SVE vector register list. */ + AARCH64_OPND_SME_Zt4, /* Quad SVE vector register list. */ }; /* Qualifier constrains an operand. It either specifies a variant of an -- cgit v1.1