From ac8cb70f3690b4eace1325c7ff918dce9073da7c Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Wed, 29 Aug 2018 20:13:00 +0800 Subject: [MIPS] Add Loongson 3A1000 proccessor support. bfd/ * archures.c (bfd_architecture): Rename bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Likewise. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Likewise. (bfd_mips_isa_ext_mach): Likewise. (bfd_mips_isa_ext): Likewise. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. binutils/ * NEWS: Mention Loongson 3A1000 proccessor support. * readelf.c (get_machine_flags): Rename loongson-3a to gs464. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. elfcpp/ * mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename CPU_LOONGSON_3A to CPU_GS464. (mips_cpu_info_table): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * doc/as.texi (march table): Rename loongson3a to gs464. * testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension" flag to None. gold/ * mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach): Rename loongson3a to gs464. (mips_isa_ext_mach, mips_isa_ext): Delete loongson3a. (infer_abiflags): Use ases instead of isa_ext for infer ABI flags. (elf_mips_mach_name): Rename loongson3a to gs464. include/ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A. * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A. (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464. * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a to gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * mips-opc.c (mips_opcodes): Change Comments. --- include/ChangeLog | 9 +++++++++ include/elf/mips.h | 3 +-- include/opcode/mips.h | 9 ++------- 3 files changed, 12 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/ChangeLog b/include/ChangeLog index baeb718..1a516ab 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,14 @@ 2018-08-29 Chenghua Xu + * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to + E_MIPS_MACH_GS464. + (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A. + * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A. + (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464. + * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case. + +2018-08-29 Chenghua Xu + * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2. * opcode/mips.h (ASE_LOONGSON_EXT2): New macro. diff --git a/include/elf/mips.h b/include/elf/mips.h index 983275a..db24080 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -299,7 +299,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) #define E_MIPS_MACH_9000 0x00990000 #define E_MIPS_MACH_LS2E 0x00A00000 #define E_MIPS_MACH_LS2F 0x00A10000 -#define E_MIPS_MACH_LS3A 0x00A20000 +#define E_MIPS_MACH_GS464 0x00A20000 /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of these @@ -1249,7 +1249,6 @@ extern void bfd_mips_elf_swap_abiflags_v0_out #define AFL_EXT_XLR 1 /* RMI Xlr instruction. */ #define AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */ #define AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */ -#define AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */ #define AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */ #define AFL_EXT_5900 6 /* MIPS R5900 instruction. */ #define AFL_EXT_4650 7 /* MIPS R4650 instruction. */ diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 28fa1d7..9424a92 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -928,7 +928,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "+S" Length-minus-one field of cins/exts. Requires msb position of the field to be <= 63. - Loongson-3A: + Loongson-ext ASE: "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) @@ -1256,8 +1256,6 @@ static const unsigned int mips_isa_table[] = { #define INSN_LOONGSON_2E 0x40000000 /* ST Microelectronics Loongson 2F. */ #define INSN_LOONGSON_2F 0x80000000 -/* Loongson 3A. */ -#define INSN_LOONGSON_3A 0x00000400 /* RMI Xlr instruction */ #define INSN_XLR 0x00000020 /* Imagination interAptiv MR2. */ @@ -1374,7 +1372,7 @@ static const unsigned int mips_isa_table[] = { #define CPU_SB1 12310201 /* octal 'SB', 01. */ #define CPU_LOONGSON_2E 3001 #define CPU_LOONGSON_2F 3002 -#define CPU_LOONGSON_3A 3003 +#define CPU_GS464 3003 #define CPU_OCTEON 6501 #define CPU_OCTEONP 6601 #define CPU_OCTEON2 6502 @@ -1433,9 +1431,6 @@ cpu_is_member (int cpu, unsigned int mask) case CPU_LOONGSON_2F: return (mask & INSN_LOONGSON_2F) != 0; - case CPU_LOONGSON_3A: - return (mask & INSN_LOONGSON_3A) != 0; - case CPU_OCTEON: return (mask & INSN_OCTEON) != 0; -- cgit v1.1