From 4765cd611992862c844e8f152c5dbaadaecc25ce Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Tue, 27 Nov 2018 11:29:23 -0800 Subject: RISC-V: Add .insn CA support. gas/ * config/tc-riscv.c (validate_riscv_insn) <'F'>: Add support for CF6 and CF2 operands. (riscv_ip) <'F'>: Likewise. * doc/c-riscv.texi (RISC-V-Formats): Add func6 abbreviation. Use rs2 instead of rs1 in CR description. Add CA docs. * gas/testsuite/riscv/insn.s: Add use of .insn ca. * gas/testsuite/riscv/insn.d: Update to match. include/ * opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New. (OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New. opcodes/ * riscv-opc.c (ciw): Fix whitespace to align columns. (ca): New. --- include/ChangeLog | 5 +++++ include/opcode/riscv.h | 4 ++++ 2 files changed, 9 insertions(+) (limited to 'include') diff --git a/include/ChangeLog b/include/ChangeLog index e737525..6424596 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2018-11-27 Jim Wilson + + * opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New. + (OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New. + 2018-11-13 Thomas Preud'homme * opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 68047a5..10c5f3d 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -247,10 +247,14 @@ static const char * const riscv_pred_succ[16] = #define OP_MASK_CRS2S 0x7 #define OP_SH_CRS2S 2 +#define OP_MASK_CFUNCT6 0x3f +#define OP_SH_CFUNCT6 10 #define OP_MASK_CFUNCT4 0xf #define OP_SH_CFUNCT4 12 #define OP_MASK_CFUNCT3 0x7 #define OP_SH_CFUNCT3 13 +#define OP_MASK_CFUNCT2 0x3 +#define OP_SH_CFUNCT2 5 /* ABI names for selected x-registers. */ -- cgit v1.1