From 01804a098dea7d08857eee82bcaad04676dd8ea1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Sun, 13 Nov 2022 16:59:21 +0100 Subject: RISC-V: Add T-Head Int vendor extension MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds the XTheadInt extension, which provides interrupt stack management instructions. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia Signed-off-by: Christoph Müllner --- include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + 2 files changed, 9 insertions(+) (limited to 'include') diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index d7d9dbc..f36b06d 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2213,6 +2213,11 @@ #define MASK_TH_FMV_HW_X 0xfff0707f #define MATCH_TH_FMV_X_HW 0x5000100b #define MASK_TH_FMV_X_HW 0xfff0707f +/* Vendor-specific (T-Head) XTheadInt instructions. */ +#define MATCH_TH_IPOP 0x0050000b +#define MASK_TH_IPOP 0xffffffff +#define MATCH_TH_IPUSH 0x0040000b +#define MASK_TH_IPUSH 0xffffffff /* Vendor-specific (T-Head) XTheadMac instructions. */ #define MATCH_TH_MULA 0x2000100b #define MASK_TH_MULA 0xfe00707f @@ -3130,6 +3135,9 @@ DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW) /* Vendor-specific (T-Head) XTheadFmv instructions. */ DECLARE_INSN(th_fmv_hw_x, MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X) DECLARE_INSN(th_fmv_x_hw, MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW) +/* Vendor-specific (T-Head) XTheadInt instructions. */ +DECLARE_INSN(th_ipop, MATCH_TH_IPOP, MASK_TH_IPOP) +DECLARE_INSN(th_ipush, MATCH_TH_IPUSH, MASK_TH_IPUSH) /* Vendor-specific (T-Head) XTheadMac instructions. */ DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f90cf97..c3cbde6 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -417,6 +417,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADCONDMOV, INSN_CLASS_XTHEADFMEMIDX, INSN_CLASS_XTHEADFMV, + INSN_CLASS_XTHEADINT, INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, -- cgit v1.1