From 00c2093f698e8f40c04340cb1832d09e11ece237 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Tue, 19 Dec 2017 12:05:20 +0000 Subject: Correct disassembly of dot product instructions. Dot products deviate from the normal disassembly rules for lane indexed instruction. Their canonical representation is in the form of: v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote that these instructions select 4x 1 byte elements instead of a single 1 byte element. Previously we were disassembling them following the normal rules, this patch corrects the disassembly. gas/ PR gas/22559 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B. * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly. include/ PR gas/22559 * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. opcodes/ PR gas/22559 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B. --- include/ChangeLog | 5 +++++ include/opcode/aarch64.h | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'include') diff --git a/include/ChangeLog b/include/ChangeLog index ecfd766..144c138 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,10 @@ 2017-12-19 Tamar Christina + PR gas/22559 + * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. + +2017-12-19 Tamar Christina + PR gas/22529 * opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 453b177..1ebc492 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -396,6 +396,11 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_S_S, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_Q, + /* This type qualifier has a special meaning in that it means that 4 x 1 byte + are selected by the instruction. Other than that it has no difference + with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical + reasons and is an exception from normal AArch64 disassembly scheme. */ + AARCH64_OPND_QLF_S_4B, /* Qualifying an operand which is a SIMD vector register or a SIMD vector register list; indicating register shape. -- cgit v1.1