From fd65497db4098140490e59e3dbf4709da5536081 Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Tue, 3 Nov 2020 14:21:32 +0000 Subject: [PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7 Armv8.7 architecture introduces the "accelerator extension", aka load/store of 64 bytes. New atomic load/store instructions are: LD64B, ST64B, ST64BV and ST64BV0. This patch adds: + New feature +ls64 to -march command line. + New atomic load/store instructions associated with above feature. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i --- include/opcode/aarch64.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/opcode') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 7d484ad..07eb911 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -52,6 +52,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */ #define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */ #define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */ +#define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */ #define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ #define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */ #define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */ @@ -131,7 +132,8 @@ typedef uint32_t aarch64_insn; | AARCH64_FEATURE_BFLOAT16 \ | AARCH64_FEATURE_I8MM) #define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \ - AARCH64_FEATURE_V8_7) + AARCH64_FEATURE_V8_7 \ + | AARCH64_FEATURE_LS64) #define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ AARCH64_FEATURE_V8_R) \ & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR)) -- cgit v1.1