From b0f266f38b49c516ab0f95c638720073899446cc Mon Sep 17 00:00:00 2001 From: Mary Bennett Date: Thu, 30 May 2024 16:06:58 +0100 Subject: RISC-V: Add support for XCVbi extension in CV32E40P Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin Nazareno Bruschi Lin Sinan include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbi as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-bi-beqimm.d: New test. * testsuite/gas/riscv/cv-bi-beqimm.s: New test. * testsuite/gas/riscv/cv-bi-bneimm.d: New test. * testsuite/gas/riscv/cv-bi-bneimm.s: New test. * testsuite/gas/riscv/cv-bi-fail-march.d: New test. * testsuite/gas/riscv/cv-bi-fail-march.l: New test. * testsuite/gas/riscv/cv-bi-fail-march.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvbi string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add disassembly for new operand. * riscv-opc.c: Add XCVbi instructions. --- include/opcode/riscv-opc.h | 5 +++++ include/opcode/riscv.h | 4 ++++ 2 files changed, 9 insertions(+) (limited to 'include/opcode') diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 73d8c0c..0661565 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2472,6 +2472,11 @@ /* Vendor-specific (CORE-V) Xcvelw instructions. */ #define MATCH_CV_ELW 0x600b #define MASK_CV_ELW 0x707f +/* Vendor-specific (CORE-V) Xcvbi instructions. */ +#define MATCH_CV_BNEIMM 0x700b +#define MASK_CV_BNEIMM 0x707f +#define MATCH_CV_BEQIMM 0x600b +#define MASK_CV_BEQIMM 0x707f /* Vendor-specific (T-Head) XTheadBa instructions. */ #define MATCH_TH_ADDSL 0x0000100b #define MASK_TH_ADDSL 0xf800707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d210e70..f6e6dae 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -55,6 +55,7 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n))) +#define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1)) #define EXTRACT_ITYPE_IMM(x) \ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) @@ -119,6 +120,8 @@ static inline unsigned int riscv_insn_length (insn_t insn) (RV_X(x, 20, 5)) #define EXTRACT_CV_IS3_UIMM5(x) \ (RV_X(x, 25, 5)) +#define EXTRACT_CV_BI_IMM5(x) \ + (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5)) #define ENCODE_ITYPE_IMM(x) \ (RV_X(x, 0, 12) << 20) @@ -490,6 +493,7 @@ enum riscv_insn_class INSN_CLASS_XCVMAC, INSN_CLASS_XCVALU, INSN_CLASS_XCVELW, + INSN_CLASS_XCVBI, INSN_CLASS_XTHEADBA, INSN_CLASS_XTHEADBB, INSN_CLASS_XTHEADBS, -- cgit v1.1