From 8edca81ece5df534c1cdd1f8362e7b5b9b090cfa Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Mon, 9 Nov 2020 11:09:12 +0000 Subject: aarch64: Limit Rt register number for LS64 load/store instructions Atomic 64-byte load/store instructions limit Rt register number to values matching below condition (register number must be even and <= 22): if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED; This patch adds check if Rt fulfills above requirement. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i --- include/opcode/aarch64.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/opcode') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ffde1ba..304c6cb 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -201,6 +201,7 @@ enum aarch64_opnd AARCH64_OPND_Rm, /* Integer register as source. */ AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ + AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */ AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ -- cgit v1.1