From 38bf472a15210c222bb3885820e763c47760a704 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Wed, 28 Jun 2017 02:07:36 +0100 Subject: MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) : New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) : New case. (mips_set_isa_flags) : Likewise. (bfd_mips_isa_ext) : Likewise. (print_mips_isa_ext) : Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) : Update comment. (validate_insn_args) : Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) : New case. (print_mips_isa_ext) : Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list. --- include/opcode/mips.h | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) (limited to 'include/opcode') diff --git a/include/opcode/mips.h b/include/opcode/mips.h index c71a33a..1b3b2c6 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -935,6 +935,9 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "+z" 5-bit rz register (OP_*_RZ) "+Z" 5-bit fz register (OP_*_FZ) + interAptiv MR2: + "-m" register list for SAVE/RESTORE instruction + Enhanced VA Scheme: "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) @@ -1007,7 +1010,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) Extension character sequences used so far ("-" followed by the following), for quick reference when adding more: "AB" - "abdstuvwxy" + "abdmstuvwxy" */ /* These are the bits which may be set in the pinfo field of an @@ -1214,7 +1217,7 @@ static const unsigned int mips_isa_table[] = { #undef ISAF /* Masks used for Chip specific instructions. */ -#define INSN_CHIP_MASK 0xc3ff4f60 +#define INSN_CHIP_MASK 0xc7ff4f60 /* Cavium Networks Octeon instructions. */ #define INSN_OCTEON 0x00000800 @@ -1254,6 +1257,8 @@ static const unsigned int mips_isa_table[] = { #define INSN_LOONGSON_3A 0x00000400 /* RMI Xlr instruction */ #define INSN_XLR 0x00000020 +/* Imagination interAptiv MR2. */ +#define INSN_INTERAPTIV_MR2 0x04000000 /* DSP ASE */ #define ASE_DSP 0x00000001 @@ -1356,6 +1361,7 @@ static const unsigned int mips_isa_table[] = { #define CPU_OCTEON2 6502 #define CPU_OCTEON3 6503 #define CPU_XLR 887682 /* decimal 'XLR' */ +#define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */ /* Return true if the given CPU is included in INSN_* mask MASK. */ @@ -1426,6 +1432,9 @@ cpu_is_member (int cpu, unsigned int mask) case CPU_XLR: return (mask & INSN_XLR) != 0; + case CPU_INTERAPTIV_MR2: + return (mask & INSN_INTERAPTIV_MR2) != 0; + case CPU_MIPS32R6: return (mask & INSN_ISA_MASK) == INSN_ISA32R6; @@ -1847,6 +1856,8 @@ extern int bfd_mips_num_opcodes; "d" 5-bit EXT size, which becomes MSBD Requires that "b" occurs first to set position. Enforces: 0 < (pos+size) <= 32. + "n" 2-bit immediate (1 .. 4) + "o" 5-bit unsigned immediate * 16 "r" 3-bit register "s" 3-bit ASMACRO select immediate "u" 16-bit unsigned immediate @@ -1882,13 +1893,13 @@ extern int bfd_mips_num_opcodes; "0123456 89" ".[]<>" "ABCDEFGHI KLMNOPQRSTUVWXYZ" - "abcde ijklm pqrs uvwxyz" + "abcde ijklmnopqrs uvwxyz" */ /* Save/restore encoding for the args field when all 4 registers are either saved as arguments or saved/restored as statics. */ -#define MIPS16_ALL_ARGS 0xe -#define MIPS16_ALL_STATICS 0xb +#define MIPS_SVRS_ALL_ARGS 0xe +#define MIPS_SVRS_ALL_STATICS 0xb /* The following flags have the same value for the mips16 opcode table: -- cgit v1.1