From 39092c7a1fb0927fbbdb40e1142de816d6f3f097 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Mon, 15 Jan 2024 09:37:32 +0000 Subject: aarch64: Add SVE2.1 dupq, eorqv and extq instructions. Hi, This patch add support for SVE2.1 instruction dupq, eorqv and extq. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath. --- include/opcode/aarch64.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include/opcode/aarch64.h') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 1af49c4..de161db 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -727,8 +727,10 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */ AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ + AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ + AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ. */ AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ @@ -1002,7 +1004,8 @@ enum aarch64_insn_class cssc, gcs, the, - sve2_urqvs + sve2_urqvs, + sve_index1, }; /* Opcode enumerators. */ -- cgit v1.1