From 93f9a11fbdb8f09428b17180d51a09a1bda39a52 Mon Sep 17 00:00:00 2001 From: Yao Qi Date: Tue, 8 Nov 2016 14:28:32 +0000 Subject: gdbarch software_single_step returns VEC (CORE_ADDR) * This patch changes gdbarch method software_single_step to return a vector of addresses on which GDB should insert breakpoints, and don't insert breakpoints. Instead, the caller of gdbarch_software_single_step inserts breakpoints if the returned vector is not NULL. gdb: 2016-11-08 Yao Qi * aarch64-tdep.c (aarch64_software_single_step): Return VEC (CORE_ADDR) *. Return NULL instead of 0. Don't call insert_single_step_breakpoint. * alpha-tdep.c (alpha_deal_with_atomic_sequence): Likewise. (alpha_software_single_step): Likewise. * alpha-tdep.h (alpha_software_single_step): Update declaration. * arm-linux-tdep.c (arm_linux_software_single_step): Return VEC (CORE_ADDR) *. Return NULL instead of 0. * arm-tdep.c (arm_software_single_step): Return NULL instead of 0. * arm-tdep.h (arm_software_single_step): Update declaration. * breakpoint.c (insert_single_step_breakpoints): New function. * breakpoint.h (insert_single_step_breakpoints): Declare. * cris-tdep.c (cris_software_single_step): Return VEC (CORE_ADDR) *. Don't call insert_single_step_breakpoint. * gdbarch.sh (software_single_step): Change it to return VEC (CORE_ADDR) *. * gdbarch.c, gdbarch.h: Regenerated. * infrun.c (maybe_software_singlestep): Adjust. * mips-tdep.c (mips_deal_with_atomic_sequence): Return VEC (CORE_ADDR) *. Don't call insert_single_step_breakpoint. (micromips_deal_with_atomic_sequence): Likewise. (deal_with_atomic_sequence): Likewise. (mips_software_single_step): Likewise. * mips-tdep.h (mips_software_single_step): Update declaration. * moxie-tdep.c (moxie_software_single_step): Likewise. * nios2-tdep.c (nios2_software_single_step): Likewise. * ppc-tdep.h (ppc_deal_with_atomic_sequence): Update declaration. * record-full.c (record_full_resume): Adjust. (record_full_wait_1): Likewise. * rs6000-aix-tdep.c (rs6000_software_single_step): Return VEC (CORE_ADDR) *. Don't call insert_single_step_breakpoint. * rs6000-tdep.c (ppc_deal_with_atomic_sequence): Return VEC (CORE_ADDR) *. Don't call insert_single_step_breakpoint. * s390-linux-tdep.c (s390_software_single_step): Likewise. * sparc-tdep.c (sparc_software_single_step): Likewise. * spu-tdep.c (spu_software_single_step): Likewise. * tic6x-tdep.c (tic6x_software_single_step): Likewise. --- gdb/aarch64-tdep.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'gdb/aarch64-tdep.c') diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 1298302..b5a88cc 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -2224,11 +2224,10 @@ value_of_aarch64_user_reg (struct frame_info *frame, const void *baton) /* Implement the "software_single_step" gdbarch method, needed to single step through atomic sequences on AArch64. */ -static int +static VEC (CORE_ADDR) * aarch64_software_single_step (struct frame_info *frame) { struct gdbarch *gdbarch = get_frame_arch (frame); - struct address_space *aspace = get_frame_address_space (frame); enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); const int insn_size = 4; const int atomic_sequence_length = 16; /* Instruction sequence length. */ @@ -2243,13 +2242,14 @@ aarch64_software_single_step (struct frame_info *frame) int bc_insn_count = 0; /* Conditional branch instruction count. */ int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ aarch64_inst inst; + VEC (CORE_ADDR) *next_pcs = NULL; if (aarch64_decode_insn (insn, &inst, 1) != 0) - return 0; + return NULL; /* Look for a Load Exclusive instruction which begins the sequence. */ if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0) - return 0; + return NULL; for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) { @@ -2258,14 +2258,14 @@ aarch64_software_single_step (struct frame_info *frame) byte_order_for_code); if (aarch64_decode_insn (insn, &inst, 1) != 0) - return 0; + return NULL; /* Check if the instruction is a conditional branch. */ if (inst.opcode->iclass == condbranch) { gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19); if (bc_insn_count >= 1) - return 0; + return NULL; /* It is, so we'll try to set a breakpoint at the destination. */ breaks[1] = loc + inst.operands[0].imm.value; @@ -2284,7 +2284,7 @@ aarch64_software_single_step (struct frame_info *frame) /* We didn't find a closing Store Exclusive instruction, fall back. */ if (!closing_insn) - return 0; + return NULL; /* Insert breakpoint after the end of the atomic sequence. */ breaks[0] = loc + insn_size; @@ -2299,9 +2299,9 @@ aarch64_software_single_step (struct frame_info *frame) /* Insert the breakpoint at the end of the sequence, and one at the destination of the conditional branch, if it exists. */ for (index = 0; index <= last_breakpoint; index++) - insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); + VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]); - return 1; + return next_pcs; } struct displaced_step_closure -- cgit v1.1