From abe7c33b45288b407e6d001aad713183d4bab5c6 Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Tue, 15 Nov 2016 15:11:47 +0100 Subject: [ARC] Add checking for LP_COUNT reg usage, improve error reporting. gas/ 2016-11-29 Claudiu Zissulescu * config/tc-arc.c (find_opcode_match): New function argument errmsg. (assemble_tokens): Collect and report the eventual error message found during opcode matching process. * testsuite/gas/arc/lpcount-err.s: New file. * testsuite/gas/arc/add_s-err.s: Update error message. opcode/ 2016-11-29 Claudiu Zissulescu * arc-opc.c (insert_ra_chk): New function. (insert_rb_chk): Likewise. (insert_rad): Update text error message. (insert_rcd): Likewise. (insert_rhv2): Likewise. (insert_r0): Likewise. (insert_r1): Likewise. (insert_r2): Likewise. (insert_r3): Likewise. (insert_sp): Likewise. (insert_gp): Likewise. (insert_pcl): Likewise. (insert_blink): Likewise. (insert_ilink1): Likewise. (insert_ilink2): Likewise. (insert_ras): Likewise. (insert_rbs): Likewise. (insert_rcs): Likewise. (insert_simm3s): Likewise. (insert_rrange): Likewise. (insert_fpel): Likewise. (insert_blinkel): Likewise. (insert_pcel): Likewise. (insert_nps_3bit_dst): Likewise. (insert_nps_3bit_dst_short): Likewise. (insert_nps_3bit_src2_short): Likewise. (insert_nps_bitop_size_2b): Likewise. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise. (RA_CHK): Define. (RB): Adjust. (RB_CHK): Define. (RC): Adjust. * arc-dis.c (print_insn_arc): Add LOAD and STORE class. * arc-tbl.h (div, divu): All instructions are DIVREM class. Change first insn argument to check for LP_COUNT usage. (rem): Likewise. (ld, ldd): All instructions are LOAD class. Change first insn argument to check for LP_COUNT usage. (st, std): All instructions are STORE class. (mac, mpy, dmac, mul, dmpy): All instructions are MPY class. Change first insn argument to check for LP_COUNT usage. (mov): All instructions are MOVE class. Change first insn argument to check for LP_COUNT usage. include/ 2016-11-29 Claudiu Zissulescu * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE instruction classes. --- gas/ChangeLog | 9 +++++++++ gas/config/tc-arc.c | 35 ++++++++++++++++++++--------------- gas/testsuite/gas/arc/add_s-err.s | 2 +- gas/testsuite/gas/arc/lpcount-err.s | 9 +++++++++ 4 files changed, 39 insertions(+), 16 deletions(-) create mode 100644 gas/testsuite/gas/arc/lpcount-err.s (limited to 'gas') diff --git a/gas/ChangeLog b/gas/ChangeLog index c88a5f3..e8912cd 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,12 @@ +2016-11-29 Claudiu Zissulescu + + * config/tc-arc.c (find_opcode_match): New function argument + errmsg. + (assemble_tokens): Collect and report the eventual error message + found during opcode matching process. + * testsuite/gas/arc/lpcount-err.s: New file. + * testsuite/gas/arc/add_s-err.s: Update error message. + 2016-11-28 Ramiro Polla Amit Pawar diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c index 4eb6d6d..f5cbc8b 100644 --- a/gas/config/tc-arc.c +++ b/gas/config/tc-arc.c @@ -1710,7 +1710,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, int *pntok, struct arc_flags *first_pflag, int nflgs, - int *pcpumatch) + int *pcpumatch, + const char **errmsg) { const struct arc_opcode *opcode; struct arc_opcode_hash_entry_iterator iter; @@ -1765,7 +1766,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, { case ARC_OPERAND_ADDRTYPE: { - const char *errmsg = NULL; + *errmsg = NULL; /* Check to be an address type. */ if (tok[tokidx].X_op != O_addrtype) @@ -1776,8 +1777,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, address type. */ gas_assert (operand->insert != NULL); (*operand->insert) (0, tok[tokidx].X_add_number, - &errmsg); - if (errmsg != NULL) + errmsg); + if (*errmsg != NULL) goto match_failed; } break; @@ -1803,11 +1804,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, /* Special handling? */ if (operand->insert) { - const char *errmsg = NULL; + *errmsg = NULL; (*operand->insert)(0, regno (tok[tokidx].X_add_number), - &errmsg); - if (errmsg) + errmsg); + if (*errmsg) { if (operand->flags & ARC_OPERAND_IGNORE) { @@ -1923,11 +1924,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, { if (operand->insert) { - const char *errmsg = NULL; + *errmsg = NULL; (*operand->insert)(0, tok[tokidx].X_add_number, - &errmsg); - if (errmsg) + errmsg); + if (*errmsg) goto match_failed; } else if (!(operand->flags & ARC_OPERAND_IGNORE)) @@ -1948,11 +1949,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, regs |= get_register (tok[tokidx].X_op_symbol); if (operand->insert) { - const char *errmsg = NULL; + *errmsg = NULL; (*operand->insert)(0, regs, - &errmsg); - if (errmsg) + errmsg); + if (*errmsg) goto match_failed; } else @@ -2326,6 +2327,7 @@ assemble_tokens (const char *opname, bfd_boolean found_something = FALSE; const struct arc_opcode_hash_entry *entry; int cpumatch = 1; + const char *errmsg = NULL; /* Search opcodes. */ entry = arc_find_opcode (opname); @@ -2342,7 +2344,7 @@ assemble_tokens (const char *opname, frag_now->fr_file, frag_now->fr_line, opname); found_something = TRUE; opcode = find_opcode_match (entry, tok, &ntok, pflags, - nflgs, &cpumatch); + nflgs, &cpumatch, &errmsg); if (opcode != NULL) { struct arc_insn insn; @@ -2356,7 +2358,10 @@ assemble_tokens (const char *opname, if (found_something) { if (cpumatch) - as_bad (_("inappropriate arguments for opcode '%s'"), opname); + if (errmsg) + as_bad (_("%s for instruction '%s'"), errmsg, opname); + else + as_bad (_("inappropriate arguments for opcode '%s'"), opname); else as_bad (_("opcode '%s' not supported for target %s"), opname, selected_cpu.name); diff --git a/gas/testsuite/gas/arc/add_s-err.s b/gas/testsuite/gas/arc/add_s-err.s index 298f4ef..024bc43 100644 --- a/gas/testsuite/gas/arc/add_s-err.s +++ b/gas/testsuite/gas/arc/add_s-err.s @@ -4,7 +4,7 @@ ; { dg-do assemble { target arc*-*-* } } ; { dg-options "--mcpu=arc700" } ;; The following insns are accepted by ARCv2 only - add_s r4,r4,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" } + add_s r4,r4,-1 ; { dg-error "Error: Register must be either r0-r3 or r12-r15 for instruction." } add_s 0,0xAAAA5555,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" } add_s r0,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" } add_s r1,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" } diff --git a/gas/testsuite/gas/arc/lpcount-err.s b/gas/testsuite/gas/arc/lpcount-err.s new file mode 100644 index 0000000..51d6f70 --- /dev/null +++ b/gas/testsuite/gas/arc/lpcount-err.s @@ -0,0 +1,9 @@ +;; LP_COUNT register cannot be used with multi-cycle instructions such as: +;; load, lr, multiply and divide. +; { dg-do assemble { target arc*-*-* } } + + .cpu HS + + mpy lp_count,r0,r1 ; { dg-error "Error: LP_COUNT register cannot be used as destination register." } + ld lp_count,[r2,1] ; { dg-error "Error: LP_COUNT register cannot be used as destination register." } + div lp_count,r12,r1 ; { dg-error "Error: LP_COUNT register cannot be used as destination register." } -- cgit v1.1