From dee35d026c92b4054a90d655324dc90b4ea6cbfc Mon Sep 17 00:00:00 2001 From: Nelson Chu Date: Tue, 3 Mar 2020 21:08:05 -0800 Subject: RISC-V: Support assembler modifier %got_pcrel_hi. gas/ * config/tc-riscv.c: Support the modifier %got_pcrel_hi. * doc/c-riscv.texi: Add documentation. * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new modifier %got_pcrel_hi. * testsuite/gas/riscv/no-relax-reloc.s: Likewise. * testsuite/gas/riscv/relax-reloc.d: Likewise. * testsuite/gas/riscv/relax-reloc.s: Likewise. --- gas/doc/c-riscv.texi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'gas/doc/c-riscv.texi') diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 6e932dc..488cf56 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -257,6 +257,23 @@ Or you can use the pseudo lla/lw/sw/... instruction to do this. lla a0, @var{symbol} @end smallexample +@item %got_pcrel_hi(@var{symbol}) +The high 20 bits of relative address between pc and the GOT entry of +@var{symbol}. This is usually used with the %pcrel_lo modifier to access +the GOT entry. + +@smallexample +@var{label}: + auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 + addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I + +@var{label}: + auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 + load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S +@end smallexample + +Also, the pseudo la instruction with PIC has similar behavior. + @item %tprel_add(@var{symbol}) This is used purely to associate the R_RISCV_TPREL_ADD relocation for TLS relaxation. This one is only valid as the fourth operand to the normally -- cgit v1.1