From 0b4595be3f04aa3741157b24654e554fc3264fc2 Mon Sep 17 00:00:00 2001 From: Xiao Zeng Date: Thu, 6 Jun 2024 15:59:53 +0800 Subject: RISC-V: Add support for Zvfbfwma extension This implements the Zvfbfwma extension, as of version 1.0. View detailed information in: 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension." 1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f 1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V 1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin 2 Depending on different usage scenarios, the Zvfbfwma extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. This is consistent with the processing strategy in Zvfbfmin. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfwma.d: New test. * testsuite/gas/riscv/zvfbfwma.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define. (MASK_VFWMACCBF16_VF): Ditto. (MATCH_VFWMACCBF16_VV): Ditto. (MASK_VFWMACCBF16_VV): Ditto. (DECLARE_INSN): New declarations for Zvfbfwma. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFWMA opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfwma instructions. --- gas/NEWS | 2 ++ 1 file changed, 2 insertions(+) (limited to 'gas/NEWS') diff --git a/gas/NEWS b/gas/NEWS index a668a52..145ce41 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -25,6 +25,8 @@ * Add support for RISC-V Zvfbfmin extension with version 1.0. +* Add support for RISC-V Zvfbfwma extension with version 1.0. + * The base register operand in D(X,B) and D(L,B) may be explicitly omitted in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) D(X,%r0), D(L,0), and D(L,%r0). -- cgit v1.1