From 14ea7f9b443950dac2b40f234e820be8a09cbb8a Mon Sep 17 00:00:00 2001 From: Nelson Chu Date: Tue, 2 Jul 2024 15:37:42 +0800 Subject: RISC-V: Tidy and complete testing of all architecture imply rules. gas/ * testsuite/gas/riscv/imply.s: New testcase for all imply cases. * testsuite/gas/riscv/imply.d: Likewise. * testsuite/gas/riscv/march-imply-i.s: Renamed to imply-zicsr-zifencei.s. * testsuite/gas/riscv/march-imply-i2p0-02.d: Renamed to imply-zicsr-zifencei-i2p0-misa-spec-2p2.d. * testsuite/gas/riscv/march-imply-i2p1-01.d/l: Renamed to imply-zicsr-zifencei-i2p1-misa-spec-20191213.d. * testsuite/gas/riscv/march-imply-i2p0-01.d: Removed. Combined into new imply testcase. * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise. * testsuite/gas/riscv/march-imply-a.d: Likewise. * testsuite/gas/riscv/march-imply-b.d: Likewise. * testsuite/gas/riscv/march-imply-f.d: Likewise. * testsuite/gas/riscv/march-imply-g.d: Likewise. * testsuite/gas/riscv/march-imply-h.d: Likewise. * testsuite/gas/riscv/march-imply-q.d: Likewise. * testsuite/gas/riscv/march-imply-smcsrind.d: Likewise. * testsuite/gas/riscv/march-imply-smstateen.d: Likewise. * testsuite/gas/riscv/march-imply-unsupported.d: Likewise. * testsuite/gas/riscv/march-imply-v.d: Likewise. * testsuite/gas/riscv/march-imply-zcd.d: Likewise. * testsuite/gas/riscv/march-imply-zcf.d: Likewise. --- .../imply-zicsr-zifencei-i2p0-misa-spec-2p2.d | 7 ++ .../imply-zicsr-zifencei-i2p1-misa-spec-20191213.d | 23 ++++++ gas/testsuite/gas/riscv/imply-zicsr-zifencei.s | 24 ++++++ gas/testsuite/gas/riscv/imply.d | 82 +++++++++++++++++++ gas/testsuite/gas/riscv/imply.s | 91 ++++++++++++++++++++++ gas/testsuite/gas/riscv/march-imply-a.d | 6 -- gas/testsuite/gas/riscv/march-imply-b.d | 6 -- gas/testsuite/gas/riscv/march-imply-d.d | 6 -- gas/testsuite/gas/riscv/march-imply-f.d | 6 -- gas/testsuite/gas/riscv/march-imply-g.d | 6 -- gas/testsuite/gas/riscv/march-imply-h.d | 6 -- gas/testsuite/gas/riscv/march-imply-i.s | 24 ------ gas/testsuite/gas/riscv/march-imply-i2p0-01.d | 7 -- gas/testsuite/gas/riscv/march-imply-i2p0-02.d | 7 -- gas/testsuite/gas/riscv/march-imply-i2p1-01.d | 3 - gas/testsuite/gas/riscv/march-imply-i2p1-01.l | 21 ----- gas/testsuite/gas/riscv/march-imply-i2p1-02.d | 7 -- gas/testsuite/gas/riscv/march-imply-q.d | 6 -- gas/testsuite/gas/riscv/march-imply-smcsrind.d | 6 -- gas/testsuite/gas/riscv/march-imply-smstateen.d | 6 -- gas/testsuite/gas/riscv/march-imply-unsupported.d | 6 -- gas/testsuite/gas/riscv/march-imply-v.d | 6 -- gas/testsuite/gas/riscv/march-imply-zcd.d | 6 -- gas/testsuite/gas/riscv/march-imply-zcf.d | 6 -- 24 files changed, 227 insertions(+), 147 deletions(-) create mode 100644 gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p0-misa-spec-2p2.d create mode 100644 gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p1-misa-spec-20191213.d create mode 100644 gas/testsuite/gas/riscv/imply-zicsr-zifencei.s create mode 100644 gas/testsuite/gas/riscv/imply.d create mode 100644 gas/testsuite/gas/riscv/imply.s delete mode 100644 gas/testsuite/gas/riscv/march-imply-a.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-b.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-d.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-f.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-g.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-h.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-i.s delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p0-01.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p0-02.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p1-01.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p1-01.l delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p1-02.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-q.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-smcsrind.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-smstateen.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-unsupported.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-v.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-zcd.d delete mode 100644 gas/testsuite/gas/riscv/march-imply-zcf.d diff --git a/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p0-misa-spec-2p2.d b/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p0-misa-spec-2p2.d new file mode 100644 index 0000000..2f5ed99 --- /dev/null +++ b/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p0-misa-spec-2p2.d @@ -0,0 +1,7 @@ +#as: -march=rv32i -march-attr -misa-spec=2.2 +#readelf: -A +#source: imply-zicsr-zifencei.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p0" +#... diff --git a/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p1-misa-spec-20191213.d b/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p1-misa-spec-20191213.d new file mode 100644 index 0000000..80630f4 --- /dev/null +++ b/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p1-misa-spec-20191213.d @@ -0,0 +1,23 @@ +#as: -march=rv32i -march-attr -misa-spec=20191213 +#source: imply-zicsr-zifencei.s +#error: .*Assembler messages: +.*Error: unrecognized opcode `csrr t0,ustatus', extension `zicsr' required +.*Error: unrecognized opcode `csrwi ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrsi ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrci ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrw ustatus,t0', extension `zicsr' required +.*Error: unrecognized opcode `csrw ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrs ustatus,t0', extension `zicsr' required +.*Error: unrecognized opcode `csrs ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrc ustatus,t0', extension `zicsr' required +.*Error: unrecognized opcode `csrc ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrrwi t0,ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrrsi t0,ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrrci t0,ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrrw t0,ustatus,t0', extension `zicsr' required +.*Error: unrecognized opcode `csrrw t0,ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrrs t0,ustatus,t0', extension `zicsr' required +.*Error: unrecognized opcode `csrrs t0,ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `csrrc t0,ustatus,t0', extension `zicsr' required +.*Error: unrecognized opcode `csrrc t0,ustatus,0x0', extension `zicsr' required +.*Error: unrecognized opcode `fence.i', extension `zifencei' required diff --git a/gas/testsuite/gas/riscv/imply-zicsr-zifencei.s b/gas/testsuite/gas/riscv/imply-zicsr-zifencei.s new file mode 100644 index 0000000..b65c3c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/imply-zicsr-zifencei.s @@ -0,0 +1,24 @@ +target: + # zicsr + csrr t0, ustatus + csrwi ustatus, 0x0 + csrsi ustatus, 0x0 + csrci ustatus, 0x0 + csrw ustatus, t0 + csrw ustatus, 0x0 + csrs ustatus, t0 + csrs ustatus, 0x0 + csrc ustatus, t0 + csrc ustatus, 0x0 + csrrwi t0, ustatus, 0x0 + csrrsi t0, ustatus, 0x0 + csrrci t0, ustatus, 0x0 + csrrw t0, ustatus, t0 + csrrw t0, ustatus, 0x0 + csrrs t0, ustatus, t0 + csrrs t0, ustatus, 0x0 + csrrc t0, ustatus, t0 + csrrc t0, ustatus, 0x0 + + # zifencei + fence.i diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d new file mode 100644 index 0000000..dee8890 --- /dev/null +++ b/gas/testsuite/gas/riscv/imply.d @@ -0,0 +1,82 @@ +#source: imply.s +#as: -misa-spec=20191213 +#objdump: --syms --special-syms + +.*file format.*riscv.* + +SYMBOL TABLE: +[0-9a-f]+ l d .text 0+000 .text +[0-9a-f]+ l d .data 0+000 .data +[0-9a-f]+ l d .bss 0+000 .bss +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0 +[0-9a-f]+ l .text 0+000 \$xrv32e1p9 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1 +[0-9a-f]+ l .text 0+000 \$xrv32i2p0_zicsr2p0_zifencei2p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicntr2p0_zicsr2p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zihpm2p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_m2p0_zmmul1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_a2p1_zaamo1p0_zabha1p0_zalrsc1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_a2p1_zaamo1p0_zalrsc1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0 +[0-9a-f]+ l .text 0+000 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\$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcntrpmf1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smepmp1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssaia1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscsrind1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssstateen1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstc1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svadu1p0 +[0-9a-f]+ l d .riscv.attributes 0+000 .riscv.attributes diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s new file mode 100644 index 0000000..f341283 --- /dev/null +++ b/gas/testsuite/gas/riscv/imply.s @@ -0,0 +1,91 @@ +.macro imply string base=i +.option push +.option arch, rv32\base\string +nop +.option pop +.endm + +.text +imply ,g +imply ,e +imply ,i +imply ,i2p0 + +imply zicntr +imply zihpm + +imply m + +imply zabha +imply zacas +imply a + +imply xsfvcp +imply v +imply zvfh +imply zvfhmin +imply zvfbfwma +imply zvfbfmin +imply zve64d +imply zve64f +imply zve32f +imply zve64x +imply zve32x +imply zve32x_zvl65536b +imply zve32x_zvl32768b +imply zve32x_zvl16384b +imply zve32x_zvl8192b +imply zve32x_zvl4096b +imply zve32x_zvl2048b +imply zve32x_zvl1024b +imply zve32x_zvl512b +imply zve32x_zvl256b +imply zve32x_zvl128b +imply zve32x_zvl64b + +imply zcb +imply zcd +imply zcf +imply zcmp + +imply h +imply zhinx +imply zhinxmin + +imply q +imply zqinx + +imply d +imply zdinx + +imply zfa +imply zfbfmin +imply zfh +imply zfhmin +imply zfinx +imply f + +imply b + +imply zk +imply zkn +imply zks +imply zvbb +imply zvkng +imply zvknc +imply zvkn +imply zvksg +imply zvksc +imply zvks + +imply smaia +imply smcsrind +imply smcntrpmf +imply smstateen +imply smepmp +imply ssaia +imply sscsrind +imply sscofpmf +imply ssstateen +imply sstc +imply svadu diff --git a/gas/testsuite/gas/riscv/march-imply-a.d b/gas/testsuite/gas/riscv/march-imply-a.d deleted file mode 100644 index b2cbfcf..0000000 --- a/gas/testsuite/gas/riscv/march-imply-a.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32ia -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-b.d b/gas/testsuite/gas/riscv/march-imply-b.d deleted file mode 100644 index 82506c9..0000000 --- a/gas/testsuite/gas/riscv/march-imply-b.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32ib -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-d.d b/gas/testsuite/gas/riscv/march-imply-d.d deleted file mode 100644 index ce2b479..0000000 --- a/gas/testsuite/gas/riscv/march-imply-d.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32id -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0" diff --git a/gas/testsuite/gas/riscv/march-imply-f.d b/gas/testsuite/gas/riscv/march-imply-f.d deleted file mode 100644 index bc372ae..0000000 --- a/gas/testsuite/gas/riscv/march-imply-f.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32if -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0" diff --git a/gas/testsuite/gas/riscv/march-imply-g.d b/gas/testsuite/gas/riscv/march-imply-g.d deleted file mode 100644 index 7e7a967..0000000 --- a/gas/testsuite/gas/riscv/march-imply-g.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32g -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-h.d b/gas/testsuite/gas/riscv/march-imply-h.d deleted file mode 100644 index 04ad9f6..0000000 --- a/gas/testsuite/gas/riscv/march-imply-h.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32ih -march-attr -misa-spec=20191213 -mpriv-spec=1.12 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_h1p0_zicsr2p0" diff --git a/gas/testsuite/gas/riscv/march-imply-i.s b/gas/testsuite/gas/riscv/march-imply-i.s deleted file mode 100644 index b65c3c3..0000000 --- a/gas/testsuite/gas/riscv/march-imply-i.s +++ /dev/null @@ -1,24 +0,0 @@ -target: - # zicsr - csrr t0, ustatus - csrwi ustatus, 0x0 - csrsi ustatus, 0x0 - csrci ustatus, 0x0 - csrw ustatus, t0 - csrw ustatus, 0x0 - csrs ustatus, t0 - csrs ustatus, 0x0 - csrc ustatus, t0 - csrc ustatus, 0x0 - csrrwi t0, ustatus, 0x0 - csrrsi t0, ustatus, 0x0 - csrrci t0, ustatus, 0x0 - csrrw t0, ustatus, t0 - csrrw t0, ustatus, 0x0 - csrrs t0, ustatus, t0 - csrrs t0, ustatus, 0x0 - csrrc t0, ustatus, t0 - csrrc t0, ustatus, 0x0 - - # zifencei - fence.i diff --git a/gas/testsuite/gas/riscv/march-imply-i2p0-01.d b/gas/testsuite/gas/riscv/march-imply-i2p0-01.d deleted file mode 100644 index 6d86034..0000000 --- a/gas/testsuite/gas/riscv/march-imply-i2p0-01.d +++ /dev/null @@ -1,7 +0,0 @@ -#as: -march=rv32i2p0 -march-attr -misa-spec=20191213 -#readelf: -A -#source: march-imply-i.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p0_zicsr2p0_zifencei2p0" -#... diff --git a/gas/testsuite/gas/riscv/march-imply-i2p0-02.d b/gas/testsuite/gas/riscv/march-imply-i2p0-02.d deleted file mode 100644 index 7686296..0000000 --- a/gas/testsuite/gas/riscv/march-imply-i2p0-02.d +++ /dev/null @@ -1,7 +0,0 @@ -#as: -march=rv32i -march-attr -misa-spec=2.2 -#readelf: -A -#source: march-imply-i.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p0" -#... diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1-01.d b/gas/testsuite/gas/riscv/march-imply-i2p1-01.d deleted file mode 100644 index fcf22ed..0000000 --- a/gas/testsuite/gas/riscv/march-imply-i2p1-01.d +++ /dev/null @@ -1,3 +0,0 @@ -#as: -march=rv32i -march-attr -misa-spec=20191213 -#source: march-imply-i.s -#error_output: march-imply-i2p1-01.l diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1-01.l b/gas/testsuite/gas/riscv/march-imply-i2p1-01.l deleted file mode 100644 index 7fbee14..0000000 --- a/gas/testsuite/gas/riscv/march-imply-i2p1-01.l +++ /dev/null @@ -1,21 +0,0 @@ -.*Assembler messages: -.*Error: unrecognized opcode `csrr t0,ustatus', extension `zicsr' required -.*Error: unrecognized opcode `csrwi ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrsi ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrci ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrw ustatus,t0', extension `zicsr' required -.*Error: unrecognized opcode `csrw ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrs ustatus,t0', extension `zicsr' required -.*Error: unrecognized opcode `csrs ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrc ustatus,t0', extension `zicsr' required -.*Error: unrecognized opcode `csrc ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrrwi t0,ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrrsi t0,ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrrci t0,ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrrw t0,ustatus,t0', extension `zicsr' required -.*Error: unrecognized opcode `csrrw t0,ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrrs t0,ustatus,t0', extension `zicsr' required -.*Error: unrecognized opcode `csrrs t0,ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `csrrc t0,ustatus,t0', extension `zicsr' required -.*Error: unrecognized opcode `csrrc t0,ustatus,0x0', extension `zicsr' required -.*Error: unrecognized opcode `fence.i', extension `zifencei' required diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1-02.d b/gas/testsuite/gas/riscv/march-imply-i2p1-02.d deleted file mode 100644 index b8065b6..0000000 --- a/gas/testsuite/gas/riscv/march-imply-i2p1-02.d +++ /dev/null @@ -1,7 +0,0 @@ -#as: -march=rv32i_zicsr_zifencei -march-attr -misa-spec=20191213 -#readelf: -A -#source: march-imply-i.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_zicsr2p0_zifencei2p0" -#... diff --git a/gas/testsuite/gas/riscv/march-imply-q.d b/gas/testsuite/gas/riscv/march-imply-q.d deleted file mode 100644 index d631d6f..0000000 --- a/gas/testsuite/gas/riscv/march-imply-q.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv64iq -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv64i2p1_f2p2_d2p2_q2p2_zicsr2p0" diff --git a/gas/testsuite/gas/riscv/march-imply-smcsrind.d b/gas/testsuite/gas/riscv/march-imply-smcsrind.d deleted file mode 100644 index e028a06..0000000 --- a/gas/testsuite/gas/riscv/march-imply-smcsrind.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32i_smcsrind -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-smstateen.d b/gas/testsuite/gas/riscv/march-imply-smstateen.d deleted file mode 100644 index 2db14fd..0000000 --- a/gas/testsuite/gas/riscv/march-imply-smstateen.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32i_smstateen -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-unsupported.d b/gas/testsuite/gas/riscv/march-imply-unsupported.d deleted file mode 100644 index 5615d59..0000000 --- a/gas/testsuite/gas/riscv/march-imply-unsupported.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32g -march-attr -misa-spec=2.2 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-v.d b/gas/testsuite/gas/riscv/march-imply-v.d deleted file mode 100644 index e07eecf..0000000 --- a/gas/testsuite/gas/riscv/march-imply-v.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32iv -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-zcd.d b/gas/testsuite/gas/riscv/march-imply-zcd.d deleted file mode 100644 index e7c75f6..0000000 --- a/gas/testsuite/gas/riscv/march-imply-zcd.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32i_zcd -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0" diff --git a/gas/testsuite/gas/riscv/march-imply-zcf.d b/gas/testsuite/gas/riscv/march-imply-zcf.d deleted file mode 100644 index 3829637..0000000 --- a/gas/testsuite/gas/riscv/march-imply-zcf.d +++ /dev/null @@ -1,6 +0,0 @@ -#as: -march=rv32i_zcf -march-attr -misa-spec=20191213 -#readelf: -A -#source: empty.s -Attribute Section: riscv -File Attributes - Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0" -- cgit v1.1