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2024-04-15sim: riscv: Fix confusion with c.jal vs. c.addiwBernd Edlinger1-4/+4
2024-04-15sim: riscv: Make stack 16-byte alignedBernd Edlinger1-0/+2
2024-04-15sim: riscv: Fix PC at gdb breakpointsBernd Edlinger1-3/+1
2024-02-13sim: riscv: Add support for compressed integer instructionsJaydeep Patil2-4/+338
2024-01-22sim: riscv: Fix crash during instruction decodingJaydeep Patil1-1/+1
2024-01-12Update copyright year range in header of all files managed by GDBAndrew Burgess8-8/+8
2023-12-22sim: riscv: fix -Wshadow=local warningsMike Frysinger1-6/+4
2023-12-21sim: riscv: fix -Wimplicit-fallthrough warningsMike Frysinger1-0/+1
2023-10-18sim/riscv: fix JALR instruction simulationJaydeep Patil1-1/+1
2023-01-15sim: modules.c: fix generation after recent refactorsMike Frysinger1-0/+3
2023-01-14sim: common: move modules.c to source trackingMike Frysinger1-1/+2
2023-01-14sim: common: move libcommon.a objects to sourcesMike Frysinger1-2/+2
2023-01-11sim: build: drop subdir Makefile.in filesMike Frysinger1-22/+0
2023-01-10sim: move arch-specific file compilation of common/ files to top-levelMike Frysinger1-2/+2
2023-01-10sim: riscv: move arch-specific file compilation to top-levelMike Frysinger1-3/+2
2023-01-10sim: build: drop support for creating libsim.a in subdirsMike Frysinger1-2/+0
2023-01-10sim: riscv: move libsim.a creation to top-levelMike Frysinger2-6/+21
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker9-9/+9
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: riscv: move arch-specific settings to internal headerMike Frysinger5-55/+83
2022-12-22sim: move bfd.h include out of sim-main.hMike Frysinger1-0/+2
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger1-1/+1
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: riscv: invert sim_cpu storageMike Frysinger3-191/+258
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger1-1/+1
2022-11-07sim: riscv: add missing AC_MSG_RESULT callMike Frysinger1-0/+1
2022-11-07sim: riscv: drop subdir configure logicMike Frysinger5-3129/+23
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+25
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-5/+5
2022-10-23sim: mips/ppc/riscv: re-add AC_CANONICAL_SYSTEM [PR sim/29439]Mike Frysinger2-0/+162
2022-10-11sim/riscv: fix multiply instructions on simulatorTsukasa OI1-0/+1
2022-09-05sim/riscv: Complete tidying up with SBREAKTsukasa OI1-3/+3
2022-02-21sim: gdbinit: hoist setup to common codeMike Frysinger1-9/+0
2022-01-06sim: riscv: migrate to standard uintXX_t typesMike Frysinger1-28/+28
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker6-6/+6
2021-11-28sim: riscv: switch to new target-newlib-syscallMike Frysinger2-3/+2
2021-11-16sim: callback: expose argv & environMike Frysinger1-0/+5
2021-11-16sim: keep track of program environment stringsMike Frysinger1-0/+6
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-10-31sim: drop unused targ-vals.h includesMike Frysinger1-2/+0
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-07-01sim: unify reserved instruction bits settingsMike Frysinger2-2/+4
2021-06-30sim: unify scache settingsMike Frysinger2-2/+4
2021-06-30sim: move default model to the runtime sim stateMike Frysinger5-37/+8
2021-06-30sim: namespace sim_machsMike Frysinger3-1/+11
2021-06-29sim: model: constify sim_machs storageMike Frysinger2-1/+5
2021-06-22sim: drop configure scripts for simple portsMike Frysinger2-0/+11
2021-06-21sim: unify hardware settingsMike Frysinger3-49/+5
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