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2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton26-13254/+10922
2023-07-31bpf: opcodes: fix regression in BPF disassemblerJose E. Marchesi2-1/+7
This patch fixes a regression recently introduced in the BPF disassembler, that was assuming an abfd was always available in info->section->owner. Apparently this is not so in GDB, and therefore https://sourceware.org/bugzilla/show_bug.cgi?id=30705. Tested in bpf-unkonwn-none. opcodes/ChangeLog: 2023-07-31 Jose E. Marchesi <jose.marchesi@oracle.com> PR 30705 * bpf-dis.c (print_insn_bpf): Check that info->section->owner is actually available before using it.
2023-07-30bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flagsJose E. Marchesi3-21/+36
This patch adds support for EF_BPF_CPUVER bits in the ELF machine-dependent header flags. These bits encode the BPF CPU version for which the object file has been compiled for. The BPF assembler is updated so it annotates the object files it generates with these bits. The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the appropriate ISA version if the user didn't specify an explicit ISA version in the command line. Note that a value of zero in EF_BPF_CPUVER is interpreted by the disassembler as "use the later supported version" (the BPF CPU versions start with v1.) The readelf utility is updated to pretty print EF_BPF_CPUVER when it prints out the ELF header: $ readelf -h a.out ELF Header: ... Flags: 0x4, CPU Version: 4 Tested in bpf-unknown-none. include/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/bpf.h (EF_BPF_CPUVER): Define. * opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in EF_BPF_CPUVER. binutils/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * readelf.c (get_machine_flags): Recognize and pretty print BPF machine flags. opcodes/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-dis.c: Initialize asm_bpf_version to -1. (print_insn_bpf): Set BPF ISA version from the cpu version ELF header flags if no explicit version set in the command line. * disassemble.c (disassemble_init_for_target): Remove unused code. gas/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.h (elf_tc_final_processing): Define. * config/tc-bpf.c (bpf_elf_final_processing): New function.
2023-07-28Fix typo in riscv-dis.c commentTsukasa OI1-1/+1
Don't go "past" the start of the section.
2023-07-27Support Intel PBNDKBHu, Lin17-6040/+6090
gas/ChangeLog: * NEWS: Support Intel PBNDKB. * config/tc-i386.c: Add pbndkb. * doc/c-i386.texi: Document .pbndkb. * testsuite/gas/i386/i386.exp: Add PBNDKB tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/pbndkb-inval.l: New test. * testsuite/gas/i386/pbndkb-inval.s: Ditto. * testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New. (X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0. (rm_table): New entry for pbndkb. * i386-gen.c (cpu_flag): Add PBNDKB. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuPBNDKB): New. (i386_cpu_flags): Add cpupbndkb. * i386-opc.tbl: Add PBNDKB instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SM4Haochen Jiang7-6751/+6825
gas/ChangeLog: * NEWS: Support Intel SM4. * config/tc-i386.c: Add sm4. * doc/c-i386.texi: Document .sm4. * testsuite/gas/i386/i386.exp: Run SM4 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sm4-intel.d: Add SM4 tests. * testsuite/gas/i386/sm4.d: Ditto. * testsuite/gas/i386/sm4.s: Ditto. * testsuite/gas/i386/x86-64-sm4-intel.d: Ditto. * testsuite/gas/i386/x86-64-sm4.d: Ditto. * testsuite/gas/i386/x86-64-sm4.s: Ditto. opcodes/ChangeLog: * i386-dis.c (prefix_table): Add SM4 instructions. * i386-gen.c (isa_dependencies): Add SM4. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSM4): New. (i386_cpu_flags): Add cpusm4. * i386-opc.tbl: Add SM4 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SM3Haochen Jiang7-6974/+7105
gas/ChangeLog: * NEWS: Support Intel SM3. * config/tc-i386.c: Add sm3. * doc/c-i386.texi: Document .sm3. * testsuite/gas/i386/i386.exp: Run sm3 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sm3-intel.d: New test. * testsuite/gas/i386/sm3.d: Ditto. * testsuite/gas/i386/sm3.s: Ditto. * testsuite/gas/i386/x86-64-sm3-intel.d: Ditto. * testsuite/gas/i386/x86-64-sm3.d: Ditto. * testsuite/gas/i386/x86-64-sm3.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F38DA_W_0): New. (VEX_LEN_0F38DA_W_0_P_0): Ditto. (VEX_LEN_0F38DA_W_0_P_2): Ditto. (VEX_LEN_0F3ADE_W_0): Ditto. (VEX_W_0F38DA): Ditto. (VEX_W_0F3ADE): Ditto. (prefix_table): Add PREFIX_VEX_0F38DA_W_0. (vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0, VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0. (vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE. * i386-gen.c (isa_dependencies): Add SM3. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSM3): New. (i386_cpu_flags): Add cpusm3. * i386-opc.tbl: Add SM3 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SHA512Haochen Jiang7-7051/+7206
gas/ChangeLog: * NEWS: Support Intel SHA512. * config/tc-i386.c: Add sha512. * doc/c-i386.texi: Document .sha512. * testsuite/gas/i386/disassem.d: Add SHA512 tests. * testsuite/gas/i386/disassem.s: Ditto. * testsuite/gas/i386/i386.exp: Run SHA512 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sha512-intel.d: New test. * testsuite/gas/i386/sha512-inval.l: Ditto. * testsuite/gas/i386/sha512-inval.s: Ditto. * testsuite/gas/i386/sha512.d: Ditto. * testsuite/gas/i386/sha512.s: Ditto. * testsuite/gas/i386/x86-64-sha512-intel.d: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.l: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.s: Ditto. * testsuite/gas/i386/x86-64-sha512.d: Ditto. * testsuite/gas/i386/x86-64-sha512.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Rxmmq): New. (Rymm): Ditto. (PREFIX_VEX_0F38CB): Ditto. (PREFIX_VEX_0F38CC): Ditto. (PREFIX_VEX_0F38CD): Ditto. (VEX_LEN_0F38CB_P_3_W_0): Ditto. (VEX_LEN_0F38CC_P_3_W_0): Ditto. (VEX_LEN_0F38CD_P_3_W_0): Ditto. (VEX_W_0F38CB_P_3): Ditto. (VEX_W_0F38CC_P_3): Ditto. (VEX_W_0F38CD_P_3): Ditto. (prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC, PREFIX_VEX_0F38CD. (vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0, VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0. (vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3. * i386-gen.c (isa_dependencies): Add SHA512. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSHA512): New. (i386_cpu_flags): Add cpusha512. * i386-opc.tbl: Add SHA512 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel AVX-VNNI-INT16konglin17-5622/+9878
gas/ChangeLog: * NEWS: Support Intel AVX-VNNI-INT16. * config/tc-i386.c: Add avx_vnni_int16. * doc/c-i386.texi: Document avx_vnni_int16. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/avx-vnni-int16.d: New test. * testsuite/gas/i386/avx-vnni-int16.s: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F38D2_W_0): New. (PREFIX_VEX_0F38D3_W_0): Ditto. (VEX_W_0F38D2_P_0): Ditto. (VEX_W_0F38D2_P_1): Ditto. (VEX_W_0F38D2_P_2): Ditto. (VEX_W_0F38D3_P_0): Ditto. (VEX_W_0F38D3_P_1): Ditto. (VEX_W_0F38D3_P_2): Ditto. (prefix_table): Add PREFIX_VEX_0F38D2_W_0 and PREFIX_VEX_0F38D3_W_0. (vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3. (vex_w_table): Ditto. * i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16. (cpu_flag): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: (CpuAVX_VNNI_INT16): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions. * i386-tbl.h: Regenerated.
2023-07-26bpf: fix register NEG[32] instructionsJose E. Marchesi2-2/+7
This patch fixes the BPF_INSN_NEGR and BPF_INSN_NEG32R BPF instructions to not use their source registers. Tested in bpf-unknown-none. opcodes/ChangeLog: 2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src register. gas/ChangeLog: 2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: The register neg instruction gets only one argument. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu32.s: Likewise. * doc/c-bpf.texi (BPF Instructions): Update accordingly.
2023-07-26Regen bpf opcodes POTFILEAlan Modra3-7/+2
2023-07-25bpf: Add atomic compare-and-exchange instructionsDavid Faust1-0/+12
This patch adds the two remaining BPF v3 atomic instructions: - BPF_INSN_ACMP{,32}: atomic compare-and-swap - BPF_INSN_AXCHG{,32}: atomic (non-conditional) exchange Tests and documentation are also updated. gas/ * doc/c-bpf.texi (BPF Instructions): Document atomic exchange and atomic compare-and-swap instructions. * testsuite/gas/bpf/atomic.s: Test ACMP, ACMP32, AXCHG, AXCGH32 instructions. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise. include/ * opcode/bpf.h (BPF_IMM32_ACMP): Fix typo. (enum bpf_insn_id): New entries for BPF_INSN_ACMP{,32} and BPF_INSN_AXCHG{,32}. opcodes/ * bpf-opc.c (bpf_opcodes): Add entries for ACMP{,32} and AXCHG{,32} instructions.
2023-07-25bpf: Update atomic instruction pseudo-C syntaxDavid Faust1-16/+16
This patch updates the pseudo-C dialect templates for the BPF v3 atomic instructions. The templates match the strings emitted by clang -S for these instructions. The tests and documentation are updated accordingly. gas/ * doc/c-bpf.texi (BPF Instructions): Update entries for atomic and 32-bit atomic instructions. * testsuite/gas/bpf/atomic.s: Test AAND, AAND32, AOR, AOR32, AXOR, AXOR32, AFADD, AFADD32, AFAND, AFAND32, AFOR, AFOR32, AFXOR and AFXOR32 instructions. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-v1.s: New test. * testsuite/gas/bpf/atomic-v1.d: Likewise. * testuiste/gas/bpf/atomic-v1-be.d: Likewise. * testuiste/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-opc.c (bpf_opcodes): Update pseudo-C dialect templates for: BPF_INSN_AADD, BPF_INSN_AOR, BPF_INSN_AAND, BPF_INSN_AXOR, BPF_INSN_AFADD, BPF_INSN_AFOR, BPF_INSN_AFAND, BPF_INSN_AFXOR, BPF_INSN_AADD32, BPF_INSN_AOR32, BPF_INSN_AAND32, BPF_INSN_AXOR32, BPF_INSN_AFADD32, BPF_INSN_AFOR32, BPF_INSN_AFAND32, and BPF_INSN_AFXOR32 instructions.
2023-07-24Updated translations for bfd, gold and opcodesNick Clifton1-372/+341
2023-07-24bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}Jose E. Marchesi2-0/+13
This patch adds support for the BPF V4 ISA byte swap instructions to opcodes, assembler and disassembler. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_IMM32_BSWAP16): Define. (BPF_IMM32_BSWAP32): Likewise. (BPF_IMM32_BSWAP64): Likewise. (enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}. opcodes/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP* instructions. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions. * testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
2023-07-24bpf: gas,opcodes: fix pseudoc syntax for MOVS* and LDXS* insnsJose E. Marchesi2-10/+15
This patch fixes the pseudoc syntax of the V4 instructions MOVS* and LDXS* in order to reflect https://reviews.llvm.org/D144829. opcodes/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS* instructions. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): Fix pseudoc syntax for MOVS* and LDXS* instructions. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-24bpf: add support for jal/gotol jump instruction with 32-bit targetJose E. Marchesi2-0/+8
This patch adds support for the V4 BPF instruction jal/gotol, which is like ja/goto but it supports a signed 32-bit PC-relative (in number of 64-bit words minus one) target operand instead of the 16-bit signed operand of the other instruction. This greatly increases the jump range in BPF programs. Tested in bpf-unkown-none. bfd/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32. * elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc. * libbfd.h (bfd_reloc_code_real_names): Regenerate. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (struct bpf_insn): New field `id'. (md_assemble): Save the ids of successfully parsed instructions and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate. (md_apply_fix): Adapt to the new BFD reloc. * testsuite/gas/bpf/jump.s: Test JAL. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/jump-pseudoc.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump-be-pseudoc.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document new instruction jal/gotol. Document new operand type disp32. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL. (enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI. opcodes/ChangeLog: 2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entry for jal.
2023-07-21bpf: disasemble offsets of value 0 as "+0"David Faust1-2/+2
This tiny patch makes the BPF disassembler to emit, e.g. ldxdw %r1, [%r0+0] instead of ldxdw %r1, [%r00] when the offset is 0, to avoid confusion. opcodes/ * bpf-dis.c (print_insn_bpf): Print offsets with value 0 as "+0". gas/ * testsuite/gas/bpf/mem.s: Add tests with offset 0. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Update accordingly. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
2023-07-21bpf: opcodes, gas: support for signed load V4 instructionsJose E. Marchesi2-0/+15
This commit adds the signed load to register (ldxs*) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entries for signed load instructions. (BPF_MODE_SMEM): Define. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW} instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: Add signed load instructions. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document the signed load instructions.
2023-07-21bpf: opcodes, gas: support for signed register move V4 instructionsJose E. Marchesi2-0/+17
This commit adds the signed register move (movs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu.d: Add expected results. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-21bpf: add missing bpf-dis.c to opcodes/Makefile.amJose E. Marchesi3-0/+8
This was breaking --enable-targets=all builds. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c * Makefile.in: Regenerate.
2023-07-21DesCGENization of the BPF binutils portJose E. Marchesi12-6380/+680
CGEN is cool, but the BPF architecture is simply too bizarre for it. The weird way of BPF to handle endianness in instruction encoding, the weird C-like alternative assembly syntax, the weird abuse of multi-byte (or infra-byte) instruction fields as opcodes, the unusual presence of opcodes beyond the first 32-bits of some instructions, are all examples of what makes it a PITA to continue using CGEN for this port. The bpf.cpu file is becoming so complex and so nested with p-macros that it is very difficult to read, and quite challenging to update. Also, every time we are forced to change something in CGEN to accommodate BPF requirements (which is often) we have to do extensive testing to make sure we do not break any other target using CGEN. This is getting un-maintenable. So I have decided to bite the bullet and revamp/rewrite the port so it no longer uses CGEN. Overall, this involved: * To remove the cpu/bpf.{cpu,opc} descriptions. * To remove the CGEN generated files. * To replace the CGEN generated opcodes table with a new hand-written opcodes table for BPF. * To replace the CGEN generated disassembler wih a new disassembler that uses the new opcodes. * To replace the CGEN generated assembler with a new assembler that uses the new opcodes. * To replace the CGEN generated simulator with a new simulator that uses the new opcodes. [This is pushed in GDB in another patch.] * To adapt the build systems to the new situation. Additionally, this patch introduces some extensions and improvements: * A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These relocations are used for section-relative 16-bit offsets used in load/store instructions. * The disassembler now has support for the "pseudo-c" assembly syntax of BPF. What dialect to use when disassembling is controlled by a command line option. * The disassembler now has support for dumping instruction immediates in either octal, hexadecimal or decimal. The used output base is controlled by a new command-line option. * The GAS BPF test suite has been re-structured and expanded in order to test the disassembler pseudoc syntax support. Minor bugs have been also fixed there. The assembler generic tests that were disabled for bpf-*-* targets due to the previous implementation of pseudoc syntax are now re-enabled. Additional tests have been added to test the new features of the assembler. .dump files are no longer used. * The linker BPF test suite has been adapted to the command line options used by the new disassembler. The result is very satisfactory. This patchs adds 3448 lines of code and removes 10542 lines of code. Tested in: * Target bpf-unknown-none with 64-bit little-endian host and 32-bit little-endian host. * Target x86-64-linux-gnu with --enable-targets=all Note that I have not tested in a big-endian host yet. I will do so once this lands upstream so I can use the GCC compiler farm. I have not included ChangeLog entries in this patch: these would be massive and not very useful, considering this is pretty much a rewrite of the port. I beg the indulgence of the global maintainers.
2023-07-21x86: adjust disassembly of insns operating on selector valuesJan Beulich1-6/+6
Bring disassembly back in line with what the assembler accepts, thus also making it self-consistent (with, in particular selector load/store insns). While there further add D to all affected insns except ARPL (where S is used, matching LAR/LSL), to also behave correctly in suffix- always mode. While there also hook up the Intel variant of the LKGS test.
2023-07-21x86: simplify disassembly of LAR/LSLJan Beulich1-14/+2
For whatever reason in c9f5b96bdab0 ("x86: correct handling of LAR and LSL") I didn't realize that we can easily use Sv instead of going through mod_table[]. Redo this aspect of that change.
2023-07-19Updated Romainian translation for the opcodes directoryNick Clifton1-374/+344
2023-07-18RISC-V: Supports Zcb extension.Jiawei2-0/+42
This patch support Zcb extension, contains new compressed instructions, some instructions depend on other existed extension, like 'zba', 'zbb' and 'zmmul'. Zcb also imply Zca extension to enable the compressing features. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcb.d: New test. * testsuite/gas/riscv/zcb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_LBU): New opcode. (MASK_C_LBU): New mask. (MATCH_C_LHU): New opcode. (MASK_C_LHU): New mask. (MATCH_C_LH): New opcode. (MASK_C_LH): New mask. (MATCH_C_SB): New opcode. (MASK_C_SB): New mask. (MATCH_C_SH): New opcode. (MASK_C_SH): New mask. (MATCH_C_ZEXT_B): New opcode. (MASK_C_ZEXT_B): New mask. (MATCH_C_SEXT_B): New opcode. (MASK_C_SEXT_B): New mask. (MATCH_C_ZEXT_H): New opcode. (MASK_C_ZEXT_H): New mask. (MATCH_C_SEXT_H): New opcode. (MASK_C_SEXT_H): New mask. (MATCH_C_ZEXT_W): New opcode. (MASK_C_ZEXT_W): New mask. (MATCH_C_NOT): New opcode. (MASK_C_NOT): New mask. (MATCH_C_MUL): New opcode. (MASK_C_MUL): New mask. (DECLARE_INSN): New opcode. * opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func. (EXTRACT_ZCB_HALFWORD_UIMM): Ditto. (ENCODE_ZCB_BYTE_UIMM): Ditto. (ENCODE_ZCB_HALFWORD_UIMM): Ditto. (VALID_ZCB_BYTE_UIMM): Ditto. (VALID_ZCB_HALFWORD_UIMM): Ditto. (enum riscv_insn_class): New extension class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operators. * riscv-opc.c: New instructions.
2023-07-14Fix loongarch build with gcc-4.5Alan Modra1-1/+1
* loongarch-opc.c (loongarch_alias_opcodes): Don't trigger gcc-4.5 bug in handling of struct initialisation.
2023-07-11x86: simplify table-referencing macrosJan Beulich1-17/+15
First of all it is entirely unclear why THREE_BYTE_TABLE_PREFIX() was introduced by bf890a93a7c4. Nothing uses the .prefix_requirement values from the two relevant entries. And then having VEX_Cn_TABLE() and friends take arguments is misleading. These aren't used (or pointlessly used in the case of VEX_C5_TABLE); the respective table index is decoded from the insn (or implied in the case of VEX_C5_TABLE).
2023-07-11x86: convert 0FXOP to just XOP in enumerator namesJan Beulich1-304/+304
There's nothing 0f-ish in XOP encodings.
2023-07-11x86: misc further register-only insns don't need to go through mod_table[]Jan Beulich4-163/+77
Several already use OP_R(), which rejects the memory forms of insns, and a few others can easily be converted to do so as well. Note that for it to be able to use BadOp() without forward declaration, OP_Skip_MODRM() is moved down. While there add the previously missing PREFIX_OPCODE to legacy opcode 0FD7.
2023-07-11x86: various operations on mask registers can avoid going through mod_table[]Jan Beulich4-296/+176
Now that we have OP_R(), use it here as well, while wiring memory-only operands to OP_M() at the same time. To keep the number of consumed opcode bytes similar to before, make BadOp() also account for VEX/XOP/ EVEX prefix bytes. To keep that change simple, convert need_vex to an actual count of prefix bytes (keeping intact all prior boolean uses of the field). Note how this improves disassembly of such bad encodings, by at least leaving a hint towards what a "nearby" instruction is. (For KSHIFT* change the immediates test testcases use, such that disassembly remains sufficiently in sync.) While there also use Ux for VPMOV{B,W,D,Q}2M, where decoding through mod_table[] was missing in the earlier scheme.
2023-07-11x86: slightly rework handling of some register-only insnsJan Beulich2-62/+53
Fold OP_MS() and OP_XS() into OP_R(), paralleling OP_M(). Use operand names (largely) matching those in the SDM. For 128-bit-only forms use Uxmm though, marking 256-bit forms as bad. This then allows no longer going through vex_len_table[] for two of the insns. Specifically _do not_ continue to mis-use v_mode.
2023-07-11x86: SIMD shift-by-immediate don't need to go through mod_table[]Jan Beulich1-54/+18
OP_MS() and OP_XS() reject memory forms of insns quite fine. This then also eliminates mis-named enumerators (we use M_1 for register forms).
2023-07-11x86: misc further memory-only insns don't need to go through mod_table[]Jan Beulich6-315/+124
Several already use OP_M(), which rejects the register forms of insns, and a few others can easily be converted to do so as well. (Note that FXSAVE_Fixup() wires through to OP_M(). Note further that OP_IndirE(), which wasn't placed very well anyway, is moved down to avoid the need to forward-declare BadOp().) Also adjust formatting of and drop PREFIX_OPCODE from a few adjacent entries.
2023-07-11x86: {,V}MOVNT* don't need to go through mod_table[]Jan Beulich3-64/+18
Most of them use Mx already for the memory operand, which rejects the register form of the insn. Use that operand type also for the two EVEX forms which so far have used EXEvexXNoBcst (and thus failed to reject the register forms), compensating by flagging broadcast as bad for all Mx. This way several other insns which don't permit embedded broadcast either are also covered at the same time.
2023-07-11x86: fold legacy/VEX {,V}MOV{H,L}* entriesJan Beulich2-68/+34
By changing decode order to do ModR/M.mod last (rather than VEX.L), the VEX entries (which are already reused by EVEX decoding) can be folded with their legacy counterparts as well. Note how this change of decode order also allows removing two auxiliary #define-s, which were introduced during earlier folding (because of that unhelpful order of steps).
2023-07-11x86: fold certain legacy/VEX table entriesJan Beulich2-305/+109
Introduce macro V to expand to 'v' in the VEX/EVEX case, and replace a couple of abort()s where legacy code can now legitimately make it. While there for {,V}LDDQU drop hoing through mod_table[] - OP_M() rejects register operands quite fine.
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich2-3/+3
The alternative is 1 byte shorter when the source is %xmm0-7, as a 2-byte VEX prefix can then be used.
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich2-21/+21
These are better expressed by the zeroing idiom {,V}PXOR. In some cases this also results in a shorter encoding.
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich2-5/+5
The {,V}PCMPEQD alternative is 1 byte shorter in many cases.
2023-07-04x86: flag bad EVEX masking for miscellaneous insnsJan Beulich6-44/+51
Masking is not permitted for certain further insns, not falling in any of the earlier categories. Introduce the Y macro (not expanding to any output) to flag such cases. Note that in a few cases entries already covered otherwise are converted as well, to continue to allow sharing of the string literals.
2023-07-04x86: flag EVEX masking when destination is GPR(-like)Jan Beulich1-1/+16
Masking is not permitted in this case. See the code comment for how this is being dealt with. To avoid excess special casing of modes, have OP_M() call OP_E_memory() directly.
2023-07-04x86: flag EVEX.z set when destination is memoryJan Beulich1-0/+7
Zeroing-masking is not permitted in this case. See the code comment for how this is being dealt with.
2023-07-04x86: flag EVEX.z set when destination is a mask registerJan Beulich1-0/+12
While only zeroing-masking is possible in this case, this still requires EVEX.z to be clear. Introduce a "global" flag right here, to be re-used by checks which need to live in specific operand handlers.
2023-07-04x86: re-work EVEX-z-without-masking checkJan Beulich1-10/+8
Rather than corrupting disassmbly altogether, flag EVEX.z set as bad when masking isn't in effect in the first place at the time the destination operand is actually processed.
2023-07-04Updated Ukranian, Romanian and German translations for various sub-directoriesNick Clifton2-747/+679
2023-07-04arc: Update neg<.f> 0,b encodingClaudiu Zissulescu1-1/+1
Wrong encoding for null destination NEG instruction. Fix it. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-07-03Change version number to 2.41.50 and regenerate filesNick Clifton3-375/+211
2023-07-03Add markers for the 2.41 branchNick Clifton1-0/+4
2023-07-03opcodes/loongarch: Mark address offset operands of LVZ/LBT insns as suchWANG Xuerui1-28/+28
opcodes/ChangeLog: * loongarch-opc.c: Mark the offset operands as "so" for {,x}v{ld,st}, {,x}v{ldrepl,stelm}.[bhwd], and {ld,st}[lr].[wd]. Signed-off-by: WANG Xuerui <git@xen0n.name>
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