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AgeCommit message (Expand)AuthorFilesLines
2024-05-21include, libctf: improve documentationNick Alcock1-32/+62
2024-05-20readelf: add pretty printing for FDO Dlopen Metadata noteLuca Boccassi1-0/+3
2024-05-17include, libctf: add a bunch of documentation to ctf-api.hNick Alcock1-50/+418
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento1-0/+2
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo1-0/+3
2024-05-14arm: remove Maverick support from BFD.Richard Earnshaw1-1/+1
2024-05-14arm: opcodes: remove Maverick disassembly.Richard Earnshaw1-5/+3
2024-05-08RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu1-1/+2
2024-04-20LoongArch: Add -mignore-start-align optionmengqinggang1-0/+1
2024-04-17aarch64: Remove asserts from operand qualifier decoders [PR31595]Victor Do Nascimento1-0/+3
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei2-0/+32
2024-04-07gdb: ignore -Wregister instead of -Wdeprecated-registerSimon Marchi2-6/+12
2024-03-28RISC-V: Removed privileged spec 1.9.1 support in assembler.Nelson Chu1-204/+185
2024-03-19gas, aarch64: Add faminmax extensionSaurabh Jha1-0/+2
2024-03-18aarch64: Add support for (M)ADDPT and (M)SUBPT instructionsYury Khrustalev1-0/+3
2024-03-08RISC-V: Support Zabha extension.Jiawei2-0/+55
2024-03-01s390: Warn when register name type does not match operandJens Remus1-0/+3
2024-02-29Synchronize GCC compile plugin headersTom Tromey3-4/+26
2024-02-29RISC-V: Add TLSDESC reloc definitions.Tatsuyuki Ishi1-0/+5
2024-02-27aarch64: rename internals related to PAuth feature to use pauth in their nami...Matthieu Longo1-2/+2
2024-02-24xtensa: move xtensa_make_property_section from bfd to gasAlan Modra1-1/+1
2024-02-20kvx: gas: rename: or -> ior, xor -> eorPaul Iannetta1-1382/+1431
2024-02-20kvx: gas: move the splat modifier to the immediatePaul Iannetta1-1915/+1864
2024-02-19arm: Add support for Armv9.5-AClaudio Bantaloukas1-0/+1
2024-02-14arc: Put DBNZ instruction to a separate classYuriy Kolerov2-0/+5
2024-02-12Add support to readelf for the PT_OPENBSD_SYSCALLS segment type.Frederic Cambus2-0/+5
2024-02-08x86-64: Add R_X86_64_CODE_6_GOTTPOFFH.J. Lu1-0/+20
2024-01-29bpf: there is no ldinddw nor ldabsdw instructionsJose E. Marchesi2-2/+7
2024-01-26LoongArch: gas: Add support for s9 registermengqinggang1-0/+1
2024-01-25riscv64-pei uninitialised data writing relocsAlan Modra1-0/+2
2024-01-23aarch64: Include +predres2 in -march=armv8.9-aAndrew Carlotti1-2/+2
2024-01-22sim: Fix -Werror=shadow=local by changing mem to addr in sim_{read,write}Mark Wielaard1-2/+2
2024-01-17Import gcc commit 65388b28656d65595bdaf191df85af81c35ca63 which adds support ...Nick Clifton1-0/+2
2024-01-15Add markers for 2.42 branchNick Clifton1-0/+4
2024-01-15aarch64: rcpc3: Add integer load/store insnsVictor Do Nascimento1-0/+1
2024-01-15aarch64: rcpc3: New RCPC3_ADDR operand typesVictor Do Nascimento1-0/+5
2024-01-15aarch64: rcpc3: Define address operand fields and inserter/extractorsVictor Do Nascimento1-2/+4
2024-01-15aarch64: rcpc3: Create implicit load/store size calc functionVictor Do Nascimento1-0/+3
2024-01-15aarch64: rcpc3: Add +rcpc3 architectural feature support flagVictor Do Nascimento1-0/+2
2024-01-15aarch64: Refactor aarch64_sys_ins_reg_supported_pAndrew Carlotti1-1/+5
2024-01-15aarch64: Remove unused BTI feature bitAndrew Carlotti1-3/+0
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni1-0/+3
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni1-1/+4
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni1-2/+8
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni1-0/+11
2024-01-15aarch64: Add support for FEAT_B16B16 instructions.Srinath Parvathaneni1-0/+2
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +wfxt flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +rcpc2 flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +jscvt flag for existing fjcvtzs instructionAndrew Carlotti1-1/+4
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