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2016-02-08FIx formatting that triggers a new compile time warning message.Nick Clifton2-2/+7
* config/tc-ia64.c (dot_prologue): Fix formatting.
2016-02-04Remove support for creating ARM NOREAD sections.Nick Clifton7-91/+10
gas * config/obj-elf.c (obj_elf_change_section): Remove support for ARM NOREAD sections. * config/tc-arm.c (arm_elf_section_letter): Delete. * config/tc-arm.h (md_elf_section_letter): Delete. * doc/c-arm.texi (ARM Section Attribute): Delete section. * testsuite/gas/arm/section-execute-only.d: Delete. * testsuite/gas/arm/section-execute-only.s: Delete. ld * testsuite/ld-arm/arm-elf.exp: Remove ARM NOREAD section tests. * testsuite/ld-arm/thumb1-input-section-flag-match.d: Delete. * testsuite/ld-arm/thumb1-input-section-flag-match.s: Delete. * testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.d: Delete. * testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.s: Delete. * testsuite/ld-arm/thumb1-noread-present-one-section.d: Delete. * testsuite/ld-arm/thumb1-noread-present-one-section.s: Delete. * testsuite/ld-arm/thumb1-noread-present-two-section.d: Delete. * testsuite/ld-arm/thumb1-noread-present-two-section.s: Delete.
2016-02-04Fix the encoding of the MSP430's RRUX instruction.Nick Clifton4-87/+51
PR target/19561 opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for decoding an RRC instruction with the ZC bit set in the extension word. include * opcode/msp430.h (IGNORE_CARRY_BIT): New define. (RRUX): Synthesise using case 2 rather than 7. gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2 to handle encoding of RRUX instruction. * testsuite/gas/msp430/msp430x.s: Add more tests of the extended shift instructions. * testsuite/gas/msp430/msp430x.d: Update expected disassembly.
2016-02-03xtensa: fix signedness of gas relocationsMax Filippov5-3/+31
Change 1058c7532d0b "Use signed data type for R_XTENSA_DIFF* relocation offsets." changed signedness of BFD_RELOC_XTENSA_DIFF* relocations substituted for BFD_RELOC_*. This made it impossible to encode arbitrary 8-, 16- and 32-bit values, which broke e.g. debug info encoding by .loc directive. Revert this part and add test. gas/ 2016-02-03 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF* substitutions for BFD_RELOC_* as unsigned. * gas/testsuite/gas/xtensa/all.exp: Add loc to list of xtensa tests. * gas/testsuite/gas/xtensa/loc.d: New file: loc test result patterns. * gas/testsuite/gas/xtensa/loc.s: New file: loc test.
2016-02-03Add -mrelax-relocations= to x86 assemblerH.J. Lu18-5/+215
The x86 relax relocations introduced in binutils 2.26 aren't supported by linker on Solaris older than Solaris 12. To use x86 assembler with older Solaris linker, this patch adds 1. A command line option -mrelax-relocations= to x86 assembler to control whether to generate relax relocations. 2. A configure option --enable-x86-relax-relocations to decide whether x86 assembler should generate relax relocations by default. It is defaulted to yes, except for x86 Solaris targets older than Solaris 12. gas/ PR gas/19520 * NEWS: Mention new command line option -mrelax-relocations and new configure option --enable-x86-relax-relocations for x86 target. * config.in: Regenerated. * configure.ac: Add --enable-x86-relax-relocations. (ac_default_x86_relax_relocations): New. Default to 1 except for x86 Solaris targets older than Solaris 12. (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define. * configure: Likewise. * config/tc-i386.c (generate_relax_relocations): New. (OPTION_MRELAX_RELOCATIONS): Likewise. (output_disp): Don't generate relax relocations if generate_relax_relocations is 0. (md_longopts): Add -mrelax-relocations. (md_show_usage): Likewise. (md_parse_option): Handle OPTION_MRELAX_RELOCATIONS. * doc/c-i386.texi: Document -mrelax-relocations=. * testsuite/gas/i386/got-no-relax.d: New file. * testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise. * testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as. * testsuite/gas/i386/localpic.d: Likewise. * testsuite/gas/i386/mixed-mode-reloc32.d: Likewise. * testsuite/gas/i386/reloc32.d: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Likewise. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. * testsuite/gas/i386/i386.exp: Run got-no-relax and x86-64-gotpcrel-no-relax. ld/ PR gas/19520 * testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as. * testsuite/ld-i386/call1.d: Likewise. * testsuite/ld-i386/call2.d: Likewise. * testsuite/ld-i386/call3a.d: Likewise. * testsuite/ld-i386/call3b.d: Likewise. * testsuite/ld-i386/call3c.d: Likewise. * testsuite/ld-i386/call3d.d: Likewise. * testsuite/ld-i386/call3e.d: Likewise. * testsuite/ld-i386/call3f.d: Likewise. * testsuite/ld-i386/call3g.d: Likewise. * testsuite/ld-i386/call3h.d: Likewise. * testsuite/ld-i386/jmp1.d: Likewise. * testsuite/ld-i386/jmp2.d: Likewise. * testsuite/ld-i386/lea1c.d: Likewise. * testsuite/ld-i386/load1.d: Likewise. * testsuite/ld-i386/load2.d: Likewise. * testsuite/ld-i386/load3.d: Likewise. * testsuite/ld-i386/load4a.d: Likewise. * testsuite/ld-i386/load5a.d: Likewise. * testsuite/ld-i386/mov2b.d: Likewise. * testsuite/ld-i386/mov3.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise. * testsuite/ld-x86-64/call1a.d: Likewise. * testsuite/ld-x86-64/call1b.d: Likewise. * testsuite/ld-x86-64/call1c.d: Likewise. * testsuite/ld-x86-64/call1d.d: Likewise. * testsuite/ld-x86-64/call1e.d: Likewise. * testsuite/ld-x86-64/call1f.d: Likewise. * testsuite/ld-x86-64/call1h.d: Likewise. * testsuite/ld-x86-64/call1i.d: Likewise. * testsuite/ld-x86-64/load1a.d: Likewise. * testsuite/ld-x86-64/load1b.d: Likewise. * testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it. * testsuite/ld-i386/got1.dd: Updated. * testsuite/ld-i386/got1d.S (1): Removed. * testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2016-02-03msp430: Set DWARF2_ADDR_SIZE to 4.Kevin Buettner2-0/+6
This change makes gas's notion of the msp430 dwarf2 address size match that of gcc and gdb. This is needed so that the format of addresses generated for DW_LNE_set_address in .debug_line will match the address size for the compilation unit. In gcc/config/msp430/msp430.h, it's set to 4: #define DWARF2_ADDR_SIZE 4 Likewise in gdb/msp430-tdep.c: set_gdbarch_dwarf2_addr_size (gdbarch, 4); (As far as I can tell, however, GDB doesn't use this value when decoding .debug_line. Instead, GDB uses the Pointer Size from the compilation unit.) readelf is able to seamlessly handle mismatches between these various sizes by using the size of the DW_LNE_set_address instruction to determine the address size. Another way to fix this problem is to make GDB behave in a similar manner. In my opinion, GDB should detect and inform the user about these mismatches; it's not clear to me if it's correct for GDB to go ahead and read the address anyway when a size mismatch is detected. Without this change, addresses in .debug_line are encoded in two bytes for some multilibs. When GDB reads the address for DW_LNE_set_address, it uses the pointer size provided by the CU. When these values don't match, GDB reads the wrong number of bytes. In the cases that I've looked at, GDB is reading 4 bytes from a 2 byte container, which results in a garbage address. GDB discards lines which have a bogus address; the end result is that GDB records no line number information for CUs which have a mismatch between the address size (from the CU) and the format of the address used by DW_LNE_set_address. gas/ChangeLog: * config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
2016-02-03Mention -mfence-as-lock-add=yes for x86 assemblerH.J. Lu2-0/+8
* NEWS: Mention new command line option -mfence-as-lock-add=yes for x86 target.
2016-02-03Remove duplicated marker for 2.26 in gas/NEWSH.J. Lu2-2/+4
* NEWS: Remove duplicated marker for 2.26.
2016-02-02[GAS][ARM]Skip none elf target for testsuite/gas/arm/thumb2_it_search.sRenlin Li2-1/+6
gas/ * testsuite/gas/arm/thumb2_it_search.d: Skip non-elf targets.
2016-02-02gas/ip2k: Add all instructions assembler testAndrew Burgess4-0/+1619
Basic all instructions assembler test, auto-generated by CGEN, then fixed by hand for some cases where CGEN had generated invalid instruction operands. gas/ChangeLog: * testsuite/gas/ip2k/allinsn.d: New file. * testsuite/gas/ip2k/allinsn.s: New file. * testsuite/gas/ip2k/ip2k-allinsn.exp: New file.
2016-02-02epiphany/gas: Update expected test results for 0 offset loadsAndrew Burgess4-14/+21
In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 some of the load instructions with a zero offset (where the offset is not mentioned) were marked as NO-DIS, meaning that the disassembler must display the offset, even though it is zero. This change seems a little strange to me as it was only applied to some loads, not all, and the same change was not applied to the stores. However, I'm reluctant to revert a specific change to the assembler, when the output is obviously correct. With this commit then I simply bring the expected assembler test results into line with what is actually produced. gas/ChangeLog: * testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to some load instructions. * testsuite/gas/epiphany/allinsn.d: Likewise. * testsuite/gas/epiphany/regression.d: Likewise.
2016-02-02epiphany/gas: Remove .l suffix from expected test resultsAndrew Burgess5-817/+825
In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 all instruction aliases that have a '.l' suffix were marked as NO-DIS, so the disassembler will not display them, in preference to the instruction without the suffix. However, the gas testsuite was not updated at the time, this commit fixes that oversight. gas/ChangeLog: * testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l' suffixes from instruction mnemonics in expected output. * testsuite/gas/epiphany/allinsn.d: Likewise. * testsuite/gas/epiphany/regression.d: Likewise. * testsuite/gas/epiphany/sample.d: Likewise.
2016-02-02gas/epiphany: Update expected register names in testsAndrew Burgess4-241/+248
In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 the register aliases sb, sl, and ip were made less preferred than r9, r10, and r12, however, the expected test results were not updated. This commit fixes this oversight and updates the test results. gas/ChangeLog: * testsuite/gas/epiphany/addr-syntax.d: Update expected register names. * testsuite/gas/epiphany/allinsn.d: Likewise. * testsuite/gas/epiphany/sample.d: Likewise.
2016-02-02epiphany/disassembler: Improve alignment of output.Andrew Burgess2-1/+5
Always set the bytes_per_line field (of struct disassemble_info) to the same constant value, this is inline with the advice contained within include/dis-asm.h. Setting this field to a constant value will cause the disassembler output to be better aligned. cpu/ChangeLog: * epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to a constant to better align disassembler output. opcodes/ChangeLog: * epiphany-dis.c: Regenerated from latest cpu files. gas/ChangeLog: * testsuite/gas/epiphany/sample.d: Update expected output.
2016-02-01Fix ARC TLS support.Claudiu Zissulescu4-2/+54
* config/tc-arc.c (md_apply_fix): Allow addendum. (arc_reloc_op): Allow complex expressions for tpoff. (md_apply_fix): Handle resolved TLS local symbol. * gas/arc/tls-relocs1.d: New file. * gas/arc/tls-relocs1.s: Likewise.
2016-02-01Fix a problem building the ARM assembler using LLVM.Loria2-1/+10
PR target/19311 * config/tc-arm.c (encode_arm_immediate): Recode to improve efficiency and avoid an LLVM loop optimization bug.
2016-02-01Fix error building Microblaze assembler on a 32-bit host.Nick Clifton2-2/+8
* config/tc-microblaze.c (parse_imm): Fix compile time warning message extending a negative 32-bit value into a larger signed value on a 32-bit host.
2016-01-29Replace == with = in gas/configure.acH.J. Lu3-2/+8
PR gas/19532 * configure.ac (compressed_debug_sections): Replace == with =. * configure: Regenerated.
2016-01-29Add testsuite/ to the last gas ChangeLog entryH.J. Lu1-6/+6
2016-01-29Add option -mfence-as-lock-add=[no|yes].Andrew Senkevich9-0/+131
With -mfence-as-lock-add=yes lfence, mfence and sfence will be encoded as lock addl $0x0, (%{r,e}sp). gas/: * config/tc-i386.c (avoid_fence): New. (output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence is true. (OPTION_FENCE_AS_LOCK_ADD): New. (md_longopts): Add -mfence-as-lock-add. (md_parse_option): Handle -mfence-as-lock-add. (md_show_usage): Add -mfence-as-lock-add=[no|yes]. * doc/c-i386.texi (-mfence-as-lock-add): Document. gas/testsuite/: * gas/i386/i386.exp: Run new tests. * gas/i386/fence-as-lock-add.s: New. * gas/i386/fence-as-lock-add-yes.d: Likewise. * gas/i386/fence-as-lock-add-no.d: Likewise. * gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise. * gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
2016-01-27Remove trailing `]' in --enable-compressed-debug-sectionsH.J. Lu3-2/+7
* configure.ac (compressed_debug_sections): Remove trailing `]'. * configure: Regenerated.
2016-01-26Skip thumb2 conditional backward search test for PE based targets.Nick Clifton1-1/+1
* testsuite/gas/arm/thumb2_it_search.d: Skip for PE targets.
2016-01-25Rename OPTION_OMIT_LOCK_PREFIX to OPTION_MOMIT_LOCK_PREFIXH.J. Lu2-3/+10
Use OPTION_MXXX for -mxxx option in x86 assembler. * config/tc-i386.c (OPTION_OMIT_LOCK_PREFIX): Renamed to ... (OPTION_MOMIT_LOCK_PREFIX): This. (md_longopts): Updated. (md_parse_option): Likewise.
2016-01-25Avoid the use of gp-relative addressing when abicalls are in effect.Catherine Moore5-0/+33
2016-01-25[PATCH[ARM]Check mapping symbol while backward searching for IT block.Renlin Li3-0/+25
opcodes/ * arm-dis.c (mapping_symbol_for_insn): New function. (find_ifthen_state): Call mapping_symbol_for_insn(). gas/ * testsuite/gas/arm/thumb2_it_search.d: New. * testsuite/gas/arm/thumb2_it_search.s: New.
2016-01-21Fix gas testsuite failures for ARM netbesdelf configuration.Nick Clifton3-3/+9
PR gas/19454 * testsuite/gas/arm/mapshort-elf.d: Fix expected output to cope with arm-netbsdelf target. * testsuite/gas/arm/blx-bl-convert.d: Skip for netbsdelf.
2016-01-20Fix unexpected failures in GAS testsuite for ARM VxWorks target.Nick Clifton9-21/+32
PR 19456 * testsuite/gas/arm/weakdef-1.d: Skip for VxWorks. * testsuite/gas/arm/blx-bl-convert.d * testsuite/gas/arm/plt-1.d: Likewise. * testsuite/gas/arm/reloc-bad.d: Likewise. * testsuite/gas/arm/thumb-w-good.d: Likewise. * testsuite/gas/arm/thumb2_pool.d: Likewise. * testsuite/gas/arm/ldconst.d: Adjust so that it works with VxWorks * testsuite/gas/arm/tls_vxworks.d: Update expected output.
2016-01-20Upda the documentation on assembler error message generation.Nick Clifton2-8/+31
PR 19499 * doc/as.texinfo (Errors): Correct documentation describing the interaction of .file and .line with warning and error messages.
2016-01-20Skip ARM v8 tests for COFF based targets.Nick Clifton4-0/+10
2016-01-20[AArch64] Reject invalid immediate operands to MSR UAOMatthew Wahab4-0/+23
In the instruction to write to the ARMv8.2 PSTATE field UAO, MSR UAO, #<imm>, the immediate should be either 0 or 1 but GAS accepts any unsigned 4-bit integer. This patch implements the constraint on the immediate, generating an error if the immediate operand is invalid, and adds tests for the illegal forms. opcodes/ 2016-01-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Check validity of MSR UAO immediate operand. gas/ 2016-01-20 Matthew Wahab <matthew.wahab@arm.com> * testsuite/gas/aarch64/armv8_2-a-illegal.d: New. * testsuite/gas/aarch64/armv8_2-a-illegal.l: New. * testsuite/gas/aarch64/armv8_2-a-illegal.s: New. Change-Id: Ibdec4967c00b1ef3be9dbc43d23b2c70d1a0b28c
2016-01-20Add support for an ARM specific 'y' section attribute flag to mark the ↵Mickael Guene7-0/+106
section as NOREAD. bfd/ChangeLog: * elf32-arm.c ((elf32_arm_special_sections): Remove catch of noread section using '.text.noread' pattern. gas/ChangeLog: * config/obj-elf.c (obj_elf_change_section) : Allow arm section with SHF_ARM_NOREAD section flag. * config/tc-arm.h (md_elf_section_letter) : Implement this hook to handle letter 'y'. (arm_elf_section_letter) : Declare it. * config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set SHF_ARM_NOREAD section flag. * doc/c-arm.texi (ARM section attribute 'y'): Document it. gas/testsuite/ChangeLog: * gas/arm/section-execute-only.s: New test case. * gas/arm/section-execute-only.d: Expected output. ld/testsuite/ChangeLog: * ld-arm/thumb1-noread-not-present-mixing-two-section.s: Add 'y' attribute usage. * ld-arm/thumb1-noread-present-one-section.s: Likewise. * ld-arm/thumb1-noread-present-two-section.s: Likewise. * ld-arm/thumb1-input-section-flag-match.s: Likewise. binutils/ChangeLog: * readelf.c (get_elf_section_flags): Display y letter for section with SHF_ARM_NOREAD section flag in readelf section output. (process_section_headers): Add y letter in readelf section output key mapping for ARM architecture.
2016-01-18MIPS: Remove remnants of 48-bit microMIPS instruction supportMaciej W. Rozycki2-4/+7
The POOL48A major opcode was defined in early revisions of the 64-bit microMIPS ISA, has never been implemented, and was removed before the 64-bit microMIPS ISA specification[1] has been finalized. This complements commit a6c7053929dd ("MIPS/opcodes: Remove microMIPS 48-bit LI instruction"). References: [1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of Major Opcode Field", p. 578 gas/ * config/tc-mips.c (micromips_insn_length): Remove the mention of 48-bit microMIPS instructions. gdb/ * mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS instruction support. (micromips_next_pc): Likewise. (micromips_scan_prologue): Likewise. (micromips_deal_with_atomic_sequence): Likewise. (micromips_stack_frame_destroyed_p): Likewise. (mips_breakpoint_from_pc): Likewise. opcodes/ * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS instruction support.
2016-01-18Provide AC_PROG_LEX that copes with LEX=missing from top-levelAlan Modra2-4/+9
config/ PR binutils/19481 * override.m4 (AC_PROG_LEX): Define. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. ld/ * configure: Regenerate.
2016-01-17Regen configureAlan Modra2-1/+5
Picks up 2016-01-12 libtool.m4 change. bfd/ * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2016-01-17m68hc11/12 and xgate config.sub weirdnessAlan Modra2-1/+5
Oddly, config.sub converts a duple ending in -elf for these target to -unknown-none, which means they aren't seen as elf targets by binutils. So, counter that. This exposes a number of testsuite issues (ones you would have seen if configuring with a full triple, say m68hc11-unknown-elf). binutils/ * testsuite/lib/binutils-common.exp (is_elf_format): Return true for m68hc11/12 and xgate triples. gas/ * testsuite/gas/cfi/cfi.exp: Exclude m68hc11/12 from m68k test. ld/ * testsuite/lib/ld-lib.exp (check_shared_lib_support): Exclude xgate. * testsuite/ld-elf/endsym.d: xfail m68hc11/12 and xgate. * testsuite/ld-elf/pr14156a.d: Likewise. * testsuite/ld-elf/pr14926.d: Don't run for m68hc11/12 and xgate. * testsuite/ld-elf/sec64k.exp: Likewise.
2016-01-14Fix display of RL78 MOVW instructions that use the stack pointer.Nick Clifton4-0/+30
* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw instructions that can support stack pointer operations. * rl78-decode.c: Regenerate. * rl78-dis.c: Fix display of stack pointer in MOVW based instructions. * testsuite/gas/rl78/sp-relative-movw.s: New test. * testsuite/gas/rl78/sp-relative-movw.d: Expected disassembly. * testsuite/gas/rl78/rl78.exp: Run the new test.
2016-01-14[AArch64] Fix missing architecture checks for ARMv8.2 system registers.Matthew Wahab3-0/+57
Some of the RAS system registers added to binutils as part of the ARMv8.2 support are missing the feature checks to warn when they aren't supported by the target. This patch adds the missing feature checks with a test to check that the correct warnings are given for all the ARMv8.2 system registers. gas/ 2016-01-14 Matthew Wahab <matthew.wahab@arm.com> * testsuite/gas/aarch64/illegal-sysreg-2.l: New. * testsuite/gas/aarch64/illegal-sysreg-2.d: New. opcodes/ 2016-01-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals testing for RAS support. Add checks for erxfr_el1, erxctlr_el1, erxtatus_el1 and erxaddr_el1. Change-Id: I66b590ea49c1eb6b0e5c93e0dc2bc9c4e79a52fe
2016-01-13Nios II/GAS: Fix build error in `output_movia'Maciej W. Rozycki2-1/+5
Fix: cc1: warnings being treated as errors .../gas/config/tc-nios2.c: In function 'output_movia': .../gas/config/tc-nios2.c:3474: warning: 'code' may be used uninitialized in this function make[4]: *** [tc-nios2.o] Error 1 seen with GCC 4.1.2 and 4.4.7. gas/ * config/tc-nios2.c (output_movia): Preset `code' to 0.
2016-01-13Remove spurious condition in test for closing parenthesis.Yoshinori Sato2-1/+6
* config/tc-h8300.c (get_operand): Remove spurious condition in test for closing parenthesis.
2016-01-12[ARM] Support ARMv8.2 RAS extension.Matthew Wahab4-0/+111
The ARMv8.2 architecture includes the RAS extension which adds an instruction, ESB, and a number of coprocessor registers. This patch adds the instruction to binutils, making it available when -march=armv8.2-a is selected. It also adds tests for the instruction and for the coprocessor registers. gas/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (arm_ext_v8_2): New. (insns): Add "esb". * testsuite/gas/arm/armv8_2-a.d: New. * testsuite/gas/arm/armv8_2-a.s: New. opcodes/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * arm-dis.c (arm_opcodes): Add "esb". (thumb_opcodes): Likewise. Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34
2016-01-12PowerPC gas test vsx3Alan Modra2-0/+5
Tweak for padding, now present for COFF. * testsuite/gas/ppc/vsx3.d: Accept nop padding.
2016-01-11Delete opcodes that have been removed from ISA 3.0.Peter Bergner5-20/+8
opcodes/ * ppc-opc.c <xscmpnedp>: Delete. <xvcmpnedp>: Likewise. <xvcmpnedp.>: Likewise. <xvcmpnesp>: Likewise. <xvcmpnesp.>: Likewise. gas/ * testsuite/gas/ppc/power9.d <xscmpnedp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp.>: Delete tests. * testsuite/gas/ppc/power9.s: Likewise. * testsuite/gas/ppc/vsx3.d: Likewise. * testsuite/gas/ppc/vsx3.s: Likewise.
2016-01-08m68k: fix constraints of move.[bw] for ISA_B/CAndreas Schwab5-0/+27
For ISA_B/C only the combination #,d(An) is allowed in addition to the ISA_A combinations for move.b and move.w (and pc-relative is never allowed as destination). opcodes/ PR gas/13050 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in addition to ISA_A. gas/ PR gas/13050 * testsuite/gas/m68k/all.exp: Add tests p13050-1 and p13050-2. * testsuite/gas/m68k/p13050-1.s: New file. * testsuite/gas/m68k/p13050-2.d: New file. * testsuite/gas/m68k/p13050-2.s: New file.
2016-01-06bfd/arc: Add R_ prefix to all relocation namesAndrew Burgess31-98/+131
The convention within for relocation names is that they start with the string "R_", however, this is not so for ARC for the display names of relocations, however, internally, the names for the relocations types do have the 'R_' prefix. I suspect that the missing 'R_' on the output strings was an oversight, as I can't see any comment to the contrary. To bring ARC into line with other targets, this commit adds the 'R_' prefix to the output strings used for relocation names, and updates all of the assembler tests where this was exposed. bfd/ChangeLog: * elf32-arc.c (reloc_type_to_name): Change ARC_RELOC_HOWTO to place 'R_' before the reloc name returned. (elf_arc_howto_table): Change ARC_RELOC_HOWTO to place 'R_' before the relocation string. gas/ChangeLog: * testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names. * testsuite/gas/arc/add.d: Likewise. * testsuite/gas/arc/and.d: Likewise. * testsuite/gas/arc/asl.d: Likewise. * testsuite/gas/arc/asr.d: Likewise. * testsuite/gas/arc/bic.d: Likewise. * testsuite/gas/arc/extb.d: Likewise. * testsuite/gas/arc/extw.d: Likewise. * testsuite/gas/arc/j.d: Likewise. * testsuite/gas/arc/jl.d: Likewise. * testsuite/gas/arc/ld2.d: Likewise. * testsuite/gas/arc/lsr.d: Likewise. * testsuite/gas/arc/mov.d: Likewise. * testsuite/gas/arc/or.d: Likewise. * testsuite/gas/arc/pcl-relocs.d: Likewise. * testsuite/gas/arc/pcrel-relocs.d: Likewise. * testsuite/gas/arc/pic-relocs.d: Likewise. * testsuite/gas/arc/plt-relocs.d: Likewise. * testsuite/gas/arc/rlc.d: Likewise. * testsuite/gas/arc/ror.d: Likewise. * testsuite/gas/arc/rrc.d: Likewise. * testsuite/gas/arc/sbc.d: Likewise. * testsuite/gas/arc/sda-relocs.d: Likewise. * testsuite/gas/arc/sda-relocs2.d: Likewise. * testsuite/gas/arc/sexb.d: Likewise. * testsuite/gas/arc/sexw.d: Likewise. * testsuite/gas/arc/st.d: Likewise. * testsuite/gas/arc/sub.d: Likewise. * testsuite/gas/arc/tls-relocs.d: Likewise. * testsuite/gas/arc/xor.d: Likewise.
2016-01-01Copyright update for binutilsAlan Modra552-554/+558
2016-01-01New 2016 binutils ChangeLog filesAlan Modra1-0/+14
Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01binutils ChangeLog rotationAlan Modra2-0/+0
2015-12-30Fix assorted ChangeLog errorsAlan Modra2-23/+23
2015-12-24Add assembler support for ARMv8-M BaselineThomas Preud'homme7-20/+194
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards to merging with ARMv8-M Baseline. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch value. gas/ * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions shared between ARMv6T2 and ARMv8-M. (move_or_literal_pool): Check mov.w/mvn and movw availability against arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking arm_arch_t2. (do_t_branch): Error out for wide conditional branch instructions if targetting ARMv8-M Baseline. (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions in ARMv8-M Baseline. (wide_insn_ok): New function. (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and adapt error message for unsupported wide instruction to ARMv8-M Baseline. (insns): Reorganize instructions shared by ARMv8-M Baseline and ARMv6t2 architecture. (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and marvell-whitney cores. (arm_archs): Define armv8-m.base architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version. (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well. gas/testsuite/ * gas/arm/archv8m-base.d: New file. * gas/arm/attr-march-armv8m.base.d: Likewise. * gas/arm/armv8m.base-idiv.d: Likewise. * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare. include/opcode/ * arm.h (ARM_EXT2_V6T2_V8M): New extension bit. (ARM_AEXT2_V8A): New architecture extension bitfield. (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_AEXT_V8M_BASE): New architecture extension bitfield. (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M. (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension bitfield. (ARM_ARCH_V6KT2): Likewise. (ARM_ARCH_V6ZT2): Likewise. (ARM_ARCH_V6KZT2): Likewise. (ARM_ARCH_V7): Likewise. (ARM_ARCH_V7A): Likewise. (ARM_ARCH_V7VE): Likewise. (ARM_ARCH_V7R): Likewise. (ARM_ARCH_V7M): Likewise. (ARM_ARCH_V7EM): Likewise. (ARM_ARCH_V8A): Likewise. (ARM_ARCH_V8M_BASE): New architecture bitfield. (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M. (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension bitfield and reindent. (ARM_ARCH_V7A_MP_SEC): Likewise. (ARM_ARCH_V7R_IDIV): Likewise. (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex, ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24Add assembler support for ARMv8-M MainlineThomas Preud'homme8-25/+217
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in comb array. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch value. (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use value. gas/ * config/tc-arm.c (arm_ext_m): Include ARMv8-M. (arm_ext_v8m): New feature for ARMv8-M. (arm_ext_atomics): New feature for ARMv8 atomics. (do_tt): New encoding function for TT* instructions. (insns): Add new entries for ARMv8-M specific instructions and reorganize the ones shared by ARMv8-M Mainline and ARMv8-A. (arm_archs): Define armv8-m.main architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and clarify the ordering rule. (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile to 'A' if extension bit for atomic instructions is set, unless it is ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0 for ARMv8-M Mainline. gas/testsuite/ * gas/arm/archv8m.s: New file. * gas/arm/archv8m-main.d: Likewise. * gas/arm/attr-march-armv8m.main.d: Likewise. * gas/arm/any-armv8m.s: Likewise. * gas/arm/any-armv8m.d: Likewise. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare. (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN. (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15. include/opcode/ * arm.h (ARM_EXT2_ATOMICS): New extension bit. (ARM_EXT2_V8M): Likewise. (ARM_EXT_V8): Adjust comment with regards to atomics and remove mention of legacy use for that bit. (ARM_AEXT2_V8_1A): New architecture extension bitfield. (ARM_AEXT2_V8_2A): Likewise. (ARM_AEXT_V8M_MAIN): Likewise. (ARM_AEXT2_V8M): Likewise. (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield. (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A. (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A. (ARM_ARCH_V8M_MAIN): New architecture feature bitfield. (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield and reindent. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of feature bits. (ARM_ARCH_V8_1A_SIMD): Likewise. (ARM_ARCH_V8_1A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl, stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of ARM_EXT_V8. (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
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