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2023-08-17bpf: gas: consolidate handling of immediate overflowsJose E. Marchesi2-12/+33
This commit changes the BPF GAS port in order to handle immediate overflows the same way than the clang BPF assembler: - For an immediate field of N bits, any written number (positive or negative) whose two's complement encoding fit in N its is accepted. This means that -2 is the same than 0xffffffe. It is up to the instructions to decide how to interpret the encoded value. - Immediate fields in jump instructions are no longer relaxed. Relaxing to jump instructions with wider range is only performed when expressions are involved. - The manual is updated to document this, and testsuite adapted accordingly. Tested in x86_64-linux-gnu host, bpf-unknown-none target. gas/ChangeLog: 2023-08-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (check_immediate_overflow): New function. (encode_insn): Use check_immediate_overflow. (md_assemble): Do not relax instructions with constant disp16 fields. * doc/c-bpf.texi (BPF Instructions): Add note about how numerical literal values are interpreted for instruction immediate operands. * testsuite/gas/bpf/disp16-overflow.s: Adapt accordingly. * testsuite/gas/bpf/jump-relax-jump.s: Likewise. * testsuite/gas/bpf/jump-relax-jump.d: Likewise. * testsuite/gas/bpf/jump-relax-jump-be.d: Likewise. * testsuite/gas/bpf/jump-relax-ja.s: Likewise. * testsuite/gas/bpf/jump-relax-ja.d: Likewise. * testsuite/gas/bpf/jump-relax-ja-be.d: Likewise. * testsuite/gas/bpf/disp16-overflow-relax.l: Likewise. * testsuite/gas/bpf/imm32-overflow.s: Likewise. * testsuite/gas/bpf/disp32-overflow.s: Likewise. * testsuite/gas/bpf/disp16-overflow.l: Likewise. * testsuite/gas/bpf/disp32-overflow.l: Likewise. * testsuite/gas/bpf/imm32-overflow.l: Likewise. * testsuite/gas/bpf/offset16-overflow.l: Likewise.
2023-08-16kvx: New port.Paul Iannetta4-0/+37820
2023-08-16aarch64: Enable Cortex-A720 CPURichard Ball1-0/+5
This patch adds support for the Cortex-A720 CPU to binutils. bfd/ChangeLog: * cpu-aarch64.c: Add Cortex-A720. gas/ChangeLog: * NEWS: Update docs. * config/tc-aarch64.c: Add Cortex-A720. * doc/c-aarch64.texi: Update docs. * testsuite/gas/aarch64/cpu-cortex-a720.d: New test.
2023-08-15RISC-V: remove indirection from register tablesJan Beulich1-1/+1
The longest register name is 4 characters (plus a nul one), so using a 4- or 8-byte pointer to get at it is neither space nor time efficient. Embed the names right into the array. For PIE this also reduces the number of base relocations in the final image. To avoid old gcc, when generating 32-bit code, bogusly warning about bounds being exceeded in the code processing Cs/Cw, Ct/Cx, and CD, an adjustment to EXTRACT_BITS() is needed: This macro shouldn't supply a 64-bit value, and it also doesn't need to - all operand fields to date are far more narrow than 32 bits. This in turn allows dropping a number of casts elsewhere.
2023-08-15PPC: remove indirection from struct pd_regJan Beulich1-1/+1
The longest register name is 5 characters (plus a nul one), so using a 4- or 8-byte pointer to get at it is neither space nor time efficient. Embed the names right into the array. For PIE this also reduces the number of base relocations in the final image.
2023-08-14Re: PR30715, VAX: md_create_long_jumpAlan Modra1-3/+3
Tidy comment formatting.
2023-08-12PR30715, VAX: md_create_long_jumpKalvis Duckmanton1-7/+8
PR 30715 * config/tc-vax.c (md_create_long_jump): Use pc-relative addressing. * testsuite/gas/vax/broken_word.d, * testsuite/gas/vax/broken_word.s: New test. * testsuite/gas/vax/vax.exp: Run it.
2023-08-11gas: purge md_elf_section_word()Jan Beulich3-19/+0
It's not documented anyway, and having it makes no sense anymore with obj_elf_section_word() now being TC_SPARC-only. In any event the x86 backing function was dead code.
2023-08-11x86: pack CPU flags in opcode tableJan Beulich1-73/+116
The table constantly growing in two dimensions (number of table entries times number of ISA extension flags) doesn't scale very well. Use a more compact representation: Only identifiers which need to combine with other identifiers retain individual flag bits. All others are combined into an enum, with a new helper added to transform the table entries into the original i386_cpu_flags layout. This way the table in the final binary shrinks by almost a third (the generated source code shrinks by about half), and isn't likely to grow again in that dimension any time soon. While moving the 3DNow! fields, drop the stray inner 'a' from their names.
2023-08-10aarch64: Enable Cortex-A520 CPURichard Ball1-0/+4
This patch adds support for the Cortex-A520 CPU to gas. No regressions on aarch64-none-elf. gas/ChangeLog: * NEWS: Update docs. * config/tc-aarch64.c: Add Cortex-A520. * doc/c-aarch64.texi: Update docs.
2023-08-09Rename bfd_bread and bfd_bwriteAlan Modra2-2/+2
These were renamed from bfd_read and bfd_write back in 2001 when they lost an unnecessary parameter. Rename them back, and get rid of a few casts that are only needed without prototyped functions (K&R C).
2023-08-03arm: sanitizer stringop-overflowAlan Modra1-2/+8
In function 'memset', inlined from 'create_unwind_entry' at /home/alan/src/binutils-gdb/gas/config/tc-arm.c:27881:3: /usr/include/bits/string_fortified.h:59:10: error: '__builtin_memset' specified size between 2147483652 and 4294967295 exceeds maximum object size 2147483647 [-Werror=stringop-overflow=] 59 | return __builtin___memset_chk (__dest, __ch, __len, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 | __glibc_objsize0 (__dest)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~ * config/tc-arm.c (create_unwind_entry): Return after bad size, and bad opcode count.
2023-08-03xtensa: sprintf sanitizer null destination pointerAlan Modra1-7/+4
* config/tc-xtensa.c (xtensa_add_config_info): Use auto buffer rather than malloc. Use sprintf return value.
2023-08-02Revert "2.41 Release sources"Sam James14-1632/+1538
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton14-1538/+1632
2023-07-30bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flagsJose E. Marchesi3-0/+13
This patch adds support for EF_BPF_CPUVER bits in the ELF machine-dependent header flags. These bits encode the BPF CPU version for which the object file has been compiled for. The BPF assembler is updated so it annotates the object files it generates with these bits. The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the appropriate ISA version if the user didn't specify an explicit ISA version in the command line. Note that a value of zero in EF_BPF_CPUVER is interpreted by the disassembler as "use the later supported version" (the BPF CPU versions start with v1.) The readelf utility is updated to pretty print EF_BPF_CPUVER when it prints out the ELF header: $ readelf -h a.out ELF Header: ... Flags: 0x4, CPU Version: 4 Tested in bpf-unknown-none. include/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/bpf.h (EF_BPF_CPUVER): Define. * opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in EF_BPF_CPUVER. binutils/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * readelf.c (get_machine_flags): Recognize and pretty print BPF machine flags. opcodes/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-dis.c: Initialize asm_bpf_version to -1. (print_insn_bpf): Set BPF ISA version from the cpu version ELF header flags if no explicit version set in the command line. * disassemble.c (disassemble_init_for_target): Remove unused code. gas/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.h (elf_tc_final_processing): Define. * config/tc-bpf.c (bpf_elf_final_processing): New function.
2023-07-30bpf: gas: add field overflow checking to the BPF assemblerJose E. Marchesi1-8/+55
This patch makes the BPF assembler to throughfully check for overflow in immediates. This includes relaxed instructions. Tested in bpf-unknown-none. gas/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (signed_overflow): Copy function from tc-aarch64.c. (encode_insn): Check for overflow in constant immediates. (add_relaxed_insn): Pass relax argument to encode_insn. (add_fixed_insn): Likewise. * testsuite/gas/bpf/disp16-overflow.d: New file. * testsuite/gas/bpf/disp16-overflow.s: Likewise. * testsuite/gas/bpf/disp16-overflow.l: Likewise. * testsuite/gas/bpf/disp32-overflow.d: Likewise. * testsuite/gas/bpf/disp32-overflow.s: Likewise. * testsuite/gas/bpf/disp32-overflow.l: Likewise. * testsuite/gas/bpf/imm32-overflow.d: Likewise. * testsuite/gas/bpf/imm32-overflow.s: Likewise. * testsuite/gas/bpf/imm32-overflow.l: Likewise. * testsuite/gas/bpf/offset16-overflow.d: Likewise. * testsuite/gas/bpf/offset16-overflow.s: Likewise. * testsuite/gas/bpf/offset16-overflow.l: Likewise. * testsuite/gas/bpf/disp16-overflow-relax.d: Likewise. * testsuite/gas/bpf/disp16-overflow-relax.l: Likewise. * testsuite/gas/bpf/disp16-overflow-relax.s: Likewise. * testsuite/gas/bpf/jump-relax-jump-be.d: New file. * testsuite/gas/bpf/bpf.exp: Run new tests.
2023-07-28bpf: remove spurious comment from tc-bpf.cJose E. Marchesi1-2/+0
2023-07-28bpf: gas: support relaxation of V4 jump instructionsJose E. Marchesi1-308/+712
The BPF jump-always instruction (JA), like all other jump instructions in the ISA, get a signed 16-bit displacement target argument denoted in number of 64-bit words minus one. This can sometimes be overflown. The BPF V4 ISA thus introduced support for a jump-always instruction (JAL) that gets a signed 32-bit displacement instead. This patch makes the BPF assembler to perform the following relaxations when the disp16 field gets overflown, unless the option -mno-relax is specified: JA disp16 -> JAL disp32 Jxx disp16 -> Jxx +1; JA +1; JAL disp32 Documentation and tests added. Tested in bpf-unknown-none. gas/ChangeLog: 2023-07-28 Jose E. Marchesi <jose.marchesi@oracle.com> PR gas/30690 * config/tc-bpf.c (struct bpf_insn): Add fields is_relaxable and relaxed_exp. (enum options): Add OPTION_NO_RELAX. (md_longopts): Likewise for -mno-relax. (do_relax): New global. (md_parse_option): Handle OPTION_NO_RELAX. (RELAX_BRANCH_ENCODE): Define. (RELAX_BRANCH_P): Likewise. (RELAX_BRANCH_LENGTH): Likewise. (RELAX_BRANCH_CONST): Likewise. (RELAX_BRANCH_UNCOND): Likewise. (relaxed_branch_length): New function. (md_estimate_size_before_relax): Likewise. (read_insn_word): Likewise. (encode_int16): Likewise. (encode_int32): Likewise. (write_insn_bytes): Likewise. (md_convert_frag): Likewise. (encode_insn): Likewise. (install_insn_fixups): Likewise. (add_fixed_insn): Likewise. (add_relaxed_insn): Likewise. (md_assemble): Move instruction encoding logic to the above new functions. * testsuite/gas/bpf/jump-relax-ja.d: New test. * testsuite/gas/bpf/jump-relax-ja-be.d: Likewise. * testsuite/gas/bpf/jump-relax-ja.s: And corresponding source. * testsuite/gas/bpf/jump-relax-jump.d: New test. * testsuite/gas/bpf/jump-relax-jump-be.d: Likewise. * testsuite/gas/bpf/jump-relax-jump.s: And corresponding source. * testsuite/gas/bpf/bpf.exp: Run new tests. * doc/c-bpf.texi (BPF Options): Document -mno-relax.
2023-07-27sh: uninitialised sh_operand_info.type in get_specificAlan Modra1-21/+6
Seen when running gas/testsuite/gas/sh/err-at.s * config/tc-sh.c (get_operands): Always init operand type. * testsuite/gas/sh/err-at.s: Expect unnecessary extra errors.
2023-07-27Support Intel PBNDKBHu, Lin11-0/+1
gas/ChangeLog: * NEWS: Support Intel PBNDKB. * config/tc-i386.c: Add pbndkb. * doc/c-i386.texi: Document .pbndkb. * testsuite/gas/i386/i386.exp: Add PBNDKB tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/pbndkb-inval.l: New test. * testsuite/gas/i386/pbndkb-inval.s: Ditto. * testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New. (X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0. (rm_table): New entry for pbndkb. * i386-gen.c (cpu_flag): Add PBNDKB. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuPBNDKB): New. (i386_cpu_flags): Add cpupbndkb. * i386-opc.tbl: Add PBNDKB instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SM4Haochen Jiang1-0/+1
gas/ChangeLog: * NEWS: Support Intel SM4. * config/tc-i386.c: Add sm4. * doc/c-i386.texi: Document .sm4. * testsuite/gas/i386/i386.exp: Run SM4 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sm4-intel.d: Add SM4 tests. * testsuite/gas/i386/sm4.d: Ditto. * testsuite/gas/i386/sm4.s: Ditto. * testsuite/gas/i386/x86-64-sm4-intel.d: Ditto. * testsuite/gas/i386/x86-64-sm4.d: Ditto. * testsuite/gas/i386/x86-64-sm4.s: Ditto. opcodes/ChangeLog: * i386-dis.c (prefix_table): Add SM4 instructions. * i386-gen.c (isa_dependencies): Add SM4. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSM4): New. (i386_cpu_flags): Add cpusm4. * i386-opc.tbl: Add SM4 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SM3Haochen Jiang1-0/+1
gas/ChangeLog: * NEWS: Support Intel SM3. * config/tc-i386.c: Add sm3. * doc/c-i386.texi: Document .sm3. * testsuite/gas/i386/i386.exp: Run sm3 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sm3-intel.d: New test. * testsuite/gas/i386/sm3.d: Ditto. * testsuite/gas/i386/sm3.s: Ditto. * testsuite/gas/i386/x86-64-sm3-intel.d: Ditto. * testsuite/gas/i386/x86-64-sm3.d: Ditto. * testsuite/gas/i386/x86-64-sm3.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F38DA_W_0): New. (VEX_LEN_0F38DA_W_0_P_0): Ditto. (VEX_LEN_0F38DA_W_0_P_2): Ditto. (VEX_LEN_0F3ADE_W_0): Ditto. (VEX_W_0F38DA): Ditto. (VEX_W_0F3ADE): Ditto. (prefix_table): Add PREFIX_VEX_0F38DA_W_0. (vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0, VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0. (vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE. * i386-gen.c (isa_dependencies): Add SM3. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSM3): New. (i386_cpu_flags): Add cpusm3. * i386-opc.tbl: Add SM3 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SHA512Haochen Jiang1-0/+1
gas/ChangeLog: * NEWS: Support Intel SHA512. * config/tc-i386.c: Add sha512. * doc/c-i386.texi: Document .sha512. * testsuite/gas/i386/disassem.d: Add SHA512 tests. * testsuite/gas/i386/disassem.s: Ditto. * testsuite/gas/i386/i386.exp: Run SHA512 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sha512-intel.d: New test. * testsuite/gas/i386/sha512-inval.l: Ditto. * testsuite/gas/i386/sha512-inval.s: Ditto. * testsuite/gas/i386/sha512.d: Ditto. * testsuite/gas/i386/sha512.s: Ditto. * testsuite/gas/i386/x86-64-sha512-intel.d: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.l: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.s: Ditto. * testsuite/gas/i386/x86-64-sha512.d: Ditto. * testsuite/gas/i386/x86-64-sha512.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Rxmmq): New. (Rymm): Ditto. (PREFIX_VEX_0F38CB): Ditto. (PREFIX_VEX_0F38CC): Ditto. (PREFIX_VEX_0F38CD): Ditto. (VEX_LEN_0F38CB_P_3_W_0): Ditto. (VEX_LEN_0F38CC_P_3_W_0): Ditto. (VEX_LEN_0F38CD_P_3_W_0): Ditto. (VEX_W_0F38CB_P_3): Ditto. (VEX_W_0F38CC_P_3): Ditto. (VEX_W_0F38CD_P_3): Ditto. (prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC, PREFIX_VEX_0F38CD. (vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0, VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0. (vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3. * i386-gen.c (isa_dependencies): Add SHA512. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSHA512): New. (i386_cpu_flags): Add cpusha512. * i386-opc.tbl: Add SHA512 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel AVX-VNNI-INT16konglin11-0/+1
gas/ChangeLog: * NEWS: Support Intel AVX-VNNI-INT16. * config/tc-i386.c: Add avx_vnni_int16. * doc/c-i386.texi: Document avx_vnni_int16. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/avx-vnni-int16.d: New test. * testsuite/gas/i386/avx-vnni-int16.s: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F38D2_W_0): New. (PREFIX_VEX_0F38D3_W_0): Ditto. (VEX_W_0F38D2_P_0): Ditto. (VEX_W_0F38D2_P_1): Ditto. (VEX_W_0F38D2_P_2): Ditto. (VEX_W_0F38D3_P_0): Ditto. (VEX_W_0F38D3_P_1): Ditto. (VEX_W_0F38D3_P_2): Ditto. (prefix_table): Add PREFIX_VEX_0F38D2_W_0 and PREFIX_VEX_0F38D3_W_0. (vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3. (vex_w_table): Ditto. * i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16. (cpu_flag): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: (CpuAVX_VNNI_INT16): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions. * i386-tbl.h: Regenerated.
2023-07-26bpf: accept # as an inline comment charDavid Faust1-1/+1
This little patch makes the BPF assembler accept '#' as an inline comment character, which clang -S seems to use. gas/ * config/tc-bpf.c (comment_chars): Add '#'. * doc/c-bpf.texi (BPF Special Characters): Add note that '#' may be used for inline comments.
2023-07-26Don't warn on .attach_to_group to same groupAlan Modra1-2/+3
* config/obj-elf.c (obj_elf_attach_to_group): Don't warn if group name matches current group for section.
2023-07-26bpf: format not a string literalAlan Modra1-1/+1
* config/tc-bpf.c (md_assemble): Correct as_bad call.
2023-07-25RISC-V: Enable RVC on ".option arch, +zca" etc.Tsukasa OI1-1/+2
Since the 'Zca' extension is the new base of the compressed instructions, this commit enables RVC *also* when the 'Zca' extension is enabled via ".option arch" directive. gas/ChangeLog: * config/tc-riscv.c (s_riscv_option): Enable RVC also when the 'Zca' extension is enabled after an ".option arch" directive.
2023-07-24bpf: add support for jal/gotol jump instruction with 32-bit targetJose E. Marchesi1-22/+34
This patch adds support for the V4 BPF instruction jal/gotol, which is like ja/goto but it supports a signed 32-bit PC-relative (in number of 64-bit words minus one) target operand instead of the 16-bit signed operand of the other instruction. This greatly increases the jump range in BPF programs. Tested in bpf-unkown-none. bfd/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32. * elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc. * libbfd.h (bfd_reloc_code_real_names): Regenerate. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (struct bpf_insn): New field `id'. (md_assemble): Save the ids of successfully parsed instructions and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate. (md_apply_fix): Adapt to the new BFD reloc. * testsuite/gas/bpf/jump.s: Test JAL. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/jump-pseudoc.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump-be-pseudoc.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document new instruction jal/gotol. Document new operand type disp32. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL. (enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI. opcodes/ChangeLog: 2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entry for jal.
2023-07-21DesCGENization of the BPF binutils portJose E. Marchesi2-1617/+906
CGEN is cool, but the BPF architecture is simply too bizarre for it. The weird way of BPF to handle endianness in instruction encoding, the weird C-like alternative assembly syntax, the weird abuse of multi-byte (or infra-byte) instruction fields as opcodes, the unusual presence of opcodes beyond the first 32-bits of some instructions, are all examples of what makes it a PITA to continue using CGEN for this port. The bpf.cpu file is becoming so complex and so nested with p-macros that it is very difficult to read, and quite challenging to update. Also, every time we are forced to change something in CGEN to accommodate BPF requirements (which is often) we have to do extensive testing to make sure we do not break any other target using CGEN. This is getting un-maintenable. So I have decided to bite the bullet and revamp/rewrite the port so it no longer uses CGEN. Overall, this involved: * To remove the cpu/bpf.{cpu,opc} descriptions. * To remove the CGEN generated files. * To replace the CGEN generated opcodes table with a new hand-written opcodes table for BPF. * To replace the CGEN generated disassembler wih a new disassembler that uses the new opcodes. * To replace the CGEN generated assembler with a new assembler that uses the new opcodes. * To replace the CGEN generated simulator with a new simulator that uses the new opcodes. [This is pushed in GDB in another patch.] * To adapt the build systems to the new situation. Additionally, this patch introduces some extensions and improvements: * A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These relocations are used for section-relative 16-bit offsets used in load/store instructions. * The disassembler now has support for the "pseudo-c" assembly syntax of BPF. What dialect to use when disassembling is controlled by a command line option. * The disassembler now has support for dumping instruction immediates in either octal, hexadecimal or decimal. The used output base is controlled by a new command-line option. * The GAS BPF test suite has been re-structured and expanded in order to test the disassembler pseudoc syntax support. Minor bugs have been also fixed there. The assembler generic tests that were disabled for bpf-*-* targets due to the previous implementation of pseudoc syntax are now re-enabled. Additional tests have been added to test the new features of the assembler. .dump files are no longer used. * The linker BPF test suite has been adapted to the command line options used by the new disassembler. The result is very satisfactory. This patchs adds 3448 lines of code and removes 10542 lines of code. Tested in: * Target bpf-unknown-none with 64-bit little-endian host and 32-bit little-endian host. * Target x86-64-linux-gnu with --enable-targets=all Note that I have not tested in a big-endian host yet. I will do so once this lands upstream so I can use the GCC compiler farm. I have not included ChangeLog entries in this patch: these would be massive and not very useful, considering this is pretty much a rewrite of the port. I beg the indulgence of the global maintainers.
2023-07-19gas 32-bit host compile warningsAlan Modra5-19/+26
* config/tc-d10v.c (find_opcode): Correct format specifier vs. arg mismatch. * config/tc-m68hc11.c (fixup8, fixup16, fixup24, fixup8_xg): Likewise. * config/tc-vax.c (md_assemble): Likewise. * config/tc-xtensa.c (dump_litpools): Likewise. * config/tc-z80.c (emit_data_val, emit_byte): Likewise.
2023-07-18RISC-V: Supports Zcb extension.Jiawei1-0/+53
This patch support Zcb extension, contains new compressed instructions, some instructions depend on other existed extension, like 'zba', 'zbb' and 'zmmul'. Zcb also imply Zca extension to enable the compressing features. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcb.d: New test. * testsuite/gas/riscv/zcb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_LBU): New opcode. (MASK_C_LBU): New mask. (MATCH_C_LHU): New opcode. (MASK_C_LHU): New mask. (MATCH_C_LH): New opcode. (MASK_C_LH): New mask. (MATCH_C_SB): New opcode. (MASK_C_SB): New mask. (MATCH_C_SH): New opcode. (MASK_C_SH): New mask. (MATCH_C_ZEXT_B): New opcode. (MASK_C_ZEXT_B): New mask. (MATCH_C_SEXT_B): New opcode. (MASK_C_SEXT_B): New mask. (MATCH_C_ZEXT_H): New opcode. (MASK_C_ZEXT_H): New mask. (MATCH_C_SEXT_H): New opcode. (MASK_C_SEXT_H): New mask. (MATCH_C_ZEXT_W): New opcode. (MASK_C_ZEXT_W): New mask. (MATCH_C_NOT): New opcode. (MASK_C_NOT): New mask. (MATCH_C_MUL): New opcode. (MASK_C_MUL): New mask. (DECLARE_INSN): New opcode. * opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func. (EXTRACT_ZCB_HALFWORD_UIMM): Ditto. (ENCODE_ZCB_BYTE_UIMM): Ditto. (ENCODE_ZCB_HALFWORD_UIMM): Ditto. (VALID_ZCB_BYTE_UIMM): Ditto. (VALID_ZCB_HALFWORD_UIMM): Ditto. (enum riscv_insn_class): New extension class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operators. * riscv-opc.c: New instructions.
2023-07-18RISC-V: Support Zca/f/d extensions.Jiawei1-1/+2
This patch add Zca/f/d extensions support, since all ZC* extensions will imply Zca extension, just enabled compress feature when Zca extension is available. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extensions. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (riscv_set_arch): Extend compress check. * testsuite/gas/riscv/zca.d: New test. * testsuite/gas/riscv/zca.s: New test. * testsuite/gas/riscv/zcd.d: New test. * testsuite/gas/riscv/zcd.s: New test. * testsuite/gas/riscv/zcf.d: New test. * testsuite/gas/riscv/zcf.s: New test.
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich1-0/+27
The alternative is 1 byte shorter when the source is %xmm0-7, as a 2-byte VEX prefix can then be used.
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich1-0/+40
These are better expressed by the zeroing idiom {,V}PXOR. In some cases this also results in a shorter encoding.
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich1-0/+17
The {,V}PCMPEQD alternative is 1 byte shorter in many cases.
2023-07-04arc: Update default target CPU to match GCC defaultsClaudiu Zissulescu1-1/+1
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-07-03IBM Z: Fix pcrel relocs for symA-symB expressionsAndreas Krebbel1-4/+10
The code in md_apply_fix which tries to deduce from the operand type which reloc to apply currently does the wrong thing for absolute relocs which have been re-written by fixup_segment as pc-relative to implement a subtraction of a local and an external symbol. In all these cases we wrongly emit an absolute reloc because we ignore the fx_pcrel flag in md_apply_fix. However, only for the last one we actually support a pc relative relocation of the proper size and can implement it accordingly. For the other 3 we have to issue an error. foo: cli 0(%r2),undef-foo la %r2,undef-foo(%r2) lay %r2,undef-foo(%r2) lhi %r2,undef-foo
2023-07-03LoongArch: gas: Fix shared buildsWANG Xuerui1-1/+0
Formerly an include of libbfd.h was added in commit 56576f4a722 ("LoongArch: gas: Add support for linker relaxation."), in order to allow calling _bfd_read_unsigned_leb128 from gas, but doing so broke shared builds. Commit d2fddb6d783 fixed this reference but did not remove the now unnecessary inclusion of libbfd.h. The gas_assert macro expands into a conditional call to abort(), but "abort" is re-defined to _bfd_abort in libbfd.h, so the extra include breaks any gas_assert usage, and should be removed. gas/ChangeLog: * config/tc-loongarch.c: Don't include libbfd.h. Fixes: d2fddb6d783 ("LoongArch: Fix ld "undefined reference" error with --enable-shared") Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner1-0/+13
Zvbb is part of the vector crypto extensions. This extension adds the following instructions: - vandn.[vv,vx] - vbrev.v - vbrev8.v - vrev8.v - vclz.v - vctz.v - vcpop.v - vrol.[vv,vx] - vror.[vv,vx,vi] - vwsll.[vv,vx,vi] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbb. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format string directive. (riscv_ip): Likewise. * testsuite/gas/riscv/zvbb.d: New test. * testsuite/gas/riscv/zvbb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VANDN_VV): New. (MASK_VANDN_VV): New. (MATCH_VANDN_VX): New. (MASK_VANDN_VX): New. (MATCH_VBREV8_V): New. (MASK_VBREV8_V): New. (MATCH_VBREV_V): New. (MASK_VBREV_V): New. (MATCH_VCLZ_V): New. (MASK_VCLZ_V): New. (MATCH_VCPOP_V): New. (MASK_VCPOP_V): New. (MATCH_VCTZ_V): New. (MASK_VCTZ_V): New. (MATCH_VREV8_V): New. (MASK_VREV8_V): New. (MATCH_VROL_VV): New. (MASK_VROL_VV): New. (MATCH_VROL_VX): New. (MASK_VROL_VX): New. (MATCH_VROR_VI): New. (MASK_VROR_VI): New. (MATCH_VROR_VV): New. (MASK_VROR_VV): New. (MATCH_VROR_VX): New. (MASK_VROR_VX): New. (MATCH_VWSLL_VI): New. (MASK_VWSLL_VI): New. (MATCH_VWSLL_VV): New. (MASK_VWSLL_VV): New. (MATCH_VWSLL_VX): New. (MASK_VWSLL_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New. (ENCODE_RVV_VI_UIMM6): New. (enum riscv_insn_class): Add instruction class for Zvbb. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add 'l' as new format string directive. * riscv-opc.c: Add Zvbb instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner1-0/+52
This patch adds support for the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of FP registers in case XLEN < FLEN * fleq/fltq (quiet comparison instructions) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) This patch is based on an earlier version from Tsukasa OI: https://sourceware.org/pipermail/binutils/2022-September/122939.html Most significant change to that commit is the switch from the rs1-field value to the actual floating-point value in the last operand of the fli* instructions. Everything that strtof() can parse is accepted and the '%a' printf specifier is used to output hex floating-point literals in the disassembly. The Zfa specification is frozen (and has passed public review). It is available as a chapter in "The RISC-V Instruction Set Manual: Volume 1": https://github.com/riscv/riscv-isa-manual/releases bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for 'Zfa' extension. (riscv_multi_subset_supports_ext): Likewise. (riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency. gas/ChangeLog: * config/tc-riscv.c (flt_lookup): New helper to lookup a float value in an array. (validate_riscv_insn): Add 'Wfv' as new format string directive. (riscv_ip): Likewise. * doc/c-riscv.texi: Add floating-point chapter and describe limiations of the Zfa FP literal parsing. * testsuite/gas/riscv/zfa-32.d: New test. * testsuite/gas/riscv/zfa-32.s: New test. * testsuite/gas/riscv/zfa-64.d: New test. * testsuite/gas/riscv/zfa-64.s: New test. * testsuite/gas/riscv/zfa-fail.d: New test. * testsuite/gas/riscv/zfa-fail.l: New test. * testsuite/gas/riscv/zfa-fail.s: New test. * testsuite/gas/riscv/zfa.d: New test. * testsuite/gas/riscv/zfa.s: New test. * testsuite/gas/riscv/zfa.s: New test. * opcode/riscv-opc.h (MATCH_FLI_H): New. (MASK_FLI_H): New. (MATCH_FMINM_H): New. (MASK_FMINM_H): New. (MATCH_FMAXM_H): New. (MASK_FMAXM_H): New. (MATCH_FROUND_H): New. (MASK_FROUND_H): New. (MATCH_FROUNDNX_H): New. (MASK_FROUNDNX_H): New. (MATCH_FLTQ_H): New. (MASK_FLTQ_H): New. (MATCH_FLEQ_H): New. (MASK_FLEQ_H): New. (MATCH_FLI_S): New. (MASK_FLI_S): New. (MATCH_FMINM_S): New. (MASK_FMINM_S): New. (MATCH_FMAXM_S): New. (MASK_FMAXM_S): New. (MATCH_FROUND_S): New. (MASK_FROUND_S): New. (MATCH_FROUNDNX_S): New. (MASK_FROUNDNX_S): New. (MATCH_FLTQ_S): New. (MASK_FLTQ_S): New. (MATCH_FLEQ_S): New. (MASK_FLEQ_S): New. (MATCH_FLI_D): New. (MASK_FLI_D): New. (MATCH_FMINM_D): New. (MASK_FMINM_D): New. (MATCH_FMAXM_D): New. (MASK_FMAXM_D): New. (MATCH_FROUND_D): New. (MASK_FROUND_D): New. (MATCH_FROUNDNX_D): New. (MASK_FROUNDNX_D): New. (MATCH_FLTQ_D): New. (MASK_FLTQ_D): New. (MATCH_FLEQ_D): New. (MASK_FLEQ_D): New. (MATCH_FLI_Q): New. (MASK_FLI_Q): New. (MATCH_FMINM_Q): New. (MASK_FMINM_Q): New. (MATCH_FMAXM_Q): New. (MASK_FMAXM_Q): New. (MATCH_FROUND_Q): New. (MASK_FROUND_Q): New. (MATCH_FROUNDNX_Q): New. (MASK_FROUNDNX_Q): New. (MATCH_FLTQ_Q): New. (MASK_FLTQ_Q): New. (MATCH_FLEQ_Q): New. (MASK_FLEQ_Q): New. (MATCH_FCVTMOD_W_D): New. (MASK_FCVTMOD_W_D): New. (MATCH_FMVH_X_D): New. (MASK_FMVH_X_D): New. (MATCH_FMVH_X_Q): New. (MASK_FMVH_X_Q): New. (MATCH_FMVP_D_X): New. (MASK_FMVP_D_X): New. (MATCH_FMVP_Q_X): New. (MASK_FMVP_Q_X): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction classes for the Zfa extension. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add support for new format string directive 'Wfv'. * riscv-opc.c: Add Zfa instructions. Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-30LoongArch: gas: Add LVZ and LBT instructions supportmengqinggang1-0/+4
gas/ChangeLog: * config/tc-loongarch.c (md_parse_option): Add LARCH_opts.ase_lvz and LARCH_opts.ase_lbt. * testsuite/gas/loongarch/uleb128.d: Regenerated. * testsuite/gas/loongarch/lvz-lbt.d: New test. * testsuite/gas/loongarch/lvz-lbt.s: New test. include/ChangeLog: * opcode/loongarch.h (ase_lvz): New. (ase_lbt): New. opcodes/ChangeLog: * loongarch-dis.c (set_default_loongarch_dis_options): Add LARCH_opts.ase_lvz and LARCH_opts.ase_lbt. * loongarch-opc.c (struct loongarch_ase): Add LVZ and LBT instructions.
2023-06-30LoongArch: Deprecate $v[01], $fv[01] and $x names per specWANG Xuerui1-5/+37
As outlined in the LoongArch ELF psABI spec [1], it is actually already 2 versions after the initial LoongArch support, and the $v[01] and $fv[01] names should really get sunset by now. In addition, the "$x" name for $r21 was never included in any released version of the ABI spec, and such usages are all fixed to say just $r21 for every project I could think of that accepted a LoongArch port. Plus, the upcoming LSX/LASX support makes use of registers named "$vrNN" and "$xrNN", so having "$vN" and "$x" alongside would almost certainly create confusion for developers. Issue warnings for such usages per the deprecation procedure detailed in the spec, so we can finally remove support in the next release cycle after this. [1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html gas/ChangeLog: * config/tc-loongarch.c: Init canonical register ABI name mappings and deprecated register names. (loongarch_args_parser_can_match_arg_helper): Warn in case of deprecated register name usage. * testsuite/gas/loongarch/deprecated_reg_aliases.d: New test. * testsuite/gas/loongarch/deprecated_reg_aliases.l: Likewise. * testsuite/gas/loongarch/deprecated_reg_aliases.s: Likewise. include/ChangeLog: * opcode/loongarch.h: Rename global variables. opcodes/ChangeLog: * loongarch-opc.c: Rename the alternate/deprecated register name mappings, and move $x to the deprecated name map. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30LoongArch: support disassembling certain pseudo-instructionsWANG Xuerui1-1/+2
Add a flag in the pinfo field for being able to mark certain specialized matchers as disassembler-only, so some degree of isolation between assembler-side and disassembler-side can be achieved. This isolation is necessary, firstly because some pseudo-instructions cannot be fully described in the opcode table, like `li.[wd]`, so the corresponding opcode entry cannot have meaningful match/mask values. Secondly, some of these pseudo-instructions can be realized in more than one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie disassembly of such aliases with the corresponding GAS support, only one canonical form among the above would be recognized as `li.w`, and it would mildly impact the readability of disassembly output. People wanting the exact disassembly can always set `-M no-aliases` to get the original behavior back. In addition, in certain cases, information is irreversibly lost after assembling, so perfect round-trip would not be possible in such cases. For example, `li.w` and `li.d` of immediates within int32_t range produce the same code; in this patch, `addi.d rd, $zero, imm` is treated as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`, due to the expressible value range well within 32 bits. gas/ChangeLog: * config/tc-loongarch.c (get_loongarch_opcode): Ignore disassembler-only aliases. * testsuite/gas/loongarch/64_pcrel.d: Update test case. * testsuite/gas/loongarch/imm_ins.d: Likewise. * testsuite/gas/loongarch/imm_ins_32.d: Likewise. * testsuite/gas/loongarch/jmp_op.d: Likewise. * testsuite/gas/loongarch/li.d: Likewise. * testsuite/gas/loongarch/macro_op.d: Likewise. * testsuite/gas/loongarch/macro_op_32.d: Likewise. * testsuite/gas/loongarch/macro_op_large_abs.d: Likewise. * testsuite/gas/loongarch/macro_op_large_pc.d: Likewise. * testsuite/gas/loongarch/nop.d: Likewise. * testsuite/gas/loongarch/relax_align.d: Likewise. * testsuite/gas/loongarch/reloc.d: Likewise. include/ChangeLog: * opcode/loongarch.h (INSN_DIS_ALIAS): Add. ld/ChangeLog: * testsuite/ld-loongarch-elf/jmp_op.d: Update test case. * testsuite/ld-loongarch-elf/macro_op.d: Likewise. * testsuite/ld-loongarch-elf/macro_op_32.d: Likewise. * testsuite/ld-loongarch-elf/relax-align.dd: Likewise. opcodes/ChangeLog: * loongarch-dis.c: Move register name map declarations to top. (get_loongarch_opcode_by_binfmt): Consider aliases when disassembling without the no-aliases option. (parse_loongarch_dis_option): Support the no-aliases option. * loongarch-opc.c: Collect pseudo instructions into a new dedicated table. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-28LoongArch: gas: Add lsx and lasx instructions supportmengqinggang1-0/+4
gas/ChangeLog: * config/tc-loongarch.c (md_parse_option): Add lsx and lasx option. (loongarch_after_parse_args): Add lsx and lasx option. opcodes/ChangeLog: * loongarch-opc.c (struct loongarch_ase): Add lsx and lasx instructions.
2023-06-28LoongArch: Add R_LARCH_64_PCREL relocation supportmengqinggang1-3/+2
Gas defaults to emit R_LARCH_ADD64/R_LARCH_SUB64 unless explcitly declared to emit R_LARCH_64_PCREL. The LoongArch ABI at here: https://github.com/loongson/la-abi-specs/blob/release/la-abi.adoc bfd/ChangeLog: * bfd-in2.h (not): Add R_LARCH_64_PCREL * elfnn-loongarch.c (perform_relocation): Likewise. * elfxx-loongarch.c: Likewise. * libbfd.h: Likewise. * reloc.c: Likewise. gas/ChangeLog: * config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper): (md_apply_fix): Add R_LARCH_64_PCREL. * testsuite/gas/loongarch/64_pcrel.d: New test. * testsuite/gas/loongarch/64_pcrel.s: New test. include/ChangeLog: * elf/loongarch.h (RELOC_NUMBER): Add R_LARCH_64_PCREL. ld/ChangeLog: * testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test. * testsuite/ld-loongarch-elf/64_pcrel.d: New test. * testsuite/ld-loongarch-elf/64_pcrel.s: New test.
2023-06-25LoongArch: Support referring to FCSRs as $fcsrXFeiyang Chen1-1/+28
Previously, FCSRs were referred to as $rX, which seemed strange. We refer to FCSRs as $fcsrX, which ensures compatibility with LLVM IAS as well. gas/ChangeLog: * config/tc-loongarch.c: (loongarch_fc_normal_name): New definition. (loongarch_fc_numeric_name): New definition. (loongarch_single_float_opcodes): Modify `movgr2fcsr` and `movfcsr2gr`. testsuite/gas/loongarch/float_op.d: Likewise. testsuite/gas/loongarch/float_op.s: Likewise. include/ChangeLog: * opcode/loongarch.h: (loongarch_fc_normal_name): New extern. (loongarch_fc_numeric_name): New extern. opcodes/ChangeLog: * opcodes/loongarch-dis.c (loongarch_after_parse_args): Support referring to FCSRs as $fcsrX. * opcodes/loongarch-opc.c (loongarch_args_parser_can_match_arg_helper): Likewise. Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
2023-06-22Revert "x86: Don't check if AVX512 template requires AVX512VL"H.J. Lu1-2/+3
This reverts commit c7face14225296a2f5d3ebeb8ace88c166d80c3e.
2023-06-20x86: Don't check if AVX512 template requires AVX512VLH.J. Lu1-3/+2
If the ZMM operand in an AVX12 template also allows XMM or ZMM, this template must require AVX512VL. Drop the AVX512VL requirement check on such AVX512 templates. * config/tc-i386.c (check_VecOperands): Don't check if AVX512 template requires AVX512VL.
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