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2023-10-15opcodes: microblaze: Add new bit-field instructionsNeal Frager1-1/+82
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref With version 6 of the patch, no new relocation types are added as this was unnecessary for adding the bsefi and bsifi instructions. FIXED: Segfault caused by incorrect termination of microblaze_opcodes. Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-10LoongArch/GAS: Add support for branch relaxationmengqinggang1-41/+195
For the instructions of R_LARCH_B16/B21, if the immediate overflow, add a B instruction and R_LARCH_B26 relocation. For example: .L1 ... blt $t0, $t1, .L1 R_LARCH_B16 change to: .L1 ... bge $t0, $t1, .L2 b .L1 R_LARCH_B26 .L2
2023-10-08as: add option for generate R_LARCH_32/64_PCREL.cailulu2-6/+36
Some older kernels cannot handle the newly generated R_LARCH_32/64_PCREL, so the assembler generates R_LARCH_ADD32/64+R_LARCH_SUB32/64 by default, and use the assembler option mthin-add-sub to generate R_LARCH_32/64_PCREL as much as possible. The Option of mthin-add-sub does not affect the generation of R_LARCH_32_PCREL relocation in .eh_frame.
2023-10-07Revert "opcodes: microblaze: Add new bit-field instructions"Michael J. Eager1-76/+1
This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9. Maciej W. Rozycki <macro@orcam.me.uk>: Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) microblaze-elf +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) ...
2023-10-06opcodes: microblaze: Add new bit-field instructionsNeal Frager1-1/+76
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-05aarch64: Enable Cortex-X4 CPUSaurabh Jha1-0/+2
2023-10-02Fix memory leak in RiscV assembler.Nick Clifton1-0/+1
PR 30861 * config/tc-riscv.c (riscv_insert_uleb128_fixes): Release duplicated memory.
2023-09-29tc-microblaze.c - int compare for X_add_number.Neal Frager1-1/+1
The range check should be checking for the range ffffffff80000000..7fffffff, not ffffffff70000000. This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-09-28Added support in gas for mlittle-endian and mbig-endian flags as options.Michael J. Eager1-0/+5
Updated show usage for MicroBlaze specific assembler options to include new entries. This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> --- V1->V2: - removed new options which were unnecessary - added documentation for MicroBlaze specific options Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-09-27x86: prefer VEX encodings over EVEX ones when possibleJan Beulich1-0/+31
AVX-* features / insns paralleling earlier introduced AVX512* ones can be encoded more compactly when the respective feature was explicitly enabled by the user.
2023-09-27x86: drop cpu_arch_tune_flagsJan Beulich1-22/+4
Apparently from its introduction the variable was only ever written (the only read is merely to determine whether to write it with another value). (Since, due to the need to re-indent, the adjacent lines setting cpu_arch_tune need touching anyway, switch to using PREOCESSOR_* constants where applicable, to make more obvious what the resulting state is going to be.)
2023-09-27x86: correct cpu_arch_isa_flags maintenanceJan Beulich1-47/+35
These may not be set from a value derived from cpu_arch_flags: That starts with (almost) all functionality enabled, while cpu_arch_isa_flags is supposed to track features that were explicitly enabled (and perhaps later disabled) by the user. To avoid needing to do any such adjustment in two places (each), introduce helper functions used by both command line handling and directive processing.
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich1-0/+4
Following the folding of some generic AVX/AVX2 templates with their AVX512F counterpart ones, do this for FMA ones as well, requiring one further adjustment to cpu_flags_match().
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich1-4/+12
Following the folding of some generic AVX/AVX2 templates with their AVX512F counterpart ones, do this for VAES and VPCLMULQDQ ones as well.
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich2-5/+102
In anticipation of APX introduce logic to reduce the number of templates we have now, allowing to limit some the number of ones we then need to gain. The fundamental requirements are that - attributes be compatible, which specifically means VexW needs to be the same in the templates (which often isn't the case, for VEX encodings having far more WIG tha, EVEX ones), - the EVEX form being AVX512F (with or without AVX512VL), not any of its extensions (the same will then be required for APX - it'll need to be APX_F). Note that in check_register() there's now a redundant zmm check. Since this logic will need revisiting for APX anyway, I'd like to keep it that way for now. (Similarly a couple of if()-s which could be folded are kept separate, to reduce code churn when adding APX support.)
2023-09-27x86: tighten .insn SAE and broadcast checkingJan Beulich1-2/+3
SAE / embedded rounding are invalid when there's the memory operand, as the bit encoding this specifies broadcast in that case. Broadcast needs to be specified on the memory operand.
2023-09-27x86-64: REX.W overrides DATA_PREFIXJan Beulich1-2/+5
REX.W needs to be respected when immediate size and relocation type are determined.
2023-09-27x86-64: fix suffix-less PUSH of symbol addressJan Beulich1-1/+6
PR gas/30856 In 5cc007751cdb ("x86: further adjust extend-to-32bit-address conditions") I neglected the case of PUSH, which is the only insn allowing (proper) symbol addresses to be used as immediates (not displacements, like CALL/JMP) in the absence of any register operands. Since it defaults to 64-bit operand size, guessing an L suffix is wrong there.
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford1-300/+162
The AArch64 feature-flag code is currently limited to a maximum of 64 features. This patch reworks it so that the limit can be increased more easily. The basic idea is: (1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum counting bit positions. (2) Make the feature-list macros take an array index argument (currently always 0). The macros then return the aarch64_feature_set contents for that array index. An N-element array would then be initialised as: { MACRO (0), ..., MACRO (N - 1) } (3) Provide convenience macros for initialising an aarch64_feature_set for: - a single feature - a list of individual features - an architecture version - an architecture version + a list of additional features (2) and (3) use the preprocessor to generate static initialisers. The main restriction was that uses of the same preprocessor macro cannot be nested. So if a macro wants to do something for N individual arguments, it needs to use a chain of N macros to do it. There then needs to be a way of deriving N, as a preprocessor token suitable for pasting. The easiest way of doing that was to precede each list of features by the number of features in the list. So an aarch64_feature_set initialiser for three features A, B and C would be written: AARCH64_FEATURES (3, A, B, C) This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-25Revert "arc: Update ARC's Gnu Assembler backend with ARCv3 ISA."Claudiu Zissulescu2-531/+238
This reverts commit f3d38d7d0b7346515ba603454feeddc58a3fc451.
2023-09-25arc: Update ARC's Gnu Assembler backend with ARCv3 ISA.Claudiu Zissulescu2-238/+531
The new Synopsys ARCv3 ISA has a similar instruction format like the old ARCv1 and ARCv2 ISA. Thus, the ARCv3 addition is using whatever we have for old ARC processors plus some ARCv3 spcific mods. To distinguish between various ARC variants, we introduced two new configure defines named TARGET_ARCv3_32 and TARGET_ARCv3_64 which are set when we choose either an ARC32 (ARCv3/32) ISA toolchain or an ARC64 (ARCv3/64) ISA toolchain. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gas/config/tc-arc.h: Selectively define default target macros. * gas/configure.ac: Add ARC64 target. * gas/configure.tgt: Likewise. * gas/configure: Regenerate * gas/config.in: Regenerate. * gas/config/tc-arc.c (DEFAULT_ARCH): New macro. (default_arch): New variable. (md_pseudo_table): Add xword. (md_shortopts): Only a few options are recognized by the new ARC64 assembler. (md_longopts): Likewise. (ARC_CPU_TYPE_A64x): New define. (ARC_CPU_TYPE_A32x): Likewise. (cpu_type): New arch field. (selected_cpu): Update fields. (arc_opcode_hash_entry_iterator_init): Formating. (arc_opcode_hash_entry_iterator_next): Likewise. (arc_select_cpu): Likewise. (arc_option): Likewise. (check_cpu_feature): Likewise. (debug_exp): Recognize new expression operands. (parse_reloc_symbol): Parse new signed/unsigend cases. (parse_opcode_flags): Update for the case when the flags needs insert/extract functions. (find_opcode_match): Match new signed/unsigned 32-bit immediates. (autodetect_attributes): PLT34 only available for ARC64. (md_assemble): Extend match characters. (declare_fp_set): New function. (init_default_arch): Likewise. (md_begin): Detect and initialize the correct CPU and coresponding registers. (md_pcrel_from_section): Add new relocs. (arc_target_format): New function. (md_apply_fix): Add new relocs. (md_parse_option): Update options. (arc_show_cpu_list): Update with ARC64 cpus. (md_show_usage): Update messages. (may_relax_expr): Add PLT34 case. (assemble_insn): Update for ARC64. (arc_make_nops): New function. (arc_handle_align): Refurbish this function, use arc_make_nops. (tc_arc_fix_adjustable): Update messages. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-20elf-attrs.c memory allocation failAlan Modra9-81/+137
Report errors rather than segfaulting. bfd/ * elf-attrs.c (elf_new_obj_attr): Return NULL on bfd_alloc fail. (bfd_elf_add_obj_attr_int): Handle NULL return from the above, and propagate return to callers. (elf_add_obj_attr_string, elf_add_obj_attr_int_string): Likewise. (bfd_elf_add_obj_attr_string): Similarly. (_bfd_elf_copy_obj_attributes): Report error on alloc fails. (_bfd_elf_parse_attributes): Likewise. * elf-bfd.h (bfd_elf_add_obj_attr_int): Update prototype. (bfd_elf_add_obj_attr_string): Likewise. (bfd_elf_add_obj_attr_int_string): Likewise. gas/ * config/obj-elf.c (obj_elf_vendor_attribute): Report fatal error on out of memory from bfd attribute functions. * config/tc-arc.c (arc_set_attribute_int): Likewise. (arc_set_attribute_string, arc_set_public_attributes): Likewise. * config/tc-arm.c (aeabi_set_attribute_int): Likewise. (aeabi_set_attribute_string): Likewise. * config/tc-mips.c (mips_md_finish): Likewise. * config/tc-msp430.c (msp430_md_finish): Likewise. * config/tc-riscv.c (riscv_write_out_attrs): Likewise. * config/tc-sparc.c (sparc_md_finish): Likewise. * config/tc-tic6x.c (tic6x_set_attribute_int): Likewise. * config/tc-csky.c (md_begin): Likewise. (set_csky_attribute): Return ok status.
2023-09-18Fix: Use of uninitialized memoryJacob Navia1-1/+1
* config/tc-riscv.c (riscv_ip_hardcode): Fully initialise the allocated riscv_opcode structure.
2023-09-15LoongArch: Enable gas sort relocsJinyang He1-0/+1
The md_pre_output_hook creating fixup is asynchronous, causing relocs may be out of order in .eh_frame. Define GAS_SORT_RELOCS so that reorder relocs when write_relocs. Reported-by: Rui Ueyama <rui314@gmail.com>
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich1-3/+3
Now that CpuLM is used solely in cpu_arch_flags and cpu_arch[] while Cpu64 is solely used in insn templates, they no longer need to be treated different from other "ordinary" flags; the only "unusual" one left if CpuNo64. Fold both, leaving just Cpu64.
2023-09-15x86: don't play with cpu_arch_flags.cpu{,no}64Jan Beulich1-37/+6
A total four places exists where we set the two bits from flag_code, but these values are never used. The two bits are evaluated only when coming from insn templates. Drop these assignments. Also make obvious that cpu_flags_check_cpu64() is only ever used against insn templates.
2023-09-15x86: make code size vs CPU arch checking consistentJan Beulich1-0/+18
While update_code_flag() checks for LM / i386, set_cpu_arch() so far didn't, allowing e.g. 64-bit code to be emitted after ".arch generic32". Oddly enough a few of our testcases actually exhibit bad behavior (and hence need minor adjustments).
2023-09-15x86: re-order update_code_flag()Jan Beulich1-19/+16
Do checks before updating state, and bail upon failure of either of the checks. While moving the code, eliminate some redundancy.
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich2-38/+185
Recognize "/<number>" suffixes on both -march=+avx10.1 and the corresponding .arch directive, setting an upper bound on the vector size that insns may use. Such a restriction can be reset by setting a new base architecture, by using a suffix-less form, by disabling AVX10, or by enabling any other VEX/EVEX-based vector extension. While for most insns we can suppress their use with too wide operands via registers becoming unavailable (or in Intel syntax memory operand size specifiers not being recognized), mask register insns have to have their minimum required vector size specified in a new attribute. (Of course this new attribute could also be used on other insns.) Note that .insn continues to be permitted to emit EVEX{512,256} (and VEX256 ones) encodings regardless of vector size restrictions in place. Of course these can't be expressed using zmm (or ymm) operands then, but need using the EVEX.512.* forms (broadcast forms may be usable right now, but this may go away so shouldn't be relied upon). This is why no assertions should be added to build_{e,}vex_prefix().
2023-09-14x86: support AVX10.1/512Jan Beulich1-0/+1
Since this is merely a re-branding of certain AVX512* features, there's little code to be added. The main aspect here are new testcases. In order to be able to re-use some of the existing testcases, several of them need their start symbols adjusted. Note that 256- and 128-bit tests want adding here, as these need to work right away. Subsequently they'll gain vector length constraints. Since it was missing and is wanted here, also add an AVX512VL+VPOPCNTDQ test.
2023-09-08aarch64: Remove unused functionRichard Sandiford1-7/+0
set_expected_error is no longer used. It has been replaced by more specific error messages.
2023-09-08x86: restrict prefix use with .insn VEX/XOP/EVEXJan Beulich1-0/+23
Avoid triggering the respective abort() in output_insn().
2023-09-07Use 32/64_PCREL to replace a pair of ADD32/64 and SUB32/64.cailulu2-12/+22
Subtraction for labels that require static relocation usually generates ADD32/64 and SUB32/64. If subsy of BFD_RELOC_32/64 and PC in same segment, and disable relax or PC at start of subsy or enable relax but not in SEC_CODE, we generate 32/64_PCREL to replace a pair of ADD32/64 and SUB32/64.
2023-09-07RISC-V: Clarify the naming rules of vendor operands.Nelson Chu1-85/+97
The vendor operands should be named starting with `X', and preferably the second letter (or multiple following letters) is enough to differentiate them from other vendors. Therefore, added letter `t' after `X' for t-head operands, to differentiate from future different vendor's operands. bfd/ * elfxx-riscv.c (riscv_supported_vendor_x_ext): Removed the vendor document link since it should already be recorded in the gas/doc/c-riscv.texi. gas/ * config/tc-riscv.c (validate_riscv_insn): Added `t' after `X' for t-head operands. Minor updates for indents and comments. (riscv_ip): Likewise. * doc/c-riscv.texi: Minor updates. opcodes/ * riscv-dis.c (print_insn_args): Added `t' after `X' for t-head operands. Minor updates for indents and comments. * riscv-opc.c (riscv_opcode): Likewise.
2023-09-05RISC-V: fold duplicate code in vector_macro()Jan Beulich1-40/+5
There's no need to have almost identical code twice. Do away with M_VMSGEU and instead simply use an unused (for these macros) field to tell apart both variants.
2023-09-05RISC-V: Add 'Smcntrpmf' extension and its CSRsTsukasa OI1-0/+9
This commit adds now stable and approved 'Smcntrpmf' extension defined by the RISC-V Cycle and Instret Privilege Mode Filtering specification. Note that, because mcyclecfg and minstretcfg CSRs conflict with the privileged specification version 1.9.1, CSRs for this extension are only enabled on the privileged specification version 1.10 or later. By checking the base privileged specification, we no longer need to change the design of base CSR handling. This is based on the specification version v1.0_rc1 (Frozen): <https://github.com/riscv/riscv-smcntrpmf/commit/32b752c40d59c1b5e95de83399c1f54be6669163> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add implication rule from the new 'Smcntrpmf' extension. (riscv_supported_std_s_ext): Add 'Smcntrpmf' to the supported S extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add new CSR classes CSR_CLASS_SMCNTRPMF and CSR_CLASS_SMCNTRPMF_32. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. Move "mscounteren" and "mhcounteren" CSRs and note that they are now aliases. * testsuite/gas/riscv/csr-dw-regnums.d: Reflect the change. * testsuite/gas/riscv/csr.s: Add new CSRs. Move "mscounteren" and "mhcounteren" CSRs and note that they are now reused for the 'Smcntrpmf' extension. * testsuite/gas/riscv/csr-version-1p9p1.d: Reflect the changes of csr.s. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h: Add new CSRs noting that this extension is incompatible with the privileged specification version 1.9.1. Move "mscounteren" and "mhcounteren" CSRs, make them aliases and reuse the CSR numbers from the 'Smcntrpmf' extension. (CSR_MSCOUNTEREN, CSR_MHCOUNTEREN) Remove as "mscounteren" and "mhcounteren" are now aliases and new CSR macros are used instead. (CSR_MCYCLECFG, CSR_MINSTRETCFG, CSR_MCYCLECFGH, CSR_MINSTRETCFGH): New CSR macros.
2023-09-01x86: unindent most of set_cpu_arch()Jan Beulich1-151/+154
Inverting the initial if()'s condition allows to move out the bulk of the function by a level, improving readability at least a bit. While doing that also pull the push/pop handling up first, such that "else if" after "return" isn't needed anymore; the order in which special cases are checked doesn't really matter.
2023-09-01x86: rename CpuPCLMULJan Beulich1-3/+3
The name we use internally isn't in line with the SDM, and also isn't in line with CpuVPCLMULQDQ. Add the missing suffix, but of course leave alone user facing names.
2023-09-01RISC-V: Fixed the wrong expansion for pseudo vmsge[u].vx instructions.Nelson Chu1-4/+4
The original report was from Kiva Oyama <libkernelpanic@gmail.com>, https://sourceware.org/pipermail/binutils/2023-August/129255.html The vmsge[u].vx pseudo should be expanded to masked vmslt[u].vx only when vd != v0. Otherwise, it should be expanded to unmasked one. gas/ * config/tc-riscv.c (vector_macro): Fixed the wrong expansion for pseudo vmsge[u].vx instructions. * testsuite/gas/riscv/vector-insns-vmsgtvx.d: Updated.
2023-08-31gas init_stab_section and get_stab_string_offsetAlan Modra7-31/+26
get_stab_string_offset currently creates the stabstr section if not already present, in the process keeping a reference to the malloc'd section name string. Really, the name belongs in bfd_alloc'd memory or some obstack so that it doesn't show as a memory leak on exit. s_stab_generic at least does allocate the name for the stab section on an obstack, but doesn't tidy that as well as it could. Return paths after issuing a warning don't release the memory, nor the memory for the "string" copy. This patch fixes these problems. s_stab_generic is rearranged so that creation of the sections occurs earlier, before any potential uses of the note obstack during expression parsing. That makes it possible to always free the section name strings unless used to create new sections. I've also avoided get_absolute_expression_and_terminator as I see that function might skip over end-of-line, and lack of a --input_line_pointer might have caused the following source line to be ignored. (Other uses of this function in gas are OK.) * config/obj-coff.c (obj_coff_init_stab_section): Add stabstr param. Pass to get_stab_string_offset rather than name of section. * config/obj-som.c (obj_som_init_stab_section): Likewise. * config/obj-elf.c (obj_elf_init_stab_section): Likewise. (elf_init_stab_section): Adjust. * config/obj-coff.h (INIT_STAB_SECTION): Update. (obj_coff_init_stab_section): Update prototype. * config/obj-som.h: Similarly. * config/obj-elf.h: Similarly. * config/obj-multi.h (INIT_STAB_SECTION): Update. * obj.h (struct format_ops <init_stab_section>): Update. * read.h (get_stab_string_offset): Update prototype. * stabs.c (cached_sec): Delete. (stabs_begin): Adjust to suit. (get_stab_string_offset): Add stabstr param, delete stabstr_name and free_stabstr_secname params. Don't make stabstr section here. (eat_comma): New function. (s_stab_generic): Replace stab_secname_obstack_end param with bool freenames. Move creation of stab and stabstr sections earlier, so the names can be freed earlier before possible use of notes obstack during expression parsing. Tidy error paths ensuring "string" is freed. Use get_absolute_expression in place of get_absolute_expression_and_terminator. (s_stab): Adjust. (s_xstab): Use notes_concat to make stabstr section name.
2023-08-31gas OBJ_PROCESS_STABAlan Modra6-12/+10
This macro and the supporting functions have an unused "seg" first argument. Tidy that. * config/obj-aout.c (obj_aout_process_stab): Delete first param. * config/obj-ecoff.h (OBJ_PROCESS_STAB): Likewise. * config/obj-elf.c (elf_process_stab): Likewise. * config/obj-elf.h (OBJ_PROCESS_STAB): Likewise. * config/obj-macho.h (OBJ_PROCESS_STAB): Likewise. * config/obj-multi.h (OBJ_PROCESS_STAB): Likewise. * ecoff.c (ecoff_stab): Likewise. * ecoff.h (ecoff_stab): Likewise. * obj.h (struct format_ops <process_stab>): Likewise. * stabs.c (OBJ_PROCESS_STAB): Likewise.
2023-08-25gas/ELF: allow "inheriting" section attributes and typeJan Beulich1-3/+50
While --sectname-subst is nice, it isn't enough to e.g. mimic -f{function,data}-sections in assembly code, when such use is to be optional (e.g. dependent upon some configuration setting). Assign meaning to '+' and '-' as section attribute letters, allowing to inherit the prior section's attributes (and possibly type) along with adding or removing some. Note that documenting the interaction with '?' as undefined is a precautionary measure. While touching the function invocation, stop using |= on the result of obj_elf_parse_section_letters(): "attr" is firmly zero ahead of the call.
2023-08-24kvx: use {u,}int32_t and {u,}int64_tPaul Iannetta3-19/+19
gas/ * config/kvx-parse.c (promote_token): Use {u,}int32_t and {u,}int64_t. (get_token_class): Likewise. * config/tc-kvx.c (insert_operand): Likewise. * config/tc-kvx.h (struct token_s): Likewise. (struct token_list): Likewise. opcodes/ * kvx-dis.c (struct decoded_insn): Use {u,}int32_t and {u,}int64_t. (decode_insn): Likewise. (print_insn_kvx): Likewise. (decode_prologue_epilogue_bundle): Likewise. * kvx-dis.h (struct kvx_prologue_epilogue_insn): Likewise.
2023-08-24kvx: fix handling of STB_GNU_UNIQUE symbolsPaul Iannetta1-6/+4
When processing a STB_GNU_UNIQUE symbol we did not update has_gnu_osabi correctly. * config/tc-kvx.c (kvx_end): Do not write to e_ident. (kvx_type): Properly handle STB_GNU_UNIQUE symbols.
2023-08-23kvx: O_pseudo_fixupAlan Modra3-23/+36
O_pseudo_fixup was defined as O_max+1, missing the fact that O_md1 through O_md32 enums are for use by target code. Worse, kvx-parse.c used 64 rather than O_pseudo_fixup. Fix this, and wrap some overlong lines. * config/tc-kvx.h (O_pseudo_fixup): Define. * config/tc-kvx.c (O_pseudo_fixup): Don't define here. (insert_operand): Delete bogus comment and cast. * config/kvx-parse.c (promote_token): Use O_pseudo_fixup rather than hardcoded value. Wrap overlong lines. (get_token_class): Likewise. (parse_with_restarts): Wrap overlong line.
2023-08-23kvx: ubsan: integer overflowAlan Modra2-4/+4
This fixes a few places where ubsan complains about signed integer overflow when running the testsuite, and that clz(0) is undefined. When fixing the clz problem, I also noticed that we'd get complaints if pval is ever LLONG_MIN. Fix that by using unsigned arithmetic. * config/kvx-parse.c (get_token_class): Avoid signed overflow. Don't clz(0). * config/tc-kvx.c (PARALLEL_BIT): Avoid signed overflow.
2023-08-23kvx: asan: out-of-bounds readAlan Modra1-1/+2
kvx-parse.c:parse_with_restarts does if (!tok.insn[tok.begin]) tok.class_id = -3; then a little later printf_debug (1, "\nEntering rule: %d (Trying to match: (%s)[%d])\n", jump_target, TOKEN_NAME (CLASS_ID (tok)), CLASS_ID (tok)); This results in a buffer overrun in TOKEN_NAME. Fix that. * config/tc-kvx.h (TOKEN_NAME): Check for tok <= 0, not just -1.
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento1-53/+53
Historically, flags and variables relating to architectural revisions for the A-profile architecture omitted the trailing `A' such that, for example, assembling for `-march=armv8.4-a' set the `AARCH64_ARCH_V8_4' flag in the assembler. This leads to some ambiguity, since Binutils also targets the R-profile Arm architecture. Therefore, it seems prudent to have everything associated with the A-profile cores end in `A' and likewise `R' for the R-profile. Referring back to the example above, the flag set for `-march=armv8.4-a' is better characterized if labeled `AARCH64_ARCH_V8_4A'. The only exception to the rule of appending `A' to variables is found in the handling of the `AARCH64_FEATURE_V8' macro, as it is the baseline from which ALL processors derive and should therefore be left unchanged. In reflecting the `ARM' architectural nomenclature choices, where we have `ARM_ARCH_V8A' and `ARM_ARCH_V8R', the choice is made to not have an underscore separating the numerical revision number and the A/R-profile indicator suffix. This has meant that renaming of R-profile related flags and variables was warranted, thus going from `.*_[vV]8_[rR]' to `.*_[vV]8[rR]'. Finally, this is more in line with conventions within GCC and adds consistency across the toolchain. gas/ChangeLog: * gas/config/tc-aarch64.c: (aarch64_cpus): Reference to arch feature macros updated. (aarch64_archs): Likewise. include/ChangeLog: * include/opcode/aarch64.h: (AARCH64_FEATURE_V8A): Updated name: V8_A -> V8A. (AARCH64_FEATURE_V8_1A): A-suffix added. (AARCH64_FEATURE_V8_2A): Likewise. (AARCH64_FEATURE_V8_3A): Likewise. (AARCH64_FEATURE_V8_4A): Likewise. (AARCH64_FEATURE_V8_5A): Likewise. (AARCH64_FEATURE_V8_6A): Likewise. (AARCH64_FEATURE_V8_7A): Likewise. (AARCH64_FEATURE_V8_8A):Likewise. (AARCH64_FEATURE_V9A): Likewise. (AARCH64_FEATURE_V8R): Updated name: V8_R -> V8R. (AARCH64_ARCH_V8A_FEATURES): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A_FEATURES): A-suffix added. (AARCH64_ARCH_V8_2A_FEATURES): Likewise. (AARCH64_ARCH_V8_3A_FEATURES): Likewise. (AARCH64_ARCH_V8_4A_FEATURES): Likewise. (AARCH64_ARCH_V8_5A_FEATURES): Likewise. (AARCH64_ARCH_V8_6A_FEATURES): Likewise. (AARCH64_ARCH_V8_7A_FEATURES): Likewise. (AARCH64_ARCH_V8_8A_FEATURES): Likewise. (AARCH64_ARCH_V9A_FEATURES): Likewise. (AARCH64_ARCH_V9_1A_FEATURES): Likewise. (AARCH64_ARCH_V9_2A_FEATURES): Likewise. (AARCH64_ARCH_V9_3A_FEATURES): Likewise. (AARCH64_ARCH_V8A): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A): A-suffix added. (AARCH64_ARCH_V8_2A): Likewise. (AARCH64_ARCH_V8_3A): Likewise. (AARCH64_ARCH_V8_4A): Likewise. (AARCH64_ARCH_V8_5A): Likewise. (AARCH64_ARCH_V8_6A): Likewise. (AARCH64_ARCH_V8_7A): Likewise. (AARCH64_ARCH_V8_8A): Likewise. (AARCH64_ARCH_V9A): Likewise. (AARCH64_ARCH_V9_1A): Likewise. (AARCH64_ARCH_V9_2A): Likewise. (AARCH64_ARCH_V9_3A): Likewise. (AARCH64_ARCH_V8_R): Updated name: V8_R -> V8R. opcodes/ChangeLog: * opcodes/aarch64-opc.c (SR_V8A): Updated name: V8_A -> V8A. (SR_V8_1A): A-suffix added. (SR_V8_2A): Likewise. (SR_V8_3A): Likewise. (SR_V8_4A): Likewise. (SR_V8_6A): Likewise. (SR_V8_7A): Likewise. (SR_V8_8A): Likewise. (aarch64_sys_regs): Reference to arch feature macros updated. (aarch64_pstatefields): Reference to arch feature macros updated. (aarch64_sys_ins_reg_supported_p): Reference to arch feature macros updated. * opcodes/aarch64-tbl.h: (aarch64_feature_v8_2a): a-suffix added. (aarch64_feature_v8_3a): Likewise. (aarch64_feature_fp_v8_3a): Likewise. (aarch64_feature_v8_4a): Likewise. (aarch64_feature_fp_16_v8_2a): Likewise. (aarch64_feature_v8_5a): Likewise. (aarch64_feature_v8_6a): Likewise. (aarch64_feature_v8_7a): Likewise. (aarch64_feature_v8r): Updated name: v8_r-> v8r. (ARMV8R): Updated name: V8_R-> V8R. (ARMV8_2A): A-suffix added. (ARMV8_3A): Likewise. (FP_V8_3A): Likewise. (ARMV8_4A): Likewise. (FP_F16_V8_2A): Likewise. (ARMV8_5): Likewise. (ARMV8_6A): Likewise. (ARMV8_6A_SVE): Likewise. (ARMV8_7A): Likewise. (V8_2A_INSN): `A' added to macro symbol. (V8_3A_INSN): Likewise. (V8_4A_INSN): Likewise. (FP16_V8_2A_INSN): Likewise. (V8_5A_INSN): Likewise. (V8_6A_INSN): Likewise. (V8_7A_INSN): Likewise. (V8R_INSN): Updated name: V8_R-> V8R.
2023-08-18x86: remove indirection from bx[] and di_si[]Jan Beulich1-2/+2
The longest register name is 3 characters (plus a nul one), so using a 4- or 8-byte pointer to get at it is neither space nor time efficient. Embed the names right into the array. For PIE this also slightly reduces the number of base relocations in the final image.
2023-08-17gas: tc-sparc.c: undo spurious change in ↵Jose E. Marchesi1-1/+1
5be1b787276d2adbe85ae7febc709ca517b62f08
generated by cgit v1.1 at 2025-09-27 03:43:10 +0000