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2024-03-06LoongArch: Delete extra instructions when TLS type transitionLulu Cai1-5/+26
This modification mainly changes the timing of type transition, adds relaxation to the old LE instruction sequence, and fixes bugs in extreme code models. We strictly distinguish between type transition and relaxation. Type transition is from one type to another, while relaxation is the removal of instructions under the same TLS type. Detailed instructions are as follows: 1. For type transition, only the normal code model of DESC/IE does type transition, and each relocation is accompanied by a RELAX relocation. Neither abs nor extreme will do type transition, and no RELAX relocation will be generated. The extra instructions when DESC transitions to other TLS types will be deleted during the type transition. 2. Implemented relaxation for the old LE instruction sequence. The first two instructions of LE's 32-bit and 64-bit models use the same relocations and cannot be distinguished based on relocations. Therefore, for LE's instruction sequence, any code model will try to relax. 3. Some function names have been adjusted to facilitate understanding, parameters have been adjusted, and unused macros have been deleted.
2024-03-01s390: Be more verbose about missing operand typeJens Remus1-1/+37
Provide expected operand type in s390-specific assembler operand parsing error message: "error: operand <operand-number>: missing <operand-type> operand" With <operand-type> being one of: - base register - displacement - [vector] index register - length - access register - control register - floating-point register - general-purpose register - vector register - [un]signed number gas/ * config/tc-s390.c: Provide missing operand type in error message. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case result validation patterns to operand number in operand syntax error messages. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Provide operand number in assembler warning and error messagesJens Remus1-33/+74
Prepend the operand number "operand %d:" to the s390-specific assembler operand parsing warning and error messages. While at it reword the custom operand out of range error message text to be closer to the one used by as_bad_value_out_of_range(). Additionally reword the invalid FPR pair warning message to make it nicer. gas/ * config/tc-s390.c: Print operand number in error messages. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case verification patterns to accept syntax error messages now containing the operand number. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. * testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise. * testsuite/gas/s390/zarch-z9-109-err.l: Likewise. * testsuite/gas/s390/zarch-z900-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Allow to explicitly omit base register operand in assemblyJens Remus1-3/+7
The base register operand B may be omitted in D(B) by coding D and in D(L,B) by coding D(L). The index register operand X may be omitted in D(X,B) by coding D(B) or explicitly omitted by coding D(,B). In both cases the omitted base register operand value defaults to zero. Allow to explicitly omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). Default the omitted base register operand value to zero. gas/ * config/tc-s390.c: Allow to explicitly omit the base register operand in assembly. * NEWS: Mention that the base register now may be omitted on s390. * gas/testsuite/gas/s390/zarch-base-index-0.s: Update test cases for change to allow to explicitly omit the base register operand in assembly. * gas/testsuite/gas/s390/zarch-base-index-0.d: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.s: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Warn when register name type does not match operandJens Remus1-0/+108
Print a warning message when the register type of a specified register name does not match with the operand's register type: operand {#}: expected {access|control|floating-point|general|vector} register name [as {base|index} register] Introduce a s390-specific assembler option "warn-regtype-mismatch" with the values "strict", "relaxed", and "no" as well as an option "no-warn-regtype-mismatch" which control whether the assembler performs register name type checks and generates above warning messages. warn-regtype-mismatch=strict: Perform strict register name type checks. warn-regtype-mismatch=relaxed: Perform relaxed register name type checks, which allow floating-point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating-point register (FPR) operands. This is acceptable as the FPRs are embedded into the lower halves of the VRs. Make "relaxed" the default, as GCC generates assembler code using FPR and VR interchangeably, which would cause assembler warnings to be generated with "strict". warn-regtype-mismatch=no: no-warn-regtype-mismatch: Disable any register name type checks. Tag .insn pseudo mnemonics as such, to skip register name type checks on those. They need to be skipped, as there do not exist .insn pseudo mnemonics for every possible operand register type combination. Keep track of the currently parsed operand number to provide it as reference in warning messages. To verify that the introduction of this change does not unnecessarily affect the compilation of existing code the GNU Binutils, GNU C Library, and Linux Kernel have been build with the new assembler, verifying that the assembler did not generate any of the new warning messages. gas/ * config/tc-s390.c: Handle new assembler options "[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate parsed register expressions with register type. Keep track of operand number being parsed. Print warning message in case of register type mismatch between instruction operand and parsed register expression. * doc/as.texi: Document new s390-specific assembler options "[no-]warn-regtype-mismatch[=strict|relaxed|no]". * NEWS: Mention new s390-specific register name type checks and related assembler option "warn-regtype-mismatch=strict| relaxed|no". * testsuite/gas/s390/s390.exp: Add test cases for new assembler option "warn-regtype-mismatch={strict|relaxed}". * testsuite/gas/s390/esa-g5.s: Fix register types in tests for didbr, diebr, tbdr, and tbedr. * testsuite/gas/s390/zarch-z13.s: Fix register types in tests for vgef, vgeg, vscef, and vsceg. * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s: Tests for assembler option "warn-regtype-mismatch=strict". * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l: Likewise. * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s: Tests for assembler option "warn-regtype-mismatch=relaxed". * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update test cases for assembler option "warn-regtype-mismatch" defaulting to "relaxed". * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. include/ * opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add instruction flag to tag .insn pseudo-mnemonics. opcodes/ * s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as such. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Revise s390-specific assembler option descriptionsJens Remus1-10/+18
Reorder, reword, and complete the s390-specific option descriptions. Align the formatting of s390-specific assembler options to that of the general assembler options in "as --help". While at it change a warning message to use the term "z/Architecture" instead of the deprecated "esame" (ESA Modal Extensions or ESAME) one. gas/ * config/tc-s390.c: Revise s390-specific assembler option descriptions. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add comments to assembler operand parsing logicJens Remus1-6/+25
gas/ * config/tc-s390.c: Add comments to assembler operand parsing logic. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Correct setting of highgprs flag in ELF outputJens Remus1-6/+8
The combination of an architecture size of 32 bits and z/Architecture mode requires the highgprs flag to be set in the ELF output. It causes the high-halves of the general purpose registers (GPRs) to be preserved at run-time, so that the code can use 64-bit GPRs. The architecture size of 32 bits can either be the default in case of a default architecture name of "s390" or due to specification of the option -m31 (to generate the 31-bit file format). The z/Architecture mode can either be the default or due to specification of the option -mzarch (to assemble for z/Architecture mode). It can also be selected using the pseudo commands ".machinemode zarch" and ".machinemode zarch_nohighgprs". The latter not causing the highgprs flag to be set. The highgprs flag was only set when the following s390-specific assembler options were given in the following specific order: "-m31 -mzarch". The highgprs flag was erroneously not set when: - the order of above options was inverse (i.e. "-mzarch -m31"), - the architecture mode defaulted to z/Architecture mode and option "-m31" was specified, - the architecture size defaulted to 32 bits due to a default architecture name of "s390" and option -mzarch was specified, - the architecture size defaulted to 32 bits and the architecture mode defaulted to z/Architecture due to the specified processor (e.g. "-march=z900" or follow-on processor). Determine whether to set the highgprs flag in init_default_arch() after having processed all assembler options in md_parse_option(). This ensures the flag is set in all of the above cases it was erroneously not set. Add test cases for highgprs flag, including ones that use .machinemode to switch the architecture mode. gas/ * config/tc-s390.c: Correct setting of highgprs flag in ELF output. * testsuite/gas/s390/s390.exp: Add test cases for highgprs flag. * testsuite/gas/s390/blank.s: Empty assembler source used in test cases for "highgprs" flag. * testsuite/gas/s390/esa-highgprs-0.d: Add test case for highgprs flag. * testsuite/gas/s390/zarch-highgprs-0.d: Likewise. * testsuite/gas/s390/zarch-highgprs-1.d: Likewise. * testsuite/gas/s390/esa-highgprs-machinemode-0.s: Add test case for highgprs flag when using .machinemode to switch architecture mode. * testsuite/gas/s390/esa-highgprs-machinemode-0.d: Likewise. * testsuite/gas/s390/esa-highgprs-machinemode-1.s: Likewise. * testsuite/gas/s390/esa-highgprs-machinemode-1.d: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Do not erroneously use base operand value for length operandJens Remus1-17/+18
The base register operand B may optionally be omitted in D(B) by coding D and in D(L,B) by coding D(L). The index register operand X may optionally be omitted in D(X,B) by coding D(,B) or D(B). Both base and index register operands may optionally be omitted in D(X,B) by coding D. In any case the omitted base and/or index register operand value defaults to zero. When parsing an erroneously omitted length L operand in D(L,B) by coding D(,B) the base register operand B was erroneously consumed as length operand. When using a register name for the base register operand this was detected and reported as error. But when not using a register name the base register operand value was erroneously used as length operand value. Correct the parsing of an omitted optional base or index register to not erroneously use the base register operand value as length, when erroneously omitting the length operand. While at it rename the variable used to remember whether the base or index register operand was omitted to enhance code readability. Additionally add test cases for the optional omission of base and/or index register operands. Example assembler source: mvc 16(1,%r1),32(%r2) mvc 16(1),32(%r2) mvc 16(,1),32(%r2) # undetected syntax error Disassembly of bad assembly without commit shows the base register operand value was erroneously used as length operand value: 0: d2 00 10 10 20 20 mvc 16(1,%r1),32(%r2) 6: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2) c: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2) Assembler messages with commit: 3: Error: operand 1: missing operand gas/ * config/tc-s390.c: Correct parsing of omitted base register. * testsuite/gas/s390/s390.exp: Add test cases for omitted base and/or index register. * testsuite/gas/s390/zarch-omitted-base-index.s: Test cases for omitted optional base or index register. * testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. * testsuite/gas/s390/zarch-omitted-base-index-err.s: Test cases for omitted base and/or index register. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Enhance handling of syntax errors in assemblerJens Remus1-2/+4
Do not consume any unexpected character including newline ('\n') when detecting a syntax error when parsing an operand block with parenthesis. This resolves the unfavorable assembler messages from the example below, including consuming the newline at the end of the current statement and reporting the next statement as junk. While at it change the only pre-increment of the current instruction string pointer into a post-increment to align with the other instances. Example assembler source: mvi 16(),32 # syntax error a %r1,16(%r2 # syntax error a %r1,16(%r2) mvc 16(1,),32(%r2) # syntax error mvc 16(1,%r1,32(%r2 # syntax error Assembler messages without commit: 1: Error: bad expression 1: Error: syntax error; missing ')' after base register 1: Error: syntax error; expected ',' 1: Error: junk at end of line: `32' 2: Error: syntax error; missing ')' after base register 2: Error: junk at end of line: `a %r1,16(%r2)' 4: Error: bad expression 4: Error: syntax error; missing ')' after base register 4: Error: syntax error; expected ',' 4: Error: operand out of range (32 is not between 0 and 15) 4: Error: syntax error; missing ')' after base register 4: Error: junk at end of line: `%r2)' 5: Error: syntax error; missing ')' after base register 5: Error: syntax error; expected ',' 5: Error: operand out of range (32 is not between 0 and 15) 5: Error: syntax error; missing ')' after base register 5: Error: junk at end of line: `%r2' Assembler messages with commit: 1: Error: bad expression 1: Error: syntax error; missing ')' after base register 2: Error: syntax error; missing ')' after base register 4: Error: bad expression 4: Error: syntax error; missing ')' after base register 5: Error: syntax error; missing ')' after base register 5: Error: syntax error; missing ')' after base register gas/ * config/tc-s390.c: Do not erroneously consume newline when parsing an addressing operand with parentheses. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Lower severity of assembler syntax errors from fatal to errorJens Remus1-6/+6
Report s390 assembler syntax errors as error instead of fatal error. This allows the assembler to continue and potentially report further syntax errors in the source. This should not cause syntax errors to be erroneously accepted, as both error and fatal error cause the assembler to return with a non-zero return code. The following syntax errors are changed from fatal to error: - invalid length field specified - odd numbered general purpose register specified as register pair - invalid floating point register pair. Valid fp register pair operands are 0, 1, 4, 5, 8, 9, 12 or 13. gas/ * config/tc-s390.c: Lower severity of assembler syntax errors from fatal to error. * testsuite/gas/s390/zarch-z9-109-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01x86: adjust which Dwarf2 register numbers to useJan Beulich2-23/+9
Consumers can't know which execution mode is in effect for a certain piece of code; they can only go from object file properties. Hence which register numbers to encode ought to depend solely on object file type. In tc_x86_frame_initial_instructions() do away with parsing a register name: We have a symbolic constant already for the 64-bit case, and the 32-bit number isn't going to change either. Said constant's definition needs moving, though, to be available also for non-ELF. While moving also adjust the comment to clarify that it's applicable to 64-bit mode only.
2024-03-01x86/APX: honor -mevexwig= for byte-size insnsJan Beulich1-0/+9
These uniformly ignore EVEX.W, and hence what we emit ought to be controllable by the command line option.
2024-03-01x86/APX: optimize certain XOR and SUB formsJan Beulich1-0/+28
While most logic in optimize_encoding() is already covering APX by way of the earlier NDD->REX2 conversion, there's a remaining set of cases which wants handling separately.
2024-03-01x86/APX: correct .insn opcode space determination when REX2 is neededJan Beulich1-28/+33
In this case spaces 0f38 and 0f3a may not be put in place. To achieve the intended effect, operand parsing (but not operand processing) needs pulling ahead, so we know whether eGRP-s are in use.
2024-03-01x86/APX: respect {vex}/{vex3}Jan Beulich2-43/+123
Even when an EVEX encoding is available, use of such a prefix ought to be respected (resulting in an error) rather than ignored. As requested during review already, introduce a new encoding enumerator to record use of eGPR-s, and update state transitions accordingly. The optimize_encoding() change also addresses an internal assembler error that was previously raised when respective memory operands used eGPR-s for addressing. While this results in a change of diagnostic issued for VEX-encoded insns, the new one is at least no worse than the prior one.
2024-02-29RISC-V: Add assembly support for TLSDESC.Tatsuyuki Ishi1-5/+13
gas/ * tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi, %tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype renamed to percent_op_relax_only as this matcher is extended to handle jalr as well which is not R-type. (riscv_ip): Apply the percent_op_relax_only rename and update comment. (md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to TLS relocation check list. * testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation generation. opcodes/ * riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with %tlsdesc_call annotations.
2024-02-29PR23877, bad value (n32r5900) for default CPUAlan Modra1-1/+3
Catching this at configure time would be nicer, but we'd need to exactly match mips_parse_cpu in configure.ac and keep it all in sync. PR 23877 * config/tc-mips.c (mips_after_parse_args): Don't assert that mips_parse_cpu returns non-NULL, call as_fatal with an informative message instead.
2024-02-27aarch64: rename internals related to PAuth feature to use pauth in their ↵Matthieu Longo1-2/+2
naming for coherency Hi, Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion. Regression tested on aarch64-none-elf, and no regression found. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu. From 58b38358b2788939d81f2df7f5fb4c64a31ae06e Mon Sep 17 00:00:00 2001 From: Matthieu Longo <matthieu.longo@arm.com> Date: Fri, 23 Feb 2024 11:30:40 +0000 Subject: [PATCH] aarch64: rename internals related to PAuth feature to use pauth in their naming for coherency Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion.
2024-02-24PR25333, GAS is slow processing -fdebug-types-sectionsAlan Modra3-105/+158
gas needs to build lists of sections for each group. This arranges to build the lists earlier, so they can be used when looking for sections that belong to a group. Using the section hash table to find sections by name, then by group isn't efficient when there are numerous groups with the same section names. Using a hash table to quickly find a group, then searching by section name on a list for the group results in a 100-fold speed improvement assembling the testcase in this PR. To reduce the number of times we traverse the section list, the patch also moves some processing done in elf_adjust_symtab for linked-to section, to elf_frob_file. This requires a testsuite change because processing will stop before elf_frob_file if there is a parse error in section21.s, ie. you'll only get the "junk at end of line" error, not the "undefined linked-to symbol" errors. PR 25333 * config/obj-elf.c (struct group_list, groups): Move earlier. (match_section): New function, extracted from.. (get_section_by_match): ..here. (free_section_idx): Move earlier. (group_section_find, group_section_insert): New functions. (change_section): Use the above. (elf_set_group_name): New function. (obj_elf_attach_to_group): Use elf_set_group_name. (set_additional_section_info): Handle linked_to_symbol_name and stabs code, extracted from.. (adjust_stab_sections): ..here,.. (build_additional_section_info): ..and here. (elf_adjust_symtab): Don't call build_additional_section_info. (elf_frob_file): Adjust. * config/obj-elf.h (elf_set_group_name): Declare. * config/tc-xtensa.c (cache_literal_section): Use elf_set_group_name. (xtensa_make_property_section): Likewise. * testsuite/gas/elf/attach-1.d: Stricter group section matching, and changed group section ordering. * testsuite/gas/elf/attach-2.d: Stricter group section matching. * testsuite/gas/elf/attach-2.s: Provide section bar type. * testsuite/gas/elf/elf.exp: Run attach-2. * testsuite/gas/elf/section21.l: Update. * testsuite/gas/elf/section21.s: Don't check for a parse error.
2024-02-24xtensa: move xtensa_make_property_section from bfd to gasAlan Modra1-0/+30
This function is only used by gas, so move it there. Necessary for gas to keep track of group sections as they are created. PR 25333 bfd/ * elf32-xtensa.c (xtensa_make_property_section): Delete. (xtensa_property_section_name): Make public. include/ * elf/xtensa.h (xtensa_make_property_section): Delete. (xtensa_property_section_name): Declare gas/ * config/tc-xtensa.c (xtensa_make_property_section): New, moved from elf32-xtensa.c.
2024-02-23x86: rename vec_encoding and vex_encoding_*Jan Beulich2-76/+76
Even with just VEX these weren't limited to vector insns. With APX the set of non-vector ones covered has greatly increased. Drop the vec_ prefix. Also drop the vex_ ones off of the enumerators, as they weren't appropriate anyway: Should have been vec_ then, too.
2024-02-23LoongArch: gas: Try to avoid R_LARCH_ALIGN associate with a symbolmengqinggang1-8/+19
The R_LARCH_ALIGN need to associated with a symbol if .align has the first and third expressions. If R_LARCH_ALIGN associate with a symbol, the addend can represent the first and third expression of .align. For '.align 3', the addend of R_LARCH_ALIGN only need to represent the alignment and R_LARCH_ALIGN not need to associate with a symbol. For '.align x, , y', R_LARCH_ALIGN need to associate with a symbol if 0 < y < 2^x - 4.
2024-02-22Leak in i386_elf_section_change_hookAlan Modra1-1/+1
notes_alloc is perfect for assorted memory you can't free easily and/or would rather leave freeing until just before exit. * config/tc-i386.c (i386_elf_section_change_hook): Use notes_alloc.
2024-02-21RISC-V: Don't generate branch/jump relocation if symbol is local when no-relax.Nelson Chu1-0/+8
Refer to commit, dff565fcca8137954d6ad571ef39f6aec5c0429c. Theoretically, assembler don't need to generate the pc-relative relocation and the refered local .L symbol when relaxation is disabled. The above commit improved the pcrel_hi/pcrel_lo relocations, and this commit improves branch and jump relocations. Passed the gcc/binutils regressions of riscv-gnu-toolchain. gas/ * config/tc-riscv.c (md_apply_fix): Raise fixP->fx_done for all branch and jump relocations when -mno-relax.
2024-02-20kvx: gas: missing aliases for $r14r15 in assembler.Paul Iannetta1-60/+60
Most registers from a register-pair suffixed by .lo and .hi suffixes. This was not the case of $r14 and $r15 since they are defined by the ABI: $r14 is the frame pointer, and $r15 is used to return aggregates from functions. We do not add aliases for $r12 (the stack pointer) and $r13 (the tls register). opcodes/ChangeLog: * kvx-opc.c: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate.
2024-02-20kvx: enable magic immediates for integer multiply-accumulate and CMOVE*Paul Iannetta1-2582/+2582
Affected instructions: - alu unit: cmovewp cmovehq - mau unit: maddwdp madduwdp maddsuwdp mma msbfwdp msbfuwdp msbfsuwdp mms mulwdp muluwdp mulsuwdp mm opcodes/ChangeLog: * kvx-opc.c (struct kvxopc): Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate.
2024-02-20kvx: gas: rename: or -> ior, xor -> eorPaul Iannetta1-5404/+6076
TCA instructions start with an X, this introduces ambiguities when it comes to XOR (Is it the OR on the TCA or the XOR of the core?). For this reason, we rename OR to IOR and XOR to EOR. OR and XOR variants are still valid on KV3-1 and KV3-2. However, they have been completely removed from KV4-1. opcodes/ChangeLog: * kvx-opc.c: Regenerate. include/ChangeLog: * opcode/kvx.h: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-20kvx: gas: move the splat modifier to the immediatePaul Iannetta1-5668/+6297
The position of the splat modifier is now after the operand it modifies and not attached directly to the opcode. opcodes/ChangeLog: * kvx-opc.c: Regenerate. include/ChangeLog: * opcode/kvx.h: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-20kvx: gas: fix leakPaul Iannetta1-0/+1
gas/ChangeLog: * config/tc-kvx.c (md_apply_fix): Free memory at this end.
2024-02-20kvx: Improve lexing & parsingPaul Iannetta1-18/+35
Up until now, we used ENV.PROMOTE_IMMEDIATE to get the next candidates, however this candidate can be directly extracted from the array (in kvx-parse.h) registering all the immediates. During lexing, we ignored trailing characters after a number, this is not good enough since now number can be followed by a modifier. The function READ_TOKEN and GET_TOKEN_CLASS have been update to take this into account. gas/ChangeLog: * config/kvx-parse.c (promote_token): Do not rely on env.promote_immediate anymore. (get_token_class): Do not ignore trailing characters after a number. (read_token): Likewise. (print_token_list): THIS SHOULD NOT BE HERE.
2024-02-20kvx: gas: fix the detection of negative powers of 2Paul Iannetta1-1/+1
The detection of negative powers of 2 was wrong and could lead to well-formed bundles ending up taking more syllables than necessary. gas/ChangeLog: * config/kvx-parse.c (get_token_class): Use the signed value. * testsuite/gas/kvx/np2-detection.d: New test. * testsuite/gas/kvx/np2-detection.s: New test.
2024-02-19bpf: fix bpf expression parsing regression in GASWill Hawkins1-1/+1
As a result of a switch instead of an if, as would issue non-specific error messages when it encountered an operand it could not parse in bpf. This patch fixes that regression and adds a test to prevent it from reoccurring. Tested for bpf-unknown-none on x86_64-redhat-linux. gas/ChangeLog: * config/tc-bpf.c (parse_expression): Change switch to if so that error * condition is handled. * testsuite/gas/bpf/bpf.exp: Invoke new test. * testsuite/gas/bpf/indcall-badoperand.d: New test. * testsuite/gas/bpf/indcall-badoperand.l: New test. * testsuite/gas/bpf/indcall-badoperand.s: New test.
2024-02-19bpf: gas: avoid UB in pointer subtractionJose E. Marchesi1-12/+25
The PARSE_ERROR macro in md_assemble performs pointer subtraction. If parse_expression returns NULL then the later will be part of the subtraction and therefore UB will be incurred. This patch changes md_assemble to: 1. Accommodate all invocations to parse_expression to the fact it will return NULL when a parse error occurs. 2. Avoid UB in PARSE_ERROR. Tested in bpf-unknown-none target / x86_64-linux-gnu host. gas/ChangeLog: * config/tc-bpf.c (md_assemble): Fix to take into account that parse_expression can return NULL. (PARSE_ERROR): Avoid passing invalid length to parse_error.
2024-02-19arm: Add support for Armv9.5-AClaudio Bantaloukas1-0/+3
2024-02-15x86: Display -msse-check= default as noneH.J. Lu1-1/+1
Display -msse-check= default as none for "as --help" since its default is none, not warning. PR gas/31389 * config/tc-i386.c (md_show_usage): Change -msse-check= default to none.
2024-02-15PR30308, infinite recursion in i386_intel_simplifyAlan Modra1-9/+13
This patch exposes the symbol "resolving" flag for use in i386_intel_simplify, not only preventing infinite recursion on the testcase in the PR but also more complicated cases like: .intel_syntax b = a a = b mov eax, [a] PR 30308 * symbols.c (symbol_mark_resolving, symbol_clear_resolving), (symbol_resolving_p): New functions. * symbols.h: Declare them. * config/tc-i386-intel.c (i386_intel_simplify): Delete forward declaration. Formatting. (i386_intel_simplify_symbol): Use resolving flag to prevent infinite recursion.
2024-02-14arc: Put DBNZ instruction to a separate classYuriy Kolerov1-0/+1
DBNZ instruction decrements its source register operand, and if the result is non-zero it branches to the location defined by a signed half-word displacement operand. DBNZ instruction is in BRANCH class as other branch instrucitons like B, Bcc, etc. However, DBNZ is the only branch instruction that stores a branch offset in the second operand. Thus it must be placed in a distinct class and treated differently. For example, current logic of arc_insn_get_branch_target in GDB assumes that a branch offset is always stored in the first operand for BRANCH class and it's wrong for DBNZ. include/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * opcode/arc.h (enum insn_class_t): Add DBNZ class. opcodes/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * arc-tbl.h (dbnz): Use "DBNZ" class. * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class. gas/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
2024-02-09PowerPC: Add support for Power11 optionsPeter Bergner1-0/+2
binutils/ * doc/binutils.texi (PowerPC -M option): Mention power11 and pwr11. gas/ * config/tc-ppc.c: (md_show_usage): Mention -mpower11 and -mpwr11. * doc/c-ppc.texi: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power11" and "pwr11" entries. (powerpc_init_dialect): Default to "power11".
2024-02-09x86: change type of Dwarf2 register numbers in register tableJan Beulich1-8/+6
Already the %bnd<N> registers used numbers beyond 127, and eGPR ones are all out of reach for "signed char", at least when CHAR_BITS=8. Switch to "unsigned char", covering appropriately in places where the value returned for "none" actually matters (in tc_x86_parse_to_dw2regnum() this is actually achieved by altering how X_op is set).
2024-02-08x86-64: Add R_X86_64_CODE_6_GOTTPOFFH.J. Lu1-22/+80
For add %reg1, name@gottpoff(%rip), %reg2 and add name@gottpoff(%rip), %reg1, %reg2 add #define R_X86_64_CODE_6_GOTTPOFF 50 if the instruction starts at 6 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF. Linker can covert GOTTPOFF to add $name@tpoff, %reg1, %reg2 Rewrite fx_tcbit, fx_tcbit2 and fx_tcbit3 usage to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX, R_X86_64_CODE_4_GOTPCRELX, R_X86_64_CODE_4_GOTTPOFF, R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_6_GOTTPOFF. NB: There is no need to check BFD_RELOC_X86_64_CODE_4_GOTTPOFF in md_assemble since there is only BFD_RELOC_X86_64_GOTTPOFF at this stage, which will be converted to BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_6_GOTTPOFF in i386_validate_fix. 5 relocations: #define R_X86_64_CODE_5_GOTPCRELX 46 #define R_X86_64_CODE_5_GOTTPOFF 47 #define R_X86_64_CODE_5_GOTPC32_TLSDESC 48 #define R_X86_64_CODE_6_GOTPCRELX 49 #define R_X86_64_CODE_6_GOTPC32_TLSDESC 51 are added for completeness and they are unused. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_6_GOTTPOFF. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Handle R_X86_64_CODE_6_GOTTPOFF. Issue an error for R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_relocate_section): Handle R_X86_64_CODE_6_GOTTPOFF. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_5_GOTPCRELX, BFD_RELOC_X86_64_CODE_5_GOTTPOFF, BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC, BFD_RELOC_X86_64_CODE_6_GOTPCRELX, BFD_RELOC_X86_64_CODE_6_GOTTPOFF and BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. elfcpp/ * x86_64.h (R_X86_64_CODE_5_GOTPCRELX): New. (R_X86_64_CODE_5_GOTTPOFF): Likewise. (R_X86_64_CODE_5_GOTPC32_TLSDESC): Likewise. (R_X86_64_CODE_6_GOTPCRELX): Likewise. (R_X86_64_CODE_6_GOTTPOFF): Likewise. (R_X86_64_CODE_6_GOTPC32_TLSDESC): Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (md_assemble): Don't check BFD_RELOC_X86_64_CODE_4_GOTTPOFF. Allow "add %reg1, foo@gottpoff(%rip), %reg2". (output_disp): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. Rewrite setting fx_tcbitX bits for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (md_apply_fix): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (i386_validate_fix): Rewrite fx_tcbitX bit checking for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. * testsuite/gas/i386/x86-64-gottpoff.d: Updated. * testsuite/gas/i386/x86-64-gottpoff.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". gold/ * x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle R_X86_64_CODE_6_GOTTPOFF. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. (Target_x86_64::Relocate::relocate_tls): Likewise. (Target_x86_64::Relocate::tls_ie_to_le): Handle. R_X86_64_CODE_6_GOTTPOFF. * testsuite/x86_64_ie_to_le.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". * testsuite/x86_64_ie_to_le.sh: Updated. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. ld/ * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_6_GOTTPOFF tests. * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
2024-02-06gas: x86: ginsn: handle sub-QWORD ALU with imm and MOV ops correctlyIndu Bhagat1-0/+23
PR gas/31326 SCFI must handle non QWORD ALU with imm and MOV ops correctly As per the x86 ISA manual: - 32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in the destination general-purpose register. - 8-bit and 16-bit operands generate an 8-bit or 16-bit result. The upper 56 bits or 48 bits (respectively) of the destination general-purpose register are not modified by the operation. Unlike previously thought, sub-QWORD ALU/imm and MOV ops do have implications on SCFI. SCFI/ginsn machinery does not track operation size in the ginsn representation. But given that these sub-QWORD ops update only a portion of a 64-bit destination register, for SCFI purposes, this needs to be deemed as an untraceable update (when the destination is REG_SP / REG_FP). Although in most cases, sub-QWORD ops are not expected for stack management, but the SCFI machinery must behave correctly, when such ops are indeed present. As mentioned earlier, ginsn representation does not carry operation size information. To resolve the issue raised in PR gas/31326, an option is to force the generation of GINSN_TYPE_OTHER for all cases when there is a 8/16/32 bit op. But this may dilute the utility of ginsn for other use-cases, when they pop up in future. The current approach is less disruptive than above in that it generates GINSN_TYPE_OTHER for all cases only when: - there is a 8/16/32 bit op, and - the 64-bit op is otherwise traceable. In other words this means: - For add/sub ops where dest is reg and src is reg/mem: these always make dest reg untraceable; So, the current handling is unchanged. We simply skip detecting 8/16/32-bit ops. - An x86 pop instruction is translated to a load ginsn followed by a stack increment add op. A load op always makes dest reg untraceable. Hence, if the pop instruction is sub-QWORD, we continue to (skip detecting 8/16/32-bit op, and) generate the load instruction as usual. This means that if input asm does have save and restore of unequal sized registers, gas/SCFI will not detect nor warn. - For ALU imm or MOV reg,reg, however, a GINSN_TYPE_OTHER is generated when a 8/16/32-bit op is seen. gas/ PR gas/31326 * config/tc-i386.c (x86_ginsn_addsub_reg_mem): Add a code comment. (x86_ginsn_addsub_mem_reg): Likewise. (x86_ginsn_alu_imm): Detect sub-QWORD opsize and exit early. (x86_ginsn_move): Likewise. (x86_ginsn_new): Add comment for 8-bit add/sub opcodes (in opcode_space SPACE_BASE) about skipped handling. gas/testsuite/: PR gas/31326 * gas/scfi/x86_64/ginsn-add-1.l: Update. * gas/scfi/x86_64/ginsn-add-1.s: Add some sub-QWORD add ops. * gas/scfi/x86_64/ginsn-dw2-regnum-1.l: Update. * gas/scfi/x86_64/ginsn-dw2-regnum-1.s: Use mov ops instead of add to invoke and test the ginsn_dw2_regnum code path.
2024-02-06x86: Warn .insn instruction with length > 15 bytesH.J. Lu1-2/+8
Change .insn instruction with length > 15 bytes from error to warning. PR gas/31323 * config/tc-i386.c (output_insn): Issue a warning when .insn instruction length exceeds the limit of 15 bytes. * testsuite/gas/i386/oversized64.s: Add a test for .insn * testsuite/gas/i386/oversized64.l: Updated.
2024-02-04LoongArch: gas: Fix the types of symbols referred with %le_*_r in the symtabXi Ruoyao1-0/+3
When a symbol is referred with %le_{hi20,lo12,add}_r, it's definitely a TLS symbol and we should set its type to TLS in the symtab. Otherwise when building Perl with gcc-14 -flto, we get: /usr/bin/ld: PL_current_context: TLS definition in ./miniperl.ltrans0.ltrans.o section .tbss mismatches non-TLS reference in ./miniperl.ltrans1.ltrans.o A minimal reproducer: $ cat t1.s .section .tbss .globl x x: .word 0 $ cat t2.s f: lu12i.w $a0, %le_hi20_r(x) add.d $a0, $a0, $tp, %le_add_r(x) li.w $a1, 1 st.w $a1, $a0, %le_lo12_r(x) $ gas/as-new t1.s -o t1.o $ gas/as-new t2.s -o t2.o $ ld/ld-new t1.o t2.o ld/ld-new: x: TLS definition in t1.o section .tbss mismatches non-TLS reference in t2.o Unfortunately this was undetected before Binutils-2.42 release because GCC < 14 does not use %le_*_r, and without LTO it's very rare to have a TLS LE definition and its reference in two different translation units. So this fix should be backported to Binutils-2.42 branch too. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-02-02x86: Disallow instructions with length > 15 bytesH.J. Lu1-2/+2
It is a hard error when an instruction length exceeds the limit of 15 bytes: [hjl@gnu-cfl-3 tmp]$ cat x.s .text xacquire lock addq $0x11223344, %fs:(,%eax) [hjl@gnu-cfl-3 tmp]$ gcc -c x.s x.s: Assembler messages: x.s:2: Warning: instruction length of 16 bytes exceeds the limit of 15 [hjl@gnu-cfl-3 tmp]$ objdump -dw x.o x.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 64 67 f2 f0 48 81 04 05 00 00 00 00 44 33 22 xacquire lock (bad) f: 11 .byte 0x11 [hjl@gnu-cfl-3 tmp]$ and [hjl@gnu-cfl-3 tmp]$ cat z.s addq $0xe0, %fs:0, %rdx [hjl@gnu-cfl-3 tmp]$ as -o z.o z.s z.s: Assembler messages: z.s:1: Warning: instruction length of 16 bytes exceeds the limit of 15 [hjl@gnu-cfl-3 tmp]$ objdump -dw z.o z.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 64 62 f4 ec 18 81 04 25 00 00 00 00 e0 00 00 (bad) ... [hjl@gnu-cfl-3 pr31323]$ Instructions with length > 15 bytes are always invalid. It is quite easy to generate invalid instructions with AVX now. We should issue an error when instruction length exceeds the limit of 15 bytes. PR gas/31323 * config/tc-i386.c (output_insn): Issue an error when instruction length exceeds the limit of 15 bytes. * testsuite/gas/i386/oversized16.l: Updated. * testsuite/gas/i386/oversized64.l: Likewise. * testsuite/gas/i386/x86-64-apx-inval.l: New file. * testsuite/gas/i386/x86-64-apx-inval.s: Likewise.
2024-02-02x86: move Q-suffix-to-REX.W translation logicJan Beulich1-17/+20
By pulling it ahead of the SHORT_MNEM_SUFFIX case label we can drop a part of another conditional there. While moving, also drop a pointless check: With QWORD_MNEM_SUFFIX, register operands of XCHG necessarily have both been 64-bit ones.
2024-02-02x86: actually implement .nooptJan Beulich1-1/+14
For quite some time we've had support for -O command line options. With that ignoring at least .noopt isn't really a good idea. Re-purpose the optimize-3 test for testing this directive's effect as well. As to the doc addition - this uses the same text as is there for the {nooptimize} pseudo-prefix, despite me not being convinced of the "size" part being fully accurate there (and hence also here).
2024-02-01gas: x86: ginsn: adjust ginsns for certain lea opsIndu Bhagat1-65/+57
A review comment on the SCFI V4 series was to handle ginsn creation for certain lea opcodes more precisely. Specifically, we should preferably handle the following two cases of lea opcodes similarly: - #1 lea with "index register and scale factor of 1, but no base register", - #2 lea with "no index register, but base register present". Currently, a ginsn of type GINSN_TYPE_OTHER is generated for the case of #1 above. For #2, however, the lea insn is translated to either a GINSN_TYPE_ADD or GINSN_TYPE_MOV depending on whether the immediate for displacement is non-zero or not respectively. Change the handling in x86_ginsn_lea so that both of the above lea manifestations are handled similarly. While at it, remove the code paths creating GINSN_TYPE_OTHER altogether from the function. It makes sense to piggy back on the x86_ginsn_unhandled code path to create GINSN_TYPE_OTHER if the destination register is interesting. This was also suggested in one of the previous review rounds; the other functions already follow that model, so this keeps functions symmetrical looking. gas/ * gas/config/tc-i386.c (x86_ginsn_lea): Handle select lea ops with no base register similar to the case of no index register. Remove creation of GINSN_TYPE_OTHER from the function. gas/testsuite/ * gas/scfi/x86_64/ginsn-lea-1.l: New test. * gas/scfi/x86_64/ginsn-lea-1.s: Likewise. * gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
2024-01-26x86: make "-msyntax=intel -mnaked-reg" match ".intel_syntax noprefix"Jan Beulich1-8/+15
Adjustments made for the directive (by set_intel_syntax()) need also making for the command line option. Break out respective code into a new helper function, to also be invoked during command line processing. Further also set register_prefix when processing -mnaked-reg.
2024-01-26x86/APX: optimize MOVBEJan Beulich1-4/+11
With identical source and destination it can be covered by the NDD-to- legacy conversion logic as well, even if in this case the original insn doesn't use an NDD encoding. The size savings are even better here, for the replacement (BSWAP) not having a ModR/M byte.
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