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2025-07-09gas bfd_put and bfd_get arg castsAlan Modra17-185/+185
bfd_{h_,}put_* and bfd_{h_,}get_* have "void *" pointer params nowadays. We don't need casts on their pointer args. We also don't need to cast values passed to bfd_put.
2025-07-09gas NULL castsAlan Modra58-179/+179
This removes many unnecessary NULL casts. I'm also adding a few arg casts in concat calls, to make the code consistent. Advice from quite a few years ago was that it's better to use the exact type for args corresponding to function ellipses, in case NULL is defined as plain 0. (I think that happened with some early 64-bit systems. Plain NULL ought to be OK nowadays.)
2025-07-09gas s3_FAIL and s7_FAILAlan Modra2-669/+669
s3_FAIL is defined as 0x80000000 which is unsigned, but everywhere it is used it is cast to int. Get rid of that silliness, and likewise for s7_FAIL.
2025-07-09gas more enum castsAlan Modra6-12/+11
Remove more unnecessary enum casts.
2025-07-09gas bfd_reloc_code_real_typeAlan Modra16-83/+74
Enumeration constants are integer types, so there should be no need to cast such constants to int in expressions. (Perhaps some older gccs warned, I checked back to gcc-4.5.) Remove some of those unnecessary casts. Also remove unnecessary casts to bfd_reloc_code_real_type.
2025-07-09gas frag_varAlan Modra16-64/+36
Many frag_var calls have unnecessary casts on arguments, no doubt from the days when binutils was written for K&R C. (ie. functions were not prototyped so you needed to cast anything that didn't match the expected type after default promotions, as you still do for args matching a function ellipsis.) Remove those casts. * config/tc-alpha.c (s_alpha_comm): Use offset_T for cur_size to avoid need for casts. Remove casts from frag_var args. * config/tc-ia64.c (obj_elf_vms_common): Remove casts from frag_var args. * config/tc-m32r.c (m32r_scomm): Likewise. * config/tc-m68hc11.c (build_jump_insn): Likewise. (build_dbranch_insn): Likewise. * config/tc-m68k.c (md_assemble): Likewise. * config/tc-microblaze.c (microblaze_s_lcomm): Likewise. * config/tc-mmix.c (s_loc): Likewise. * config/tc-ppc.c (ppc_elf_lcomm, ppc_comm): Likewise. * config/tc-score.c (s3_s_score_lcomm): Likewise. * config/tc-score7.c (s7_s_score_lcomm): Likewise. * config/tc-sh.c (sh_cons_align): Likewise. * config/tc-sparc.c (s_reserve, s_common): Likewise. (sparc_cons_align): Likewise. * config/tc-tic4x.c (tic4x_seg_alloc, tic4x_bss): Likewise. * config/tc-tic54x.c (tic54x_bss, tic54x_space): Likewise. (tic54x_usect, tic54x_field): Likewise. * config/tc-tic6x.c (s_tic6x_scomm): Likewise. * config/tc-v850.c (v850_offset, v850_comm): Likewise. * frags.c (frag_align, frag_align_pattern, frag_align_code): Likewise. * gen-sframe.c (output_sframe_row_entry): Likewise. (output_sframe_funcdesc): Likewise. * read.c (s_fill, do_org, s_space, emit_leb128_expr): Likewise. * symbols.c (colon)): Likewise.
2025-07-09gas pointer to int and vice versaAlan Modra4-21/+21
Use "intptr_t" or "uintptr_t" for these conversions, not "long" which is wrong on LLP64 systems, or "size_t" which is better but still not the correct type. * config/tc-alpha.c (emit_ldXu, emit_ldX, emit_uldXu, emit_uldX), (emit_stX, emit_ustX, emit_sextX): Use correct type when converting vlgsize pointer to in. Use "int" rather than "long" for result. * config/tc-ia64.c (generate_unwind_image): Use intptr_t cast when passing personality_routine to frag_var. * config/tc-ppc.c (ppc_frob_symbol <coff>): Use uintptr_t cast when converting symbol pointer to valueT. * config/tc-v850.c (md_assemble): Use intptr_t cast when loading integer opindex.
2025-07-08aarch64: Add support for FEAT_SVE2p2 and FEAT_SME2p2Alice Carlotti1-0/+5
2025-07-08aarch64: Reorder virtual feature dependenciesAlice Carlotti1-4/+3
This will improve readability when more combinations of "SVE* or SME*" are added.
2025-07-08RISC-V: Fixed mapping symbol for .option norvc directiveNelson Chu1-1/+2
2025-07-08RISC-V: Fixed that .option push/pop won't recover the xlenNelson Chu1-0/+3
2025-06-25aarch64: Add supports for FEAT_PoPS feature and DC instructions.Srinath Parvathaneni1-0/+1
This patch add support for FEAT_PoPS feature which can be enabled through +pops command line flag. This patch also adds support for following DC instructions and the spec can be found here [1]. 1. "dc cigdvaps" enabled on passing +memtag+pops command line flags. 2. "dc civaps" enabled on passing +pops command line flag. [1]: https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Instructions?lang=en
2025-06-19aarch64: Support for FEAT_LSFEEzra Sitorus1-0/+1
FEAT_LSFE - Large System Float Extension - implements A64 base atomic floating-point in-memory instructions.
2025-06-19aarch64: Support for FEAT_SVE_F16F32MM, FEAT_F8F16M, FEAT_F8F32MMEzra Sitorus1-0/+3
FEAT_SVE_F16F32MM introduces the SVE half-precision floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F32MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F16MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to half-precision instruction.
2025-06-19aarch64: Support for FEAT_CMPBREzra Sitorus1-2/+40
FEAT_CMPBR - Compare and branch instructions. This patch adds these instructions: - CB<CC> (register) - CB<CC> (immediate) - CBH<CC> - CBB<CC> where CC is one of the following: - EQ - NE - GT - GE - LT - LE - HI - HS - LO - LS
2025-06-19aarch64: Add occmo flag for FEAT_OCCMOEzra Sitorus1-0/+1
FEAT_OCCMO support was introduced, but the feature flags were missing. This patch adds these flags, as well as splitting up the tests to test occmo vs occmo+memtag operands.
2025-06-19aarch64: Support for FEAT_SVE_BFSCALEEzra Sitorus1-0/+4
FEAT_SVE_BFSCALE introduces the SVE BFSCALE instruction, when the PE is not in Streaming SVE mode. If FEAT_SME2 is implemented, FEAT_SVE_BFSCALE also introduces SME multi-vector Z-targeting BFloat16 scaling instructions, BFSCALE and BFMUL.
2025-06-13x86: don't constrain %axl/%cxlJan Beulich1-0/+5
They can be used like their %al/%cl counterparts everywhere else; there's no apparent reason why they shouldn't be usable as accumulator / shift count respectively. Enforcing such a restriction only makes writing heavily macro-ized code more cumbersome.
2025-06-13x86: swap operands in OUT-with-immediate templateJan Beulich1-33/+33
In a number of places we assume that immediates come first in the set of operands. It is mere luck that so far OUT, having operands the other way around, wasn't negatively impacted by this. Leverage this to have a few loops start from the first non-immediate operand (or in one case to stop there). Note, however, that process_immext() inserts an immediate last, so especially all output_*() functions cannot be changed in the same way.
2025-06-13gas: also maintain signed-ness for O_big expressionsJan Beulich1-0/+1
Interestingly emit_leb128_expr() already assumes X_unsigned is properly set for O_big. Adjust its conversion-to-bignum to respect the incoming flag, and have convert_to_bignum() correctly set it on output. It further can't be quite right that convert_to_bignum() depends on anything other than the incoming expression. Therefore adjust emit_expr_with_reloc() to be in line with the other invocation. This also requires an adjustment for SH, which really should have been part of 762acf217c40 ("gas: maintain O_constant signedness in more cases").
2025-06-12aarch64: Add support for FEAT_FPRCVTRichard Ball1-0/+1
FEAT_FPRCVT introduces new versions of previous instructions. The instructions are used to convert between floating points and Integers. These new versions take as operands SIMD&FP registers for both the source and destination register. FEAT_FPRCVT also enables the use of some existing AdvSIMD instructions in streaming mode. However, no changes are needed in gas to support this.
2025-06-11arm: ignore inapplicable .arch=no...Jan Beulich1-2/+6
Unlike for command line options, where a base architecture needs to be provided explicitly, the .arch directive doesn't have such a requirement. Therefore it is odd that disabling of an inapplicable extension isn't silently ignored; claiming "not allowed for the current base architecture" is at best misleading. Alter the error path to emit a more "soft" diagnostic in that case instead.
2025-06-11gas md_apply_fix value castsAlan Modra11-22/+20
These are all innocuous but unneeded. pdp11 and ppc are only formatting.
2025-06-11gas md_apply_fix bad castsAlan Modra3-3/+3
ns32k and z8k cast a valueT pointer to a long pointer when loading md_apply_fix's value. That's quite wrong if the types have different sizes, as they may eg. on a 32-bit host with 64-bit bfd support. sparc also loads the value via a cast pointer, but at least in that case the cast is to the same size pointer. None of these casts are needed. Get rid of them.
2025-06-11loongarch gcc-4.5 build fixesAlan Modra3-18/+33
Yet another case of missing fields in struct initialisation, which I've replaced with a memset, and some complaints about identifiers shadowing global declarations. Fixing the shadowing in loongarch-parse.y is easy. This one isn't so easy: gas/expr.c: In function 'expr': gas/expr.c:1891:12: error: declaration of 'is_unsigned' shadows a global declaration include/opcode/loongarch.h:224:14: error: shadowed declaration is here opcode/loongarch.h declares lots of stuff that shouldn't be made available to generic gas code, so I've removed that header from tc-loongarch.h and moved the parts of TC_FORCE_RELOCATION_SUB_LOCAL and TC_FORCE_RELOCATION_SUB_LOCAL that need LARCH_opts to functions in tc-loongarch.c * config/loongarch-parse.y (loongarch_parse_expr): Rename param to avoid shadowing. * config/tc-loongarch.c (loongarch_assemble_INSNs): Use memset rather than struct initialisation. (loongarch_force_relocation_sub_local): New function. (loongarch_force_relocation_sub_same): Likewise. * config/tc-loongarch.h: Don't include opcode/loongarch.h. (loongarch_force_relocation_sub_local): Declare, and.. (TC_FORCE_RELOCATION_SUB_LOCAL): ..use here. (loongarch_force_relocation_sub_same): Declare, and.. (TC_FORCE_RELOCATION_SUB_SAME): ..use here.
2025-06-11kvx gcc-4.5 build fixesAlan Modra2-3/+3
More missing struct initialisers, for expressionS vars that in this case don't need to be initialised. Also an error: redefinition of typedef 'symbolS'. OK, so don't use a typedef.
2025-06-11csky gcc-4.5 build fixAlan Modra1-26/+50
gcc-4.5 warns about missing csky_cpus struct initialisers. Fix that by providing everything in the init macros and the zero sentinel, rather than just a single {0} as allowed by C99.
2025-06-11gas m68hc11 use standard qsort predicate signatureAlan Modra1-4/+4
Avoid a function cast when using cmp_opcode with qsort.
2025-06-11Re: Further rs_code_align support refinementAlan Modra1-9/+9
Don't write the repeating nop pattern if it won't be used for alpha handle_align too.
2025-06-11gas: xtensa build failure with --enable-64-bit-bfdAlan Modra1-7/+13
A 32-bit host with --enable-64-bit-bfd --target=xtensa-lx106-elf give: gas/config/tc-xtensa.c: In function ‘xg_get_best_chain_entry’: gas/config/tc-xtensa.c:7689:11: error: absolute value function ‘labs’ given an argument of type ‘offsetT’ {aka ‘long long int’} but has parameter of type ‘long int’ which may cause truncation of value [-Werror=absolute-value] 7689 | if (labs (off) >= J_RANGE - J_MARGIN) | ^~~~ Let's not use labs. Unlike labs vma_abs deliberately returns an unsigned value, and does the negation in an unsigned type so that signed overflow can't happen. * config/tc-xtensa.c (vma_abs): New function. (xg_get_best_chain_entry, xg_get_fulcrum, xg_find_best_trampoline), (xg_is_relaxable_fixup): Use in place of labs.
2025-06-09str_hash_find castsAlan Modra50-250/+187
Putting an explicit cast on the void* return from str_hash_find isn't necessary and doesn't add much to code clarity. In other cases, poor choice of function parameter types, eg. "void *value" in tc-aarch64.c checked_hash_insert rather than "const void *value" leads to needing (void *) casts all over the place just to cast away const. Fix that by correcting the parameter type. (And it really is a const, the function and str_hash_insert don't modify the strings.) This patch also removes some unnecessary casts in hash.c
2025-06-09str_hash_find_intAlan Modra7-168/+125
This changes the internal representation of string_tuple.value from a void* to an intptr_t, removing any concerns that code wanting to store an integer value will use values that are trap encodings or suchlike for a pointer. The ISO C standard says any void* can be converted to intptr_t and back again and will compare equal to the original pointer. It does *not* say any intptr_t can be converted to void* and back again to get the original integer.. Two new functions, str_hash_find_int and str_hash_insert_int are provided for handling integer values. str_hash_find_int returns (intptr_t) -1 on failing to find the key string. Most target code need minimal changes to use the new interface, but some simplification is possible since now a zero can be stored and differentiated from the NULL "can't find" return. (Yes, that means (intptr_t) -1 can't be stored.) I've changed the avr_no_sreg_hash dummy value to zero, and the loongarch register numbers don't need to be incremented. loongarch also doesn't need to store an empty key string (if it ever did).
2025-06-09metag build errorAlan Modra1-5/+4
gas/config/tc-metag.c: In function ‘parse_dsp_addr’: gas/config/tc-metag.c:4386:29: error: ‘regs[0]’ may be used uninitialized [-Werror=maybe-uninitialized] 4386 | if (!is_addr_unit (regs[0]->unit) && | ~~~~~~~^~~~~~ It looks like regs_read can be zero with "l" non-NULL, so this gcc complaint is accurate. * config/tc-metag.c (parse_dsp_addr, parse_dget_set): Check regs_read.
2025-05-30elf symbol sizeAlan Modra10-111/+43
This changes elf_obj_sy.size from being malloc'd to being on the notes obstack. That means no code needs to free these expressions, which in turn means that the size expression can be shared when cloning symbols. Nothing modifies the size expressions except when resolving. In all cases I could see, if the size changes the entire expression is replaced. The patch also extracts code from elf_copy_symbol_attributes into a separate function for use by riscv and aarch64. * config/obj-elf.c (elf_obj_symbol_clone_hook): Delete. (elf_copy_symbol_size): New function, extracted and modified from.. (elf_copy_symbol_attributes): ..here. (obj_elf_size): Don't free size and use notes_alloc. (elf_frob_symbol): Don't free size. (elf_format_ops): Zero symbol_clone_hook. * config/obj-elf.h (elf_obj_symbol_clone_hook): Delete. (obj_symbol_clone_hook): Don't define. (elf_copy_symbol_size): Declare. * config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Delete. * config/tc-aarch64.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Define as elf_copy_symbol_size. * config/tc-alpha.c (s_alpha_end): notes_alloc symbol size exp. * config/tc-ia64.c (dot_endp): Likewise. * config/tc-kvx.c (kvx_endp): Likewise. * config/tc-mips.c (s_mips_end): Likewise. * config/tc-riscv.c (riscv_elf_copy_symbol_attributes): Delete. * config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Define as elf_copy_symbol_size.
2025-05-30Reduce rs_align_code memory for small alignmentsAlan Modra26-30/+52
On x86, MAX_MEM_FOR_RS_ALIGN_CODE is 35, when the most common alignment is 2**3 or 2**4, where the max memory required for the alignment nops is 7 and 15 bytes respectively. So there is some memory wasted since commit 83d94ae428b1. It's not a large amount, especially considering that frag overhead on x86_46 is 144 bytes, but even so I'd rather not be blamed for increasing gas memory usage. So to reduce the memory we'd like to take the alignment into consideration when initialising an rs_align_code frag. The only difficulty here is start_bundle making an rs_align_code frag with an alignment of zero initially, then later increasing the alignment. We change that to use the bundle alignment when setting up the frag. I think that is sufficient as bundle_align_p2 can't change in the middle of a start_bundle/finish_bundle sequence. I haven't modified any targets other than x86 in this patch. Most won't benefit much due to using fairly small MAX_MEM_FOR_RS_ALIGN_CODE. * read.c (start_bundle): Create rs_align_code frag with bundle_align_p2 alignment, then set to zero alignment. (finish_bundle): Adjust comment. * frags.c (MAX_MEM_FOR_RS_ALIGN_CODE): Pass p2align and max to macro. * config/tc-i386.h (HANDLE_ALIGN): Assert that max_bytes is sufficient for nop padding. (max_mem_for_rs_align_code): New inline function. (MAX_MEM_FOR_RS_ALIGN_CODE): Use it. * config/tc-aarch64.h: Adjust MAX_MEM_FOR_RS_ALIGN_CODE. * config/tc-alpha.h: Likewise. * config/tc-arc.h: Likewise. * config/tc-arm.h: Likewise. * config/tc-epiphany.h: Likewise. * config/tc-frv.h: Likewise. * config/tc-ia64.h: Likewise. * config/tc-kvx.h: Likewise. * config/tc-loongarch.h: Likewise. * config/tc-m32r.h: Likewise. * config/tc-metag.h: Likewise. * config/tc-mips.h: Likewise. * config/tc-nds32.h: Likewise. * config/tc-ppc.h: Likewise. * config/tc-riscv.h: Likewise. * config/tc-rl78.h: Likewise. * config/tc-rx.h: Likewise. * config/tc-score.h: Likewise. * config/tc-sh.h: Likewise. * config/tc-sparc.h: Likewise. * config/tc-spu.h: Likewise. * config/tc-tilegx.h: Likewise. * config/tc-tilepro.h: Likewise. * config/tc-visium.h: Likewise. * config/tc-xtensa.h: Likewise.
2025-05-28Further rs_code_align support refinementAlan Modra7-17/+39
Don't write the repeating nop pattern if it won't be used.
2025-05-23rs_fill_nop and md_generate_nopsAlan Modra2-1/+2
Make rs_fill_nop behave like rs_fill in using a repeat count (fr_offset) to emit fr_var length repeated nop patterns. Besides being more elegant, this reduces memory required for large .nops directives. * as.h (rs_fill_nop): Update comment. * config/tc-i386.c (i386_generate_nops): Handle rs_fill_nop as for rs_align_code. * config/tc-i386.h (MAX_MEM_FOR_RS_SPACE_NOP): Define. * listing.c (calc_hex): Handle rs_fill_nop as for rs_fill. * read.c (MAX_MEM_FOR_RS_SPACE_NOP): Define. (s_nops): Use MAX_MEM_FOR_RS_SPACE_NOP setting up frag. * write.c (write_contents): Call md_generate_nops for rs_fill_nop before the fr_fix part is written, so that rs_fill_nop can be handled as for rs_fill.
2025-05-23tidy x86 HANDLE_ALIGNAlan Modra2-53/+37
Reduce memory requirement for .align in code. I've changed some of the tests to use "clc" rather than "nop", so that code emitted by .p2align can be clearly seen. * config/tc-i386.c (i386_output_nops): Merge into.. (i386_generate_nops): ..here. Put shorter nop first. For rs_align_code make use of the fact that the last fr_var bytes are output repeatedly rather than repeating them here. * config/tc-i386.h (HANDLE_ALIGN): Don't test max_bytes. (MAX_MEM_FOR_RS_ALIGN_CODE): Update. * testsuite/gas/i386/nops-1.s, * testsuite/gas/i386/nops-2.s, * testsuite/gas/i386/nops-3.s, * testsuite/gas/i386/nops-4.s, * testsuite/gas/i386/nops16-1.s: Replace "nop" with "clc". * testsuite/gas/i386/align-branch-6.d, * testsuite/gas/i386/nop-1-suffix.d, * testsuite/gas/i386/nop-1.d, * testsuite/gas/i386/nop-1.l, * testsuite/gas/i386/nop-2.d, * testsuite/gas/i386/nop-4.d, * testsuite/gas/i386/nop-5.d, * testsuite/gas/i386/nops-1-core2.d, * testsuite/gas/i386/nops-1.d, * testsuite/gas/i386/nops-10.d, * testsuite/gas/i386/nops-2.d, * testsuite/gas/i386/nops-3.d, * testsuite/gas/i386/nops-4.d, * testsuite/gas/i386/nops-4a-i686.d, * testsuite/gas/i386/nops-5.d, * testsuite/gas/i386/nops-6.d, * testsuite/gas/i386/nops-7.d, * testsuite/gas/i386/nops-9.d, * testsuite/gas/i386/nops16-1.d, * testsuite/gas/i386/x86-64-align-branch-6.d, * testsuite/gas/i386/x86-64-nop-1.d, * testsuite/gas/i386/x86-64-nop-5.d, * testsuite/gas/i386/x86-64-nops-1-core2.d, * testsuite/gas/i386/x86-64-nops-1-pentium.d, * testsuite/gas/i386/x86-64-nops-1.d, * testsuite/gas/i386/x86-64-nops-2.d, * testsuite/gas/i386/x86-64-nops-3.d, * testsuite/gas/i386/x86-64-nops-4-core2.d, * testsuite/gas/i386/x86-64-nops-4.d, * testsuite/gas/i386/x86-64-nops-5.d, * testsuite/gas/i386/x86-64-nops-6.d, * testsuite/gas/i386/x86-64-nops-7.d: Adjust to suit.
2025-05-23tidy target HANDLE_ALIGNAlan Modra18-190/+79
avr, kvx, metag, mn10300, nds32, v850, visium, and wasm32 targets defined HANDLE_ALIGN without defining MAX_MEM_FOR_RS_ALIGN_CODE. This can result in a rather large chunk of memory being allocated. Fix that by a combination of changing the default allocation to one byte and/or defining a target MAX_MEM_FOR_RS_ALIGN_CODE. arm wanted to write out the entire set of nops, and limited allowed code alignment to 64 bytes to prevent large memory allocations. Fix that by making use of the fact that rs_align_code frags repeat fr_var bytes at fr_literal + fr_fix to fill out the required area. Fix metag, nds32 and kvx too, which it seems copied either arm or x86 in similarly not making use of repeating patterns. It's worth mentioning that my tidy to kvx changed the order of nop bundles, placing a short bundle first rather than last. epiphany was totally broken in that uninitialised data was written out for any alignment requiring more than three bytes of fill. ppc created a new frag to handle a branch over a large number of nops. This saves 4 bytes per rs_align_code frag, and most times the branch isn't used so it is generally a win for memory usage, but I figured the extra code complexity wasn't worth it. So that code of mine goes. visium copied the same scheme, so that goes too. This leaves x86 as the only target making large allocations for alignment frags. * frags.c (MAX_MEM_FOR_RS_ALIGN_CODE): Default to 1. * config/tc-aarch64.c (aarch64_handle_align): Remove always true condition. * config/tc-aarch64.h (MAX_MEM_FOR_RS_ALIGN_CODE): Move to be adjacent to HANDLE_ALIGN define. * config/tc-arm.c (arm_handle_align): Allow alignment of more than MAX_MEM_FOR_RS_ALIGN_CODE bytes. Just write one repeat of nop pattern to frag. (arm_frag_align_code): Delete function. * config/tc-arm.h (MAX_MEM_ALIGNMENT_BYTES): Don't define. (MAX_MEM_FOR_RS_ALIGN_CODE): Set to 7. (md_do_align): Don't define. (arm_frag_align_code): Don't declare. * config/tc-epiphany.c (epiphany_handle_align): Correct frag so that nop_pattern repeats rather than random data. * config/tc-epiphany.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define. * config/tc-kvx.c (kvx_make_nops): Merge into.. (kvx_handle_align): ..here. Put short nop bundle first, followed by repeated full nop bundle. * config/tc-kvx.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define. * config/tc-m32c.h (HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): Don't define. * config/tc-metag.c (metag_handle_align): Just write one repeat of nop pattern to frag. * config/tc-metag.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define. * config/tc-nds32.c (nds32_handle_align): Just write one repeat of nop pattern to frag. * config/tc-nds32.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define. * config/tc-ppc.c (ppc_handle_align): Don't make a new frag for branch. * config/tc-ppc.h (MAX_MEM_FOR_RS_ALIGN_CODE): Increase to 8. * config/tc-visium.c (visium_handle_align): Don't make a new frag for branch. * config/tc-visium.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define. * config/tc-wasm32.h (HANDLE_ALIGN): Don't define. * testsuite/gas/epiphany/nop.d, * testsuite/gas/epiphany/nop.s: New test. * testsuite/gas/epiphany/allinsn.exp: Run it. * testsuite/gas/kvx/nop-align.d: Adjust.
2025-05-22RISC-V: Add support for Smcdeleg and Ssccfg extensions.Jiawei1-0/+4
This patch rebases the original patch from Nelson's implement[1]. Added new extension Smcdeleg and Ssccfg with a new CSR, scountinhibit.[2] Co-Authored-By: Nelson Chu <nelson@rivosinc.com> Co-Authored-By: Jiawei Chen <jiawei@iscas.ac.cn> [1] https://patchwork.sourceware.org/project/binutils/patch/20240620045359.47513-1-nelson@rivosinc.com/ [2] https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0 bfd/ChangeLog: * elfxx-riscv.c: New extensions. gas/ChangeLog: * NEWS: Mention new extensions. * config/tc-riscv.c (enum riscv_csr_class): New CSR class. (riscv_csr_address): Add support for Ssccfg. * testsuite/gas/riscv/csr-version-1p10.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p10.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p11.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p11.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p12.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p12.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p13.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p13.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr.s: New Ssccfg CSR. * testsuite/gas/riscv/imply.d: New imply check. * testsuite/gas/riscv/imply.s: New implies. * testsuite/gas/riscv/march-help.l: New helping info. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTINHIBIT): New CSR address. (DECLARE_CSR): Add Ssccfg CSR.
2025-05-22ubsan: integer overflow in tc-i386.c:offset_in_rangeAlan Modra1-1/+1
or $9223372036854775808,%eax runtime error: negation of -9223372036854775808 cannot be represented in type 'offsetT' (aka 'long'); cast to an unsigned type to negate this value to itself * config/tc-i386.c (offset_in_range): Avoid signed overflow.
2025-05-19gas: sframe: i386: have the backend specify the RA tooIndu Bhagat2-9/+18
To process some CFI directives like .cfi_undefined and .cfi_same_value, it is necessary for correctness to detect all cases when the register used is one of SP, FP or RA. Currently, the backends needed to specify the SFRAME_CFA_RA_REG only in the case of those ABIs where RA tracking was necessary, e.g. AArch64. For AMD64, since the return address is always at a fixed offset from the CFA, RA tracking was disabled. The backends must now specify the applicable return address register via SFRAME_CFA_RA_REG. This is necessary so that SFrame generation code can then properly handle the cases when RA is used like so: .cfi_undefined <RA> or, .cfi_same_value <RA> Detecting these cases is necessary for correctness. E.g., on AMD64, we need to skip FDE generation as the above constructs cannot be represented in SFrame yet. This change is a prerequisite to fixing the two PRs: PR gas/32952 - sframe: incorrect handling of .cfi_undefined in gas PR gas/32953 - sframe: incorrect handling of .cfi_same_value in gas In the SFrame generation code in gen-sframe.c, instead of using SFRAME_FRE_RA_TRACKING ifdef's, we now simply rely on the API sframe_ra_tracking_p () to detect if RA-tracking is enabled for the target. While at it, use const variables for x86 backend. ChangeLog: * gas/config/tc-i386.c (x86_sframe_cfa_ra_reg): New definition. * gas/config/tc-i386.h (REG_RA): New definition. (SFRAME_CFA_RA_REG): New declaration. * gas/gen-sframe.c (SFRAME_FRE_RA_TRACKING): Remove.
2025-05-16x86: improve matching diagnostics when %st is involvedJan Beulich1-18/+46
Diagnosing operand size vs operand type mismatches doesn't work very well when GPRs and FPRs are in the same register class, distinguished just by size. Introduce a separate RegFP class.
2025-05-16x86: move Anysize check in operand_size_match()Jan Beulich1-5/+1
Anysize is applicable to memory operands only. Move the check to where memory operands are handled. (The RegSIMD part there was questionable altogether.)
2025-05-16x86: improve matching diagnostics when "accumulator" registers are involvedJan Beulich1-3/+32
In templates, the expectation of an "accumulator" register to be used is expressed solely by operand size; there's no "class" specifier there. Hence operand_size_match() is too eager in invoking match_{operand,simd}_size(), resulting in "operand size mismatch" errors when it's the type (of register), not the size that's wrong. Interestingly adjustments there alone lead to no error at all then: To "compensate", operand_type_match() needs to disambiguate register types when register instances are specified in the template (matching the actual operand), by checking a match (overlap) in operand sizes.
2025-05-16x86: fold Accum checking in operand_size_match()Jan Beulich1-16/+13
There's little point invoking match_{operand,simd}_size() twice per loop; in fact the SIMD case with D set simply doesn't exist. Amend the checks by one looking at the given operand, just like we already have been doing for memory ones.
2025-05-16x86: improve matching diagnosticsJan Beulich1-3/+10
Many times in the past I was puzzled by seeing "operand size mismatch" when really "operand type mismatch" would be far more appropriate. As it turns out, there were at least two flaws: In the single operand case we didn't propagate i.error to match_template()'s local specific_error when noticing a type mismatch. And then operand_size_match() was too eager in invoking match_mem_size(): Especially the Unspecified attribute can get in the way there when the expected operand isn't a memory one (and hence Unspecified would not be set in the operand template, whereas it's uniformly set for memory operands in AT&T syntax). (In the x86-64-lkgs-inval testcase the particular error for the two bogus Intel syntax forms doesn't really matter; all we ought to care about there isthat there is _some_ error.)
2025-05-16x86: drop bogus accumulator checkJan Beulich1-1/+0
Accum is an "instance", not a "class". With present enumerator values of Reg and Accum, the 2nd check simply did the same as the first. In fact checking for the accumulator (%rax) isn't necessary here at all, because there's no case where an individual template would permit alternatively a memory operand or the (qword) accumulator; only "any GPR" is ever being paired with "memory".
2025-05-16RISC-V: check offsets when linker relaxation is disabledTsukasa OI1-6/+38
The assembler partially relied on the linker to check whether the offset is valid. However, some optimization logic (added later) removes relocations relative to local symbols without checking offsets. For instance, it caused following code to silently emit wrong jumps (to the jump instruction "." itself) without relocations: > .option norelax > j .+0x200000 # J (or JAL) instruction cannot encode this offset. > j .+1 # Jump to odd address is not valid. This commit adds offset checks where necessary. gas/ChangeLog: * config/tc-riscv.c (md_apply_fix): Check offsets when the relocation relative to a local symbol is being optimized out. * testsuite/gas/riscv/no-relax-branch-offset-fail.s: Failure case where the branch offset is invalid. * testsuite/gas/riscv/no-relax-branch-offset-fail.d: Ditto. * testsuite/gas/riscv/no-relax-branch-offset-fail.l: Ditto. * testsuite/gas/riscv/no-relax-branch-offset-ok.s: Border case. * testsuite/gas/riscv/no-relax-branch-offset-ok.d: Ditto. * testsuite/gas/riscv/no-relax-pcrel-offset-fail-64.s: Failure case only on RV64 where the PC-relative offset exceed limits. * testsuite/gas/riscv/no-relax-pcrel-offset-fail-64.d: Ditto. * testsuite/gas/riscv/no-relax-pcrel-offset-fail-64.l: Ditto. * testsuite/gas/riscv/no-relax-pcrel-offset-fail-not-32.d: Test case for RV32 so that no errors occur. * testsuite/gas/riscv/no-relax-pcrel-offset-ok.s: Border case. * testsuite/gas/riscv/no-relax-pcrel-offset-ok.d: Ditto.
2025-05-14Remove annoying space from gas/config/obj-elf.cMatthieu Longo1-1/+1
generated by cgit v1.1 at 2025-09-18 12:21:43 +0000