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2024-07-12MIPS/GAS: Omit LI 0 for condition trapYunQiang Su1-3/+8
MIPSr6 removes condition trap instructions with imm, so we expand the instruction like "tne $2,IMM" to li $at,IMM tne $2,$at While if IMM is 0, we can use tne $2,$zero only.
2024-07-12aarch64: disable feature b16b16Matthieu Longo1-1/+3
Feature b16b16 is currently incomplete and requires re-work. Disable the command line option for b16b16, and mark the associated tests as XFAIL.
2024-07-08aarch64: Add support for sve2p1 pmov instruction.srinath1-3/+25
This patch adds support for followign SVE2p1 instruction, spec is available here [1]. 1. PMOV (to vector) 2. PMOV (to predicate) Both pmov (to vector) and pmov (to predicate) have destination scalable vector register and source scalable vector register respectively as an operand with no suffix and optional index. To handle this case we have added 8 new operands in this patch. AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */ AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */ AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */ AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */ AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */ AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */ AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */ AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */ Since the index of the <Zd> operand is optional, the index part is dropped in disassembly in both the cases of "no index" or "zero index". As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D PMOV <Pn>.D, <Zd>{[<imm>]} Example1: Assembly: pmov z5[0], p6.d Disassembly: pmov z5, p6.d Assembly: pmov z5, p6.d Disassembly: pmov z5, p6.d Example2: Assembly: pmov p4.b, z5[0] Disassembly: pmov p4.b, z5 Assembly: pmov p4.b, z5 Disassembly: pmov p4.b, z5 [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-05x86-64: Fix support for APX NF TLS IE with 2 operandsLingling Kong1-3/+2
Added the restriction in assemble for APX TLS IE that the destination can only be a register. gas/ * config/tc-i386.c (md_assemble): Added stricter restrictions for APX TLS IE.
2024-07-05aarch64: fix build with old glibcJan Beulich1-3/+3
As was pointed out several times before, old glibc declares index(), resulting in warnings from -Wshadow, in turn failing the build due to -Werror.
2024-07-04RISC-V: Fix BFD_RELOC_RISCV_PCREL_LO12_S patch issueSun Sunny1-1/+4
In commit dff565fcca8137954d6ad571ef39f6aec5c0429c, the fixups for PCREL_LO12_I and PCREL_LO12_S were mixed, so the "IMM" field were applied to incorrect position, this caused incorrect src registers to be encoded. gas/ * config/tc-riscv.c (md_apply_fix): Fix PCREL_LO12_S issue. * testsuite/gas/riscv/ixup-local.s: Updated for PCREL_LO12_S cases. * testsuite/gas/riscv/fixup-local-relax.d: Likewise. * testsuite/gas/riscv/fixup-local-norelax.d: Likewise. Signed-off-by: Jianwei Sun <sunny.sun@corelabtech.com>
2024-07-04RISC-V: hash with segment id and pcrel_hi address while recording pcrel_hiLifang Xia1-7/+17
When the same address across different segments (sections) needs to be recorded, it will overwrite the slot, leading to a memory leak. To ensure uniqueness, the segment (section) ID needs to be included in the hash key calculation. gas/ * config/tc-riscv.c (riscv_pcrel_hi_fixup): New "const asection *sec". (riscv_pcrel_fixup_hash): make sec->id and e->adrsess as the hash key. (riscv_pcrel_fixup_eq): Check sec->id at first. (riscv_record_pcrel_fixup): New member "sec". (md_apply_fix) <case BFD_RELOC_RISCV_PCREL_HI20>: Likewise. (md_apply_fix) <case BFD_RELOC_RISCV_PCREL_LO12_I>: Likewise.
2024-07-04mve: Fix encoding for vcvt[bt] single-half float conversion instructionsAndre Vieira1-4/+13
The encoding was previously not taking into account that the Quad vector registers were being encoded using their Q-register numbers rather than their D-register equivalent (multiply by 2). gas/ * config/tc-arm.c (do_neon_cvttb_1): Use Q-register vector number rather than their D-register equivalent. gas/testsuite/ * gas/arm/mve-vcvt-3.d: Correct expected values in test.
2024-07-04gas: Enhance arch-specific SFrame configuration descriptionsJens Remus4-14/+19
Explicitly mention "SFrame" in the descriptions for the architecture- specific SFrame configuration macros, variables, and functions. Use the term "frame pointer" (FP) instead of "base pointer". This aligns with the terminology used in the SFrame specification. Additionally it helps not to confuse "base-pointer register" with the term "BASE_REG" used in the specification to denote either the SP or FP register. Specify what the SFRAME_CFA_*_REG register numbers are used for: - SP (stack pointer): CFA tracking - FP (frame pointer): CFA and FP tracking - RA (return address): RA tracking Align the descriptions for definitions in the source files to the declarations in the header files. gas/ * config/tc-aarch64.h: Enhance architecture-specific SFrame configuration descriptions. * config/tc-aarch64.c: Likewise. * config/tc-i386.h: Likewise. * config/tc-i386.c: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04x86: Remove unused SFrame CFI RA register variableJens Remus1-1/+0
gas/ * config/tc-i386.c (x86_sframe_cfa_ra_reg): Remove. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04Support APX CFCMOVCui, Lili1-1/+1
The CMOVcc instruction proposed by EVEX has four different forms, corresponding to the four possible combinations of EVEX.ND and EVEX.NF values. In the encoder part, when the CFCMOV template supports EVEX_NF, it means that it requires EVEX.NF to be 1. In the decoder part, CFCMOV_Fixup is used to reverse source and destination operands in the 2-operand case. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Set NF bit for cfcmov when the insn template supports EVEX_NF. * testsuite/gas/i386/x86-64-apx-inval.l: Add invalid tests for cfcmov. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add tests for cfcmov and cmov. * testsuite/gas/i386/x86-64-apx-cfcmov-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add cfcmov instructions. * i386-dis.c (CFCMOV_Fixup): Special handling of cfcmov. (putop): Print 'cf' for cfcmov instructions. * i386-opc.h (EVEX_NF): New. * i386-opc.tbl: Add cfcmov instructions. * i386-mnem.h: Regerated. * i386-tbl.h: Regerated.
2024-07-03x86-64: Support APX NF TLS IE with 2 operandsLingling Kong1-2/+8
Support APX NF TLS IE with 2 operands.Verify it with ld and gold. gas/ * config/tc-i386.c (md_assemble): Allow APX NF TLS IE with 2 operands. * testsuite/gas/i386/x86-64-gottpoff.d: Updated. * testsuite/gas/i386/x86-64-gottpoff.s: Add APX NF TLS IE tests with 2 operands. gold/ * testsuite/x86_64_ie_to_le.s: Add APX NF TLS IE tests with 2 operands. * testsuite/x86_64_ie_to_le.sh: Updated. ld/ * testsuite/ld-x86-64/tlsbindesc.s: Add APX NF TLS IE tests with 2 operands. * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
2024-06-28aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas1-0/+1
The new -march=armv9.5-a flag enables access to the mandatory cpa, lut and faminmax extensions. Existing test cases for features are extended to verify they work without additional flags.
2024-06-28x86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich1-1/+16
With both sources being registers, these insns are almost commutative; the only extra adjustment needed is inversion of the encoded condition.
2024-06-28x86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich1-2/+8
The same properties apply there.
2024-06-28x86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich1-0/+70
..., for differing only in the resulting EFLAGS, which are left untouched anyway. That's a shorter encoding, available as long as certain constraints on operands are met; see code comments. (SHL-by-1 forms may then be subject to further optimization that was introduced earlier.) Note that kind of as a side effect this also converts multiplication by 1 to shift by 0, which is a plain move or even no-op anyway. That could be further shrunk (as could be presence of shifts/rotates by 0 in the original code as well as a fair set of other {nf}-form insns), yet the expectation (for now) is that people won't write such code in the first place.
2024-06-28x86-64: restrict by-imm31 optimizationJan Beulich1-12/+15
Avoid changing the encoding when there's no size gain: If there's a REX or REX2 prefix anyway and the base opcode wouldn't be changed, dropping just REX.W / REX2.W has no (size) effect. (Same for the AND-by-imm7 case in the same big conditional.) While there also pull out the .qword check: For the 2-register-operands case whether that's done on the 1st or 2nd operand doesn't matter. Due to reduction in necessary parentheses this improves readability a tiny bit.
2024-06-28x86/APX: optimize certain {nf}-form insns to LEAJan Beulich1-8/+236
..., as that leaves EFLAGS untouched anyway. That's a shorter encoding, available as long as certain constraints on operand size and registers are met; see code comments. Note that this requires deferring to derive encoding_evex from {nf} presence, as in optimize_encoding() we want to avoid touching the insns when {evex} was also used. Note further that this requires want_disp32() to now also consider the opcode: We don't want to replace i.tm.mnem_off, for diagnostics to still report the original mnemonic (or else things can get confusing). While there, correct adjacent mis-indentation.
2024-06-28x86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich1-1/+21
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS.CF, for the NF variants the immediate can be got rid of in that case by switching to a 1-bit rotate in the opposite direction.
2024-06-28x86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich1-1/+83
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS, for the NF variants we can safely replace ones using 0x80 by the respectively other insn while negating the immediate, saving 3 immediate bytes (just 1 though for 16-bit operand size). Similarly we can replace ones using 1 / -1 by INC/DEC (eliminating the immediate).
2024-06-25aarch64: Treat operand ADDR_SIMPLE as address with base registerJens Remus1-3/+3
The AArch64 instruction table (aarch64-tbl.h) defines the operand ADDR_SIMPLE as "address with base register (no offset)". During assembly it is correctly encoded as address with base register (addr.base_regno) in parse_operands. In warn_unpredictable_ldst it is erroneously treated as register number (reg.regno). This resolves the assembler test case "Diagnostics Quality" to erroneously fail when changing the union in struct aarch64_opnd_info from union to struct for debugging purposes. gas/ * config/tc-aarch64.c: Treat operand ADDR_SIMPLE as address with base register. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-06-25aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni1-3/+1
This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q as mentioned below, for the issues reported here. https://sourceware.org/pipermail/binutils/2024-February/132408.html 1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added as predicated instructions and this issue is fixed in this patch by replacing "SVE2p1_INSNC" with "SVE2p1_INSN" macro. 2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fixed by replacing "SVE_Zt" with "SVE_ZtxN". 3) Wrong operand qualifiers in ld1q and st1q instructions are also fixed in this patch. 4) In ld1q/st1q the index in the second argument is optional and if index is xzr and is skipped in the assembly, the index field is ignored by the disassembler. Fixing above mentioned issues helps with following: 1) ld1q and st1q first register operand accepts enclosed figure braces. 2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping sequence of vector registers. For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector registers are added along with short-form of operands for non-wrapping sequence. I have added test using following logic: ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all zeroes) ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of <Zt1> ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of <Pg> ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of <Xm> ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of <imm> (low value) ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of <imm> (high value) ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all fields (all ones) ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding. For all the above form of instructions the hyphenated form is preferred for disassembly if there are more than two registers in the list, and the register numbers are monotonically increasing in increments of one.
2024-06-25aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni1-1/+1
This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th argument an 4-bit unsigned immediate of extq instruction. The instruction encoding is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately precede in program order by a MOVPRFX instruction. Also removed the unused operand AARCH64_OPND_SVE_Zm_imm4. This issues was reported here: https://sourceware.org/pipermail/binutils/2024-February/132408.html
2024-06-24aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti1-0/+11
This includes: - FEAT_SME_F8F32 (+sme-f8f32) - FEAT_SME_F8F16 (+sme-f8f16) The FP16 addition/subtraction instructions originally added by FEAT_SME_F16F16 haven't been added to Binutils yet. They are also required to be enabled if FEAT_SME_F8F16 is present, so they are included in this patch.
2024-06-24aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti1-2/+24
This includes all the instructions under the following features: - FEAT_FP8FMA (+fp8fma) - FEAT_FP8DOT4 (+fp8dot4) - FEAT_FP8DOT2 (+fp8dot2) - FEAT_SSVE_FP8FMA (+ssve-fp8fma) - FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4) - FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
2024-06-24aarch64: Add support for virtual featuresAndrew Carlotti1-19/+45
These features will be used to gate instructions that can be enabled by either of two (or more) different sets of command line feature flags. This patch add a postprocessing step to the feature parsing code to set the value of the virtual bits.
2024-06-24aarch64: Move struct definition towards its usageAndrew Carlotti1-8/+8
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com1-4/+88
Introduces instructions for the SME2 lutv2 extension for AArch64. They are documented in the following document: * ARM DDI0602 For both luti4 instructions, we introduced an operand called SME_Znx2_BIT_INDEX. We use the existing function parse_vector_reg_list for parsing but modified that function so that it can accept operands without qualifiers and rejects instructions that have operands with qualifiers but are not supposed to have operands with qualifiers. For disassembly, we modified print_register_list so that it could accept register lists without qualifiers. For one luti4 instruction, we introduced a SME_Zdnx4_STRIDED. It is similar to SME_Ztx4_STRIDED and we could use existing code for parsing, encoding, and disassembly. For movt instruction, we introduced an operand called SME_ZT0_INDEX2_12. This is a ZT0 register with a bit index encoded in [13:12]. It is similar to SME_ZT0_INDEX. We also introduced an iclass named sme_size_12_b so that we can encode size bits [13:12] correctly when only 'b' is allowed as qualifier.
2024-06-21x86: optimize {,V}PEXTR{D,Q} with immediate of 0Jan Beulich1-0/+38
Such are equivalent to simple moves, which are up to 3 bytes shorter to encode (and perhaps also cheaper to execute).
2024-06-21x86: optimize left-shift-by-1Jan Beulich1-0/+79
These can be replaced by adds when acting on a register operand. While for the scalar forms there's no gain in encoding size, ADD generally has higher throughput than SHL. EFLAGS set by ADD are a superset of those set by SHL (AF in particular is undefined there). For the SIMD cases the transformation also reduced code size, by eliminating the 1-byte immediate from the resulting encoding. Note that this transformation is not applied by gcc13 (according to my observations), so would - as of now - even improve compiler generated code.
2024-06-21x86: %riz, %rip, and %eip don't require REXJan Beulich1-2/+2
While these can't be used as register operands, they can be used for memory operand addressing. Such uses do not prevent conversion: The RegRex64 checks in check_Rex_required() for base and index registers were simply wrong. They specifically also aren't needed for byte registers, as those won't pass i386_index_check() anyway.
2024-06-21x86: don't suppress errors when optimizingJan Beulich1-1/+16
Blindly ignoring any mnemonic suffix can't be quite right: Bad suffix / operand combinations still want flagging. Simply avoid optimizing in such situations.
2024-06-18Support APX CCMP and CTESTCui, Lili1-1/+145
CCMP and CTEST are two new sets of instructions for conditional CMP and TEST, SCC and OSZC flags are given as suffixes of CCMP or CTEST in the instruction mnemonic, e.g.: ccmp<cc> { dfv=sf , cf , of } %eax, %ecx also add {evex} cmp/test %eax, %ecx as an alias for ccmpt. For the encoder part, add function check_Scc_OszcOperation to parse '{ dfv=of , sf, sf, cf}', store scc in the lower 4 bits of base_opcode, and adjust base_opcode to its normal meaning in install_template. For the decoder part, add 'SC' and 'DF' macros to add scc and oszc flags suffixes. gas/ChangeLog: * config/tc-i386.c (OSZC_CF): New. (OSZC_ZF): Ditto. (OSZC_SF): Ditto. (OSZC_OF): Ditto. (set_oszc_flags): Set oszc flags and report error for using the same oszc flags twice. (check_Scc_OszcOperations): Handle SCC OSZC flags. (install_template): Add scc and oszc_flags. (build_apx_evex_prefix): Encode SCC and oszc flags bits. (parse_insn): Handle check_Scc_OszcOperations. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add ivalid test case. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add test for ccmp and ctest. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d: New test. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.d: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add ccmp and ctest. * i386-dis-evex.h: Ditto. * i386-dis.c (struct instr_info): add scc. (struct dis386): Add new micro 'NE','SC' and'DF'. (get_valid_dis386): Get scc value and move MAP4 invalid check to print_insn. (putop): Handle %NE, %SC and %DF. * i386-opc.h (SCC): New. * i386-opc.tbl: Add ccmp/ctest and evex format for cmp/test. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto.
2024-06-18LoongArch: add .option directiveLulu Cai1-0/+59
In some cases we may want to use different options only for certain assembly, so the .option directive is added to control the assembler options. .option can accept 4 parameters: push pop Pushes or pops the current option stack. They limit the scope of option changes so that they do not affect other parts of the assembly file. relax norelax Enables or disables relaxation.
2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas1-0/+8
The FEAT_BRBE extension provides two aliases of sys: - brb iall (Invalidates all Branch records in the Branch Record Buffer) - brb inj (Injects the Branch Record held in BRBINFINJ_EL1, BRBSRCINJ_EL1, and BRBTGTINJ_EL1 into the Branch Record Buffer) This patch adds: - the feature option "brbe" that must be added for the aliases to be available - a new operand flag AARCH64_OPND_Rt_IN_SYS_ALIASES that warns in a comment when Rt is set to the non default value 0b11111 (it is constrained unpredictable whether the instruction is undefined or behaves as if the Rt field is set to 0b11111). - a new operand flag AARCH64_OPND_BRBOP that encodes and decodes Op2 values from bit 5 - support for the two brb aliases above See: - https://developer.arm.com/documentation/ddi0602/2024-03/Base-Instructions/BRB--Branch-Record-Buffer--an-alias-of-SYS-?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-INJ--Branch-Record-Injection-into-the-Branch-Record-Buffer?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-IALL--Invalidate-the-Branch-Record-Buffer?lang=en
2024-06-12RISC-V: Support S[sm]csrind extension csrs.Jiawei1-0/+22
This patch supports RISC-V Smcsrind/Sscsrind privilege extension csrs. Reuse csr 'smselect/siselect', 'mireg/sireg' and 'vsiselect,vsireg' csrs in Smaia/Ssaia extension. bfd/ChangeLog: * elfxx-riscv.c: New extensions. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (enum riscv_csr_class): New extensions. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extensions. include/ChangeLog: * opcode/riscv-opc.h (CSR_MIREG2): New csr. (CSR_MIREG3): Ditto. (CSR_MIREG4): Ditto. (CSR_MIREG5): Ditto. (CSR_MIREG6): Ditto. (CSR_SIREG2): Ditto. (CSR_SIREG3): Ditto. (CSR_SIREG4): Ditto. (CSR_SIREG5): Ditto. (CSR_SIREG6): Ditto. (CSR_VSIREG2): Ditto. (CSR_VSIREG3): Ditto. (CSR_VSIREG4): Ditto. (CSR_VSIREG5): Ditto. (CSR_VSIREG6): Ditto. (DECLARE_CSR): Ditto.
2024-06-10aarch64: warn on unpredictable results for new rcpc3 instructionsMatthieu Longo1-1/+39
The previous patch for the feature rcpc3 introduced 4 new operations (ldiapp, stilp, ldapr, stlr). The specification mentions some cases of inputs causing unpredictable results. gas currently fails to diagnose them, and does not emit warnings. Even if the instruction encoding is valid, the developer probably wants to know for those cases that the instruction won't have the expected effect. - ldiapp & stilp: * unpredictable load pair transfer with register overlap * unpredictable transfer with writeback - ldapr & stlr: * unpredictable transfer with writeback This patch also completes the existing relevant tests.
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich1-1/+5
Extremely rarely used attributes are inefficient when represented by a separate attribute. Convert it to an operand constraint, as already suggested during review. The collision with RegKludge is pretty simple to resolve.
2024-06-05arm: remove FPA instructions from assemblerRichard Earnshaw1-699/+0
These can no-longer be generated as the options to reach them have now gone. So remove the parsing support for FPA instructions.
2024-06-05arm: remove options to select the FPARichard Earnshaw1-15/+1
Remove the command-line options to choose the FPA (or FPE - an emulated FPA). From this point on it should be impossible to assemble the old FPA instructions.
2024-06-05arm: change default FPUs from FPA to noneRichard Earnshaw1-62/+63
Change the cases where the default FPU was FPA to none. This should ensure that any code that used settings to pick the floating-point order will not silently produce a different output. The options that explicitly set the FPA remain for the moment.
2024-06-05arm: redirect fp constant data directives through a wrapperRichard Earnshaw1-5/+20
Assembler directives such as .float, or .double are handled by generic code, but on Arm, their output can vary depeding on the type of FPU begin targetted. When we remove FPA support we don't want to silently generate different code for processors that previously defaulted to the FPA, so redirect these directives through a wrapper function that checks the FPU is enabled; we use the legacy -mno-fpu in the test to catch this. Also fix a few tests so that they won't start to fail on targets (eg arm-wince-pe) where there is no default format for the FPU and we pick this from the default processor type.
2024-06-05arm: adjust FPU selection logicRichard Earnshaw1-9/+2
The logic here seems to be overly complex, so simplify it a bit. One particular problem was that using the legacy -mno-fpu option was not working properly, as this has all the feature bits set to zero causing the code to then pick a different FPU as the default. Fix this by only selecting an FPU as a fallback if the code has not otherwise selected one: there was only one route by which this could happen. This patch is really a pre-cursor to the following one where we want to make no-fpu internally a fall-back position for some legacy processors where previously we would have dropped back to the FPA.
2024-06-05arm: default to softvfp on armv6 or later coresRichard Earnshaw1-17/+17
From armv6 onwards a lot of cores started to come with a physical VFP implementation; but many still did not and in some cases there are both variants. For the cores that lacked a physical VFP we would fall back to FPU_NONE if the platform/ABI did not mandate something else. To make matters worse, FPU_NONE is internal state used to imply soft-fpa (ie a mixed-endian double format), so any use of .double in hand-written assembly is almost certainly generating incorrect output. That's undesirable, all these cores should really default to a softvfp model.
2024-06-05arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFPRichard Earnshaw5-58/+96
FPU_ARCH_VFP has always meant VFP floating-point format (natural FP word order) but without any VFP instructions. But the name FPU_ARCH_VFP is potentially confusing. This patch just changes the name to make the meaning clearer.
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-1/+11
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> Nazareno Bruschi <nazareno.bruschi@embecosm.com> Lin Sinan include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbi as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-bi-beqimm.d: New test. * testsuite/gas/riscv/cv-bi-beqimm.s: New test. * testsuite/gas/riscv/cv-bi-bneimm.d: New test. * testsuite/gas/riscv/cv-bi-bneimm.s: New test. * testsuite/gas/riscv/cv-bi-fail-march.d: New test. * testsuite/gas/riscv/cv-bi-fail-march.l: New test. * testsuite/gas/riscv/cv-bi-fail-march.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvbi string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add disassembly for new operand. * riscv-opc.c: Add XCVbi instructions.
2024-06-04LoongArch: Make align symbol be in same section with alignment directivemengqinggang2-1/+65
R_LARCH_ALIGN (psABI v2.30) requires a symbol index. The symbol is only created at the first time to handle alignment directive. This means that all other sections may use this symbol. If the section of this symbol is discarded, there may be problems. Search it in its own section. Remove elf_backend_data.is_rela_normal() function added at commit daeda14191c. Co-authored-by: Jinyang He <hejinyang@loongson.cn> Reported-by: WANG Xuerui <git@xen0n.name> Link: https://lore.kernel.org/loongarch/2abbb633-a10e-71cc-a5e1-4d9e39074066@loongson.cn/T/#t
2024-05-31x86: reduce check_{byte,word,long,qword}_reg() overheadJan Beulich1-4/+15
These run after template matching. Therefore it is quite pointless for them to check all operands, when operand sizes matching across operands is already known. Exit the loops early in such cases. In check_byte_reg() also drop a long-stale part of a comment.
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich1-0/+13
Except for very few insns mnemonic suffixes aren't permitted in Intel syntax. Warn about such for now, indicating that they will be outright refused down the road. While fiddling with testcases to address fallout, drop a few things which should never have been tested as valid Intel syntax. Also add a previously missing line to simd-suffix.d.
2024-05-29x86/Intel: SHLD/SHRD have dual meaningJan Beulich1-2/+5
Since we uniformly permit D suffixes in Intel mode whenever in AT&T mode an L suffix may be used, we need to be consistent with this. Take the easy route, despite that still leading to an anomaly which is also visible from the new testcase: shld eax, ecx, 1 shld eax, ecx, cl can mean two things with APX: SHL with a D suffix in NDD EVEX encoding, or the traditional SHLD in legacy encoding.
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