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2024-12-02x86/COFF: support RVA (image-relative) relocations in insn operandsJan Beulich1-1/+7
As was pointed out in [1] compilers produce code using such constructs, and hence we'd better support this. In analogy to the .rva directive permit @rva to be used for this, and in analogy with other architectures (plus to not diverge from e.g. Clang's integrated assembler, albeit I haven't been able myself to confirm it knows this form) also permit @imgrel. While there also adjust the operand type specifier for the adjacent @secrel32 - 64-bit fields cannot be used with a 32-bit relocation. Further while there also deal with *-*-pe* in x86-64.exp, even if (right now) perhaps only for completeness. [1] https://sourceware.org/pipermail/binutils/2024-November/137548.html
2024-11-29s390: Simplify parsing of omitted index register operandJens Remus1-16/+8
The index register operand X in D(X,B) can optionally be omitted by coding D(,B) or D(B). Simplify the parsing logic. gas/ * config/tc-s390.c (md_gather_operands): Rename omitted_base_or_index to omitted_index and simplify logic. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-29s390: Treat addressing operand sequence as one in assemblerJens Remus1-14/+34
The assembler erroneously treated any number of operands as optional, if the instruction was flagged to have one or two optional operands (i.e. optparm or optparm2). Only treat the exact specified number of operands as optional while treating addressing operand sequences D(X,B), D(B), and D(L,B) as one operand. gas/ * config/tc-s390.c (operand_count): New helper to count the remaining operands, treating D(X,B), D(B), and D(L,B) as one. (skip_optargs_p): Use new helper operand_count to treat D(X,B), D(B), and D(L,B) as one operand. (md_gather_operands): Use skip_optargs_p to skip only the optional last operands. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-29x86: restrict gas'es recognition of -s to SolarisJan Beulich1-3/+8
When there for Solaris compatibility only, also recognize it only there. This way the option becomes available for other possible uses. While adjusting md_shortopts[], also re-arrange things such that we have only a single, uniform definition of it.
2024-11-29x86/Solaris: support Sun form of CMOVccJan Beulich1-0/+27
Sun specifies an alternative form for CMOVcc [1], which for some reason we never cared to support, even if - as per gcc's configure checking for it - it may have been the only permitted form at some point. While documentation doesn't indicate FCMOVcc to have similar alternative forms, gcc assumes so. Hence cover FCMOVcc as well. [1] https://docs.oracle.com/cd/E37838_01/html/E61064/ennbz.html#XALRMeoizm
2024-11-26nios2: Remove binutils support for Nios II target.Sandra Loosemore3-4239/+0
The Nios II architecture has been EOL'ed by the vendor. This patch removes all binutils, bfd, gas, binutils, and opcodes support for this target with the exception of the readelf utility. (The ELF EM_* number remains valid and the relocation definitions from the Nios II ABI will never change in future, so retaining the readelf support seems consistent with its purpose as a utility that tries to parse the headers in any ELF file provided as an argument regardless of target.)
2024-11-20arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M MainlineAndre Vieira1-1/+17
Add support for pac_key_[pu]_[0-3](_ns)? register operands for the MRS and MSR instructions when assembling for Armv8.1-M Mainline, as well as adding the corresponding support for disassembling instructions that use it.
2024-11-20RISC-V: Add Zcmt instructions and csr.Jiawei1-0/+29
This patch supports Zcmt[1] instruction 'cm.jt' and 'cm.jalt'. Add new CSR jvt for tablejump using. Since 'cm.jt' and 'cm.jalt' have the same instructiong encoding, use 'match_cm_jt' and 'match_cm_jalt' check the 'zcmt_index' field to distinguish them. [1] https://github.com/riscvarchive/riscv-code-size-reduction/releases Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): New CSR. (riscv_csr_address): Ditto. (validate_riscv_insn): New operand. (riscv_ip): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. * testsuite/gas/riscv/zcmt-fail.d: New test. * testsuite/gas/riscv/zcmt-fail.l: New test. * testsuite/gas/riscv/zcmt-fail.s: New test. * testsuite/gas/riscv/zcmt.d: New test. * testsuite/gas/riscv/zcmt.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_JT): New opcode. (MASK_CM_JT): New mask. (MATCH_CM_JALT): New opcode. (MASK_CM_JALT): New mask. (CSR_JVT): New CSR. (DECLARE_INSN): New declaration. (DECLARE_CSR): Ditto. * opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco. (ENCODE_ZCMT_INDEX): Ditto. (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operand. * riscv-opc.c (match_cm_jt): New function. (match_cm_jalt): Ditto.
2024-11-19Support x86 Intel MSR_IMMHu, Lin11-10/+15
gas/ChangeLog: * NEWS: Support x86 Intel MSR_IMM. * config/tc-i386.c (cpu_arch): Add MSR_IMM. (cpu_flags_match): Add MSR_IMM to APX_F related processing. (i386_assemble): WRMSRNS's first operand is imm32, so add MN_wrmsrns like MN_uwrmsr. * doc/c-i386.texi: Document .msr_imm. * testsuite/gas/i386/i386.exp: Run MSR_IMM tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/msr_imm-inval.l: New test. * testsuite/gas/i386/msr_imm-inval.s: Ditto. * testsuite/gas/i386/x86-64-msr_imm-intel.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add REG_VEX_MAP7_F6_L_0_W_0, PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, VEX_LEN_MAP7_F6, VEX_W_MAP7_F6_L_0. (reg_table): New entry for MSR_IMM. (prefix_table): Ditto. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map7_f6_opcode): New variable for MAP7. (get_valid_dis386): Support MAP7. * i386-gen.c (cpu_flags): Add MSR_IMM. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumsr_imm. * i386-opc.tbl: Add MSR_IMM instructions. * i386-tbl.h: Regenerated.
2024-11-18x86: rename SPACE_{,E}VEX_MAP<N>Jan Beulich1-21/+21
Map7 already has dual purpose for USER-MSR (and is to gain more for MSR-IMM), while Map5 is about to gain VEX uses for AMX extensions. Drop the not really meaningful infixes and (in the opcode table) prefixes, retaining merely EVexMap4 for encoding EVex128 at the same time.
2024-11-18x86: VP2INTERSECT{D,Q} have mask register destination groupJan Beulich1-0/+6
Much like AVX512-{4FMAPS,4VNNIW} have a constraint on their register source, there's a constraint (need to be even) on the destination register here. Adjust "good" test cases accordingly, and add a new test case to check the warning.
2024-11-18x86: generalize "implicit quad group" handlingJan Beulich1-15/+28
We'll want to re-use it for VP2INTERSECT{D,Q}. While there add a testcase for the similarly affected AVX512-4VNNIW insns.
2024-11-18ELF: SHF_STRINGS isn't really tied to SHF_MERGEJan Beulich1-13/+17
It's not overly useful without it, but the spec doesn't name any dependency between the two. People may want to use it for purely informational purposes, for example. Adjust, in particular, entity size processing to be engaged if either flag is set, as mandated by the spec.
2024-11-18ELF: SHF_MERGE vs SHT_NOBITSJan Beulich1-0/+3
bfd/merge.c puts in quite some effort to track mergable sections. That's all wasted for sections which don't have contents, as for them _bfd_write_merged_section() will never be called. With the combination not having any useful effect, also warn about this in gas.
2024-11-18gas/ELF: also reject merge entity size being zeroJan Beulich1-1/+1
This won't have any useful effect, so is at best marginally less bogus than a negative value. The change actually points out a flawed (for Arm) testcase: @ is a comment character there.
2024-11-08aarch64: remove redundant register type R_NMatthieu Longo1-5/+1
The register type R_N is redundant with R_ZR_SP. This patch removes it, and replaces its usage by R_ZR_SP.
2024-11-08aarch64: constify unchanged char* argumentsMatthieu Longo1-1/+1
2024-10-30x86: add a helper to copy insn operand infoJan Beulich1-133/+44
We're doing such in fairly many places, and yet more are likely to appear; centralize the logic, much like we already have swap_2_operands(). While there also correct mis-indentation in adjacent code in process_operands().
2024-10-30x86/APX: support JMPABS also in assemblerJan Beulich2-5/+25
Without this APX support isn't really complete. For Intel syntax displacement form is needed, such that symbolic operands won't need prefixing by "offset". (The other form is actually not used at all in Intel syntax.) For the record: To restrict displacement form to Intel syntax is not something I actually agree with.
2024-10-30x86/APX: squash REX prefix when REX2 is being emittedJan Beulich1-1/+3
We should not (silently) emit a REX prefix ahead of a REX2-encoded insn; such encodings are illegal. Best we can do is fold the REX bits into the REX2 prefix, and then zap the REX one from i.prefix[].
2024-10-29LoongArch: Corrected to GNU style codeLulu Cai1-10/+10
2024-10-29gas: constify md_{short,long}opts and md_longopts_sizeJan Beulich75-233/+227
First of all make the declarations globally visible, such that producer and consumer actually share them. For the latter two simply add const (as PPC already had it,), while for the former achieve the effect by converting to an array: There's no need for the extra level of indirection.
2024-10-24Replace uses of asprintf with xasprintfAlan Modra2-17/+4
xasprintf has a nicer interface and behaves like xmalloc as far as memory is concerned, ie. no need to check a return status and the program exits with an error on OOM. binutils/ * dwarf.c (load_debug_sup_file): Replace asprintf with xasprintf. * nm.c (get_elf_symbol_type, get_coff_symbol_type): Likewise. * objdump.c (dump_ctf_indent_lines): Likewise. * readelf.c (display_lto_symtab, dump_ctf_indent_lines): Likewise. * windres.c (main): Likewise. * configure.ac: Remove asprintf from AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate. gas/ * config/tc-kvx.c (kvx_emit_single_noop): Simplify. * config/tc-riscv.c (md_assemblef): Replace asprintf with xasprintf. * read.c (s_nop, do_s_func): Likewise. * stabs.c (stabs_generate_asm_func): Likewise. (stabs_generate_asm_endfunc): Likewise. * configure.ac: Remove asprintf from AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate. ld/ * ldlang.c (lang_leave_overlay_section): Replace xmalloc+sprintf with xasprintf. Localise vars. * lexsup.c (parse_args): Replace asprintf with xasprintf. * pe-dll.c (make_head, make_tail, make_one): Likewise. (make_singleton_name_thunk, make_import_fixup_entry): Likewise. (make_runtime_pseudo_reloc): Likewise. (pe_create_runtime_relocator_reference): Likewise. * configure.ac: Remove asprintf from AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate.
2024-10-22LoongArch: Force relocation for every reference to the global offset tableLulu Cai2-0/+27
Local absolute symbols are resolved at assembly stage and the symbol value is placed in the relocation addend. But non-zero addend will cause an assertion failure during linking. Forces emission of relocations to defer resolution of local abs symbols until link time. bfd/ * elfnn-loongarch.c (loongarch_elf_relax_section): Determine absolute symbols in advance to avoid ld crash. gas/ * config/tc-loongarch.c (loongarch_force_relocation): New function to force relocation. * config/tc-loongarch.h (TC_FORCE_RELOCATION): New macros to force relocation. (loongarch_force_relocation): Function declaration. * testsuite/gas/loongarch/localpic.d: New test. * testsuite/gas/loongarch/localpic.s: New test.
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc1-0/+1
gas/ChangeLog: * NEWS: Support ZHAOXIN GMI instructions. * config/tc-i386.c: Add gmi. * doc/c-i386.texi: Document gmi. * testsuite/gas/i386/i386.exp: Add gmi test. * testsuite/gas/i386/gmi.d: Ditto. * testsuite/gas/i386/gmi.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New comment. * i386-gen.c: Add gmi. * i386-opc.h (CpuGMI): New. * i386-opc.tbl: Add Zhaoxin GMI instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2024-10-15x86: Refine instruction check in x86_check_tls_relocationCui, Lili1-10/+11
gas/ChangeLog: * config/tc-i386.c (x86_check_tls_relocation): Refine instruction check.
2024-10-14gas: drop SKIP_WHITESPACE_AFTER_NAME()Jan Beulich15-72/+69
Exclusively all users should use restore_line_pointer() instead, at which point SKIP_WHITESPACE() suffices as a check afterwards.
2024-10-14LoongArch: Fixed R_LARCH_[32/64]_PCREL generation bugLulu Cai1-1/+2
The enum BFD_RELOC_[32/64] was mistakenly used in the macro instead of the relocation in fixp. This can cause the second relocation of a pair to be deleted when -mthin-add-sub is enabled. Apply the correct macro to fix this. Also sets the initial value of -mthin-add-sub.
2024-10-11x86: bring 64-bit-only cmdline option handling in syncJan Beulich1-2/+8
--64 and --x32 are already suppressed in --help output when BFD64 is not defined. Also avoid recognizing these options in such configurations.
2024-10-10s390: Add arch15 instructionsAndreas Krebbel1-0/+2
opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
2024-10-04gas: hide emulation struct format_ops instances when not neededJan Beulich7-114/+131
Most targets don't even support emulations, so this data (and certain functions) are entirely dead code for them.
2024-10-04x86: prune OBJ_MAYBE_... usesJan Beulich3-169/+113
With the removal of emulations, OBJ_MAYBE_... can no longer be defined. Tidy code wherever they're used, which also includes the dropping of most IS_ELF and uses and checks of OUTPUT_FLAVOR. Where touching such constructs anyway, also drop TE_PEP checks when used together with TE_PE ones (the former implies the latter).
2024-10-04x86: drop largely defunct gas emulationsJan Beulich3-84/+0
Both ELF and COFF have various sub-flavors, each of which would then require its own emulation: Right now when configuring a COFF/PE secondary target (with perhaps an ELF primary one), one gets plain COFF emulation rather than COFF/PE one. As such a multitude of emulations would be unwieldy (and likely fragile) drop gas emulations altogether instead.
2024-10-04include: de-duplicate i386.h and x86_64.hJan Beulich1-6/+1
Move common definitions to a new x86.h, thus allowing gas'es obj-coff.h to include just that, getting rid of a TE_PEP compile-time dependency.
2024-10-04gas: drop generate_asm_lineno emulation hookJan Beulich4-13/+0
It's not wired up, so can't be used.
2024-10-04gas: don't use COFF-specific SF_SET_LOCAL() directly from read.cJan Beulich6-0/+20
Make this a proper obj-format hook instead.
2024-10-04gas: drop unused fields from struct emulationJan Beulich6-60/+0
Neither .match not .bfd_name appear to ever have been used in the last about 25 years. Purge them.
2024-09-27RISC-V: odd data padding vs mapping symbolsJan Beulich1-5/+5
Odd data padding has a $d label inserted at its beginning. When a $x... label is removed instead, a replacement is inserted after the padding. The same, however, needs to also happen when there's no $x to replace.
2024-09-27RISC-V: correct alignment directive handling for text sectionsJan Beulich2-17/+54
.insn or data emitted inside text sections can lead to positions not being at insn granularity. In such situations using alignment directives should reliably enforce the requested alignment. Specifically requests to align back to insn granularity may not be ignored (where, as a subcase thereof, the ordering of ".option norvc" and e.g. ".p2align 2" should not matter; so far the alignment directive needs to come first to have any effect). Similarly ahead of emitting NOPs alignment first needs to be forced back to insn granularity. The new testcases actually point out a corner case issue in the disassembler as well, which is being corrected at the same time: We don't want to print "0x" without any subsequent digits.
2024-09-27x86: optimize {,V}INSERTPS with certain immediatesJan Beulich1-0/+96
They are equivalent to simple moves or xors, which are up to 3 bytes shorter to encode (and maybe/likely also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0Jan Beulich1-0/+74
They, too, are equivalent to simple moves, which are up to 3 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACTPS with immediate 0Jan Beulich1-0/+36
They are equivalent to simple moves, which are up to 2 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-27x86: correct {,V}PEXTR{D,Q} optimizationJan Beulich1-0/+1
A possible relocation associated with a memory operand also needs moving.
2024-09-26x86 TLS relocation checksAlan Modra1-7/+8
Some configurations (eg. i386-bsd, i386-msdos) broke with the addition of the TLS relocation checking. The "x86_elf_abi undeclared" error has been fixed, but "gotrel defined but not used" remains. Fix that. Also invert the preprocessor test around lex_got to make it positive logic and remove the LEX_AT condition which is no longer necessary. (The only x86 config files defining LEX_AT also define TE_PE.)
2024-09-25RISC-V: Add Smrnmi extension csrs.Jiawei1-0/+4
This patch support Smrnmi extension[1], The csrs address can be find in[2]. [1] https://github.com/riscv/riscv-isa-manual/commit/35eb3948bf0b87c83fab5a7238bd68b6211faf62 [2] https://github.com/riscv/riscv-isa-manual/blob/smrnmi-1.0/src/priv-csrs.adoc bfd/ChangeLog: * elfxx-riscv.c: New extension. gas/ChangeLog: * NEWS: Add Smrnmi extension support. * config/tc-riscv.c (enum riscv_csr_class): New extension class. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. include/ChangeLog: * opcode/riscv-opc.h (CSR_MNSCRATCH): New csr. (CSR_MNEPC): Ditto. (CSR_MNCAUSE): Ditto. (CSR_MNSTATUS): Ditto. (DECLARE_CSR): New csr declarations.
2024-09-24x86: Enable TLS relocation check only for ELFH.J. Lu1-11/+11
Since TLS relocation check is ELF specific, enable it only for ELF. PR gas/32022 * config/tc-i386.c (x86_tls_error_type): Define only if OBJ_MAYBE_ELF or OBJ_ELF is defined. (x86_check_tls_relocation): Likewise. (x86_report_tls_error): Likewise. (i386_assemble): Check TLS relocations only if OBJ_MAYBE_ELF or OBJ_ELF is defined. (md_show_usage): Output -mtls-check= only if OBJ_MAYBE_ELF or OBJ_ELF is defined. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-23Fix compile time error introduced by ↵Nick Clifton1-2/+8
d774bf9b3623239a1cfa729afcf048a15da657d3 for non-ELF x86 targets
2024-09-23x86: Turn PLT32 to PC32 only for PC-relative relocationsH.J. Lu1-1/+10
commit 292676c15a615b5a95bede9ee91004d3f7ee7dfd Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Feb 13 13:44:17 2020 -0800 x86: Resolve PLT32 reloc aganst local symbol to section resolved PLT32 relocation against local symbol to section and commit 2585b7a5ce5830e60a089aa2316a329558902f0c Author: H.J. Lu <hjl.tools@gmail.com> Date: Sun Jul 19 06:51:19 2020 -0700 x86: Change PLT32 reloc against section to PC32 turned PLT32 relocation against section into PC32 relocation. But these transformations are valid only for PC-relative relocations. Add fx_pcrel check for PC-relative relocations when performing these transformations to keep PLT32 relocation in `movq $foo@PLT, %rax`. gas/ PR gas/32196 * config/tc-i386.c (tc_i386_fix_adjustable): Return fixP->fx_pcrel for PLT32 relocations. (i386_validate_fix): Turn PLT32 relocation into PC32 relocation only if fixp->fx_pcrel is set. * testsuite/gas/i386/reloc32.d: Updated. * testsuite/gas/i386/reloc64.d: Likewise. * testsuite/gas/i386/reloc32.s: Add PR gas/32196 test. * testsuite/gas/i386/reloc64.s: Likewise. ld/ PR gas/32196 * testsuite/ld-x86-64/plt3.s: New file. * testsuite/ld-x86-64/x86-64.exp: Run plt3. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-21x86: Add tls check in gasCui, Lili1-22/+416
Assembler shouldn't accept invalid TLS instructions, TLS relocations can only be used with specific instructions as specified in TLS psABI and linker issues an error when TLS relocations are used with wrong instructions or format. Since it is inconvenient for gcc to rely on linker to report errors, adding TLS check in the assembler stage so that gcc can know TLS errors earlier. gas/ChangeLog: PR gas/32022 * config.in: Regenerate. * config/tc-i386.c *(enum x86_tls_error_type): New. *(struct _i386_insn): Added has_gotrel to indicate whether TLS relocations need to be checked. (x86_check_tls_relocation): Added a new function to check TLS relocation. (x86_report_tls_error): Created a new function to report TLS error. (i386_assemble): Handle x86_check_tls_relocation. (lex_got): Set i.has_gotrel. (OPTION_MTLS_CHECK): Added a new option to contrl TLS check. (struct option): Ditto. (md_parse_option): Ditto. (md_show_usage): Ditto. * configure.ac: Added a new option to check TLS relocation by default. * configure: Regenerated. * doc/c-i386.texi: Document -mtls-check=. * testsuite/gas/i386/i386.exp: Added new tests. * testsuite/gas/i386/ilp32/ilp32.exp: Ditto. * testsuite/gas/i386/ilp32/reloc64.d: Disable TLS check for it. * testsuite/gas/i386/ilp32/x32-tls.d: Ditto. * testsuite/gas/i386/inval-tls.l: Added more test cases. * testsuite/gas/i386/inval-tls.s: Ditto. * testsuite/gas/i386/reloc32.d: Disable TLS check for it. * testsuite/gas/i386/reloc64.d: Ditto. * testsuite/gas/i386/x86-64-inval-tls.l: Added more test cases. * testsuite/gas/i386/x86-64-inval-tls.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added new tests. * testsuite/gas/i386/ilp32/x32-inval-tls.l: New test. * testsuite/gas/i386/ilp32/x32-inval-tls.s: Ditto. * testsuite/gas/i386/ilp32/x86-64-tls.d: Ditto. * testsuite/gas/i386/tls.d: Ditto. * testsuite/gas/i386/tls.s: Ditto. * testsuite/gas/i386/x86-64-tls.d: Ditto. * testsuite/gas/i386/x86-64-tls.s: Ditto. ld/ChangeLog: PR gas/32022 * testsuite/ld-i386/tlsgdesc1.d: Disable TLS check for it. * testsuite/ld-i386/tlsgdesc2.d: Ditto. * testsuite/ld-i386/tlsie2.d: Ditto. * testsuite/ld-i386/tlsie3.d: Ditto. * testsuite/ld-i386/tlsie4.d: Ditto. * testsuite/ld-i386/tlsie5.d: Ditto. * testsuite/ld-i386/tlsgdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc4.d: Ditto. * testsuite/ld-x86-64/tlsie2.d: Ditto. * testsuite/ld-x86-64/tlsie3.d: Ditto. * testsuite/ld-x86-64/tlsie5.d: Ditto. * testsuite/ld-x86-64/tlsdesc5.d: Ditto.
2024-09-20x86-64: Never make R_X86_64_GOT64 section relativeH.J. Lu1-0/+1
R_X86_64_GOT64 relocation should never be made section relative. Change tc_i386_fix_adjustable to return 0 for BFD_RELOC_X86_64_GOT64. gas/ PR gas/32189 * config/tc-i386.c (tc_i386_fix_adjustable): Return 0 for BFD_RELOC_X86_64_GOT64. * testsuite/gas/i386/reloc64.d: Updated. * testsuite/gas/i386/reloc64.s: Add more tests for R_X86_64_GOT64 and R_X86_64_GOTOFF64. ld/ PR gas/32189 * testsuite/ld-x86-64/x86-64.exp: Run PR gas/32189 test. * testsuite/ld-x86-64/pr32189.s: New file. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
generated by cgit v1.1 at 2025-09-19 03:25:38 +0000