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Adjust parsing for AARCH64_OPND_SVE_ADDR_RR{_LSL*} operands to accept
implicit XZR offsets. Add new AARCH64_OPND_SVE_ADDR_RM{_LSL*} operands
to support instructions where an XZR offset is allowed but must be
specified explicitly. This allows the removal of the duplicate opcode
table entries using AARCH64_OPND_SVE_ADDR_R.
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The fix for PR22988 in 2018 added a new operand AARCH64_OPND_SVE_ADDR_R
to support implicit XZR offsets, but this fix had several flaws that
meant it accepted several invalid addressing modes:
1. The base register type wasn't properly checked when the optional
register offset was omitted. This meant that
ldff1b {z1.s}, p1/z,[z1.d]
was parsed as if it were
ldff1b z1.d, p1/z, [x1.d, xzr].
2. The explicit offset parsing didn't include a shift type, so the new
operand would incorrectly parse
ldff1h{z0.s}, p0/z, [x0, x0]
as if it were
ldff1h{z0.s}, p0/z, [x0, x0, lsl #1].
3. Regardless of the above correctness issues, support for implicit
offsets should have been added by amending the operands in the existing
opcode table entries, instead of adding new duplicate table entires.
Issue 1 can be fixed by using an "if" instead of an "else if" in
parse_operands, while issue 2 can be fixed by failing when the first
condition is false. This patch applies just these two fixes, leaving
issue 3 to be addressed in a subsequent more invasive patch.
The instructions removed from the test sme-5.d are architecturally
invalid. The new tests cover all of the affected ldff1 variants; the
issue also affected SME ZA ld1*/st1* instructions using the same operand
type.
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This patch support RISC-V Privileged Architecture 1.13 CSRs 'medelegh' and
'hedelegh'. More details between 1.12 and 1.13 see [1].
[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv-preface.adoc
Version log: Remove gas/po changes.
bfd/ChangeLog:
* cpu-riscv.c: New option.
* cpu-riscv.h (enum riscv_spec_class): Ditto.
binutils/ChangeLog:
* doc/binutils.texi: New option.
gas/ChangeLog:
* NEWS: Add priv-1.13 support.
* config/tc-riscv.c: New option.
* configure: Ditto.
* configure.ac: Ditto.
* testsuite/gas/riscv/csr-version-1p10.d: New CSR.
* testsuite/gas/riscv/csr-version-1p10.l: New warning.
* testsuite/gas/riscv/csr-version-1p11.d: New CSR.
* testsuite/gas/riscv/csr-version-1p11.l: New warning.
* testsuite/gas/riscv/csr-version-1p12.d: New CSR.
* testsuite/gas/riscv/csr-version-1p12.l: New warning.
* testsuite/gas/riscv/csr.s: New CSR.
* testsuite/gas/riscv/attribute-15.d: New test.
* testsuite/gas/riscv/attribute-16.d: New test.
* testsuite/gas/riscv/csr-version-1p13.d: New test.
* testsuite/gas/riscv/csr-version-1p13.l: New test.
include/ChangeLog:
* opcode/riscv-opc.h (CSR_MEDELEGH): New CSR.
(CSR_HEDELEGH): Ditto.
(DECLARE_CSR): Ditto.
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Spec:
https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf
Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp
with verison 1.0.
Passed binutils testsuites of targets elf32/elf64/linux32/linux64.
Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com>
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
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as_bad() already emits a newline; having extra ones leads to somewhat
distorted diagnostics.
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Both as_bad() and as_warn() already emit a newline; having extra ones
leads to somewhat distorted diagnostics.
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It's unclear why the array part of the union was used there, when we're
dealing with a function. Originally, when 32-bit hosts and targets were
prevailing, the memset() in question ended up clearing the entire x_fcn,
while for 64-bit hosts/targets only x_lnnoptr would have been cleared.
Then a2c7ca15a560 ("Use stdint types in coff internal_auxent") made
things consistent, but imo in the wrong direction (and likely
unintentionally). Go back to what apparently was meant originally, using
the correct part of the union now.
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For one at least x86 gcc emits .def/.endef for functions, but no 2nd
pair to designate their ends (sizes). While we can't recover the sizes,
we can at least properly establish the chain of function symbols, which
of course requires to emit auxiliary symbols for every function symbol
even when there's no C_EFCN: We simply shouldn't be making their
insertion conditional upon there not being a function processing of
which is "in progress".
In fact it was wrong to assign dual purpose to {,next_}set_end:
Functions don't have "ends" set, but links to the next one. The same
symbol table entry can serve both as an end marker and be a part of the
chain of (defined) functions; this can't be expressed by a single static
variable. Use what (again) becomes last_functionP for this purpose,
along with tracking what symbol C_EFCN should apply to.
This then allows to undo exposing of the respective (supposedly static)
tracking variable, which PPC's XCOFF handling had introduced. Also
rename it back to what it was before its exposure.
For now the new testcases are XFAIL for Arm64 since there, unlike for
Arm32, mapping symbols are emitted for COFF, too.
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There's no reason to reject this common COFF directive when it doesn't
have any other meaning.
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gas/config/
* tc-aarch64.c (aarch64_sframe_get_abi_arch): Fix typo in
comment on SFrame identifier.
* tc-aarch64.h (aarch64_sframe_get_abi_arch,
sframe_get_abi_arch): Likewise.
* tc-i386.c (x86_sframe_get_abi_arch): Likewise.
* tc-i386.h (x86_sframe_get_abi_arch, sframe_get_abi_arch):
Likewise.
Reported-by: Indu Bhagat <indu.bhagat@oracle.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Seen on x86_64-linux Ubuntu 24.04.2 using gcc-13.3.0 with
CFLAGS="-m32 -g -O2 -fsanitize=address,undefined"
In function ‘sprintf’,
inlined from ‘s_mri_for’ at gas/config/tc-m68k.c:6941:5:
/usr/include/bits/stdio2.h:30:10: error: null destination pointer [-Werror=format-overflow=]
30 | return __builtin___sprintf_chk (__s, __USE_FORTIFY_LEVEL - 1,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
31 | __glibc_objsize (__s), __fmt,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
32 | __va_arg_pack ());
| ~~~~~~~~~~~~~~~~~
Rewrite the code without sprintf, as in other parts of s_mri_for.
See also commit 760fb390fd4c and following commits.
Note that adding -D_FORTIFY_SOURCE=0 to CFLAGS (which is a good idea
when building with sanitizers) merely transforms the sprintf_chk error
here into one regarding plain sprintf.
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The test added in commit 4fe96ddaf614 results in an asan complaint:
loongarch-parse.y:225:16: runtime error: left shift of negative value -1
To avoid the complaint, perform left shifts as unsigned (which gives
the same result on 2's complement machines). Do the same for
addition, subtraction and multiplication. Furthermore, warn on
divide/modulus by zero.
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So far IBM z17 was identified as arch15. Add the real name, as it has
been announced. [1]
[1]: IBM z17 announcement letter, AD25-0015,
https://www.ibm.com/docs/en/announcements/z17-makes-more-possible
gas/
* config/tc-s390.c (s390_parse_cpu): Add z17 as alternate CPU
name for arch15.
* doc/c-s390.texi: Likewise.
* doc/as.texi: Likewise.
opcodes/
* s390-mkopc.c (main): Add z17 as alternate CPU name for arch15.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The GNU Assembler User Guide says that the right shift operator ">>"
in an expression is the same as the C operator.
On LoongArch the assembler directives and instructions do not treat
negative numbers ">>" the same way. The directives treats negative
numbers ">>" as logical right shifts while the instructions treats them
as arithmetic right shifts.
The right shift of negative numbers in the instructions may be changed
from an arithmetic right shift to a logical right shift in the future,
and a warning is issued for this.
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Like ELF for all symbols, COFF can record size for at least function
ones. Use that - if available - in preference to the distance-to-next-
symbol heuristic.
To be able to use the new test there, make TI C54x follow TI C4x in
providing .sdef to cover for .def already having different meaning.
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Instruction templates with only sign-extended 8-bit immediate operand
also have a second template with full-operand-size immediate operand
under a different opcode. Add {noimm8s} pseudo prefix to exclude
templates with only sign-extended 8-bit immediate operand.
gas/
PR gas/32811
* config/tc-i386.c (pseudo_prefixes): Add no_imm8s.
(operand_size_match): Return false for templates with only sign-
extended 8-bit immediate operand if {noimm8s} is used.
(parse_insn): Handle Prefix_NoImm8s.
* doc/c-i386.texi: Document {noimm8s}.
* testsuite/gas/i386/pseudos.s: Add tests for {noimm8s}.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
* testsuite/gas/i386/pseudos.d: Updated.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
opcodes/
PR gas/32811
* opcodes/i386-opc.h (Prefix_NoImm8s): New.
* i386-opc.tbl: Add {noimm8s} pseudo prefix.
* i386-mnem.h: Regenerated.
* i386-tbl.h: Likewise.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
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Since we will support 512 bit on both P-core and E-core for AVX10, 256 bit
rounding is not that useful because we currently have rounding feature
directly on E-core now and no need to use 256-bit rounding as somehow
a workaround. This patch will remove all the support and backport to
Binutils 2.44.
gas/ChangeLog:
* NEWS: Mention support removal.
* config/tc-i386.c (build_evex_prefix): Remove U bit encode.
(check_VecOperands): Remove ymm check for rounding.
(s_insn): Revise .insn comment.
* testsuite/gas/i386/avx10_2-256-cvt-intel.d: Remove ymm
rounding related test.
* testsuite/gas/i386/avx10_2-256-cvt.d: Ditto.
* testsuite/gas/i386/avx10_2-256-cvt.s: Ditto.
* testsuite/gas/i386/avx10_2-256-miscs-intel.d: Ditto.
* testsuite/gas/i386/avx10_2-256-miscs.d: Ditto.
* testsuite/gas/i386/avx10_2-256-miscs.s: Ditto.
* testsuite/gas/i386/avx10_2-256-satcvt-intel.d: Ditto.
* testsuite/gas/i386/avx10_2-256-satcvt.d: Ditto.
* testsuite/gas/i386/avx10_2-256-satcvt.s: Ditto.
* testsuite/gas/i386/evex.d: Ditto.
* testsuite/gas/i386/evex.s: Ditto.
* testsuite/gas/i386/i386.exp: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-cvt-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-cvt.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-cvt.s: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-miscs-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-miscs.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-miscs.s: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-satcvt-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-satcvt.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-satcvt.s: Ditto.
* testsuite/gas/i386/x86-64-evex.d: Ditto.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/avx10_2-rounding-intel.d: Removed.
* testsuite/gas/i386/avx10_2-rounding-inval.l: Removed.
* testsuite/gas/i386/avx10_2-rounding-inval.s: Removed.
* testsuite/gas/i386/avx10_2-rounding.d: Removed.
* testsuite/gas/i386/avx10_2-rounding.s: Removed.
* testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Removed.
* testsuite/gas/i386/x86-64-avx10_2-rounding.d: Removed.
* testsuite/gas/i386/x86-64-avx10_2-rounding.s: Removed.
opcodes/ChangeLog:
* i386-dis.c (struct instr_info): Remove U bit.
(get_valid_dis386): Roll back to APX condition.
* i386-opc.tbl: Remove ymm rounding support.
* i386-tbl.h: Regenerated.
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The original observation was that STILP is warned about when everything
is fine. Documentation, not just for STILP, says explicitly that
behavior is identical to respective pre-existing insns (for STILP in
particular that's STP). With that it's unclear why distinct logic was
added: Other code can be re-used, simply distinguishing by the number of
operands. This was diagnostics also end up more consistent.
Along with adding some STILP uses to the (positive) testcase, also add a
pair of STLR to similarly demonstrate that the register overlap goes
without warning when there's no write-back.
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Since we now always generate $x+isa for now, these would increase the
dis-assemble time by parsing the same architecture string repeatedly. We
already have `arch_str' field into `subset_list' to record the current
architecture stirng, but it's only useful for assembler, since dis-assembler
and linker don't need it before. Now for dis-assembler, we just need to
update the `arch_str' after parsing the architecture stirng, and then avoid
parsing repeatedly if the strings are the same.
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These are data generating directives not overly different from e.g.
.byte and .long. Whatever (directly) results from should also be
represented in the listing, if one was requested. It's just that the
output data is generated much later than the parsing of the directive
arguments.
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The prologue generated by __gcc_isr can be improved in
situations where:
* ZERO_REG is needed, and
* SREG is not clobbered by the ISR, and
* avr-gcc provides a GPR >= R16 with the Done chunk, and
* Code generation is for ordinary AVRs (not AVRrc).
For example, the prologue for
volatile char var;
__attribute__((signal)) void __vector_1 (void)
{
var = 1;
var = 0;
}
may be
00000000 <__vector_1>:
0: 8f 93 push r24
2: 1f 92 push r1
4: 80 e0 ldi r24, 0
6: 18 2e mov r1, r24
instead of the code as currently generated by GAS:
00000000 <__vector_1>:
0: 1f 92 push r1
2: 1f b6 in r1, SREG
4: 1f 92 push r1
6: 11 24 clr r1
8: 8f 93 push r24
which consumes more stack, time and code than needed.
gas/
PR gas/32704
PR gas/21683
* config/tc-avr.c (avr_isr): bool-ize.
(avr_emit_insn): Emit "mov" code as MOV R1,<reg>.
(avr_isr_stack_t): New typedef.
(avr_emit_push, avr_emit_pop): New static functions.
(avr_patch_gccisr_frag): Overhaul prologue and epilogue
generation.
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Besides it being somewhat off to have three decls scattered across the
code base, it is generally bad practice for the definition of a symbol
to not also observe its declaration (making sure the two won't go out of
sync).
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PR gas/32721
In this bogus piece of code distilled from fuzzing and slightly edited:
A=%eax|%!
Y=A
Z=A
or $6,Z
the first of the equates with A on the rhs changes A's section (due to
the use of S_GET_VALUE()), from expression to register, thus yielding Y
in the expression section (and X_op being O_symbol), but Z in the
register section (and X_op being O_register with X_add_value being -1).
There shouldn't be random O_register expressions, though, for targets
setting md_register_arithmetic to false. Plus both Y and Z would better
be exchangeable.
In pseudo_set() wire handling of O_symbol expressions referencing a
symbol in the expression section to that of other stuff ending up in
this section.
Also avoid bogus O_register expressions to be created, for targets
setting md_register_arithmetic to false: S_GET_VALUE() would resolve
any arithmetic, which must not happen for such targets. To be on the
safe side for such targets, also amend resolve_register(). Correct
another earlier oversight there too (affecting at least Z80), by using
the new expr_copy() helper there as well.
Undo 46b9f07dfe79 ("PR 32721, internal error in
tc-i386.c:parse_register"), albeit without losing the simplification it
did.
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... by way of introducing LEX_EOL and LEX_EOS. As a prereq convert the
remaining open-coded accesses.
The Alpha change is actually a functional one: The array slot for '!'
having been set to 1 is very unlikely to have been correct. 1 means "end
of line", when surely "end of statement" was always meant.
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With the switch to the use of is_end_of_stmt() in 2dd0370c433d
("rl78: use is_whitespace()") the open-coded checking against
line_separator_chars[] can be dropped.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it. This also fixes two array underrun
issues, when plain char is a signed type.
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... instead of open-coding it. Also convert a variable to plain char
(allowing to drop two casts), which is how it's actually used.
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... instead of open-coding it. Also convert a variable to plain char
(allowing to drop two casts), which is how it's actually used.
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... instead of open-coding it.
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... instead of open-coding it.
In tic54x_stringer() this also fixes an array overrun issue: Converting
plain char to unsigned int could have yielded huge values when plain
char is a signed type.
In subsym_substitute() also convert a local variable to plain char, as
that's what it's really holding (and how it's used everywhere else).
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it. This also fixes two array underrun
issues, when plain char is a signed type.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it. With this there's no need for op_end (and
hence op_start) to be other than pointer to plain char. Which in turn
eliminates the need for several questionable casts.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it.
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... instead of open-coding it.
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