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Any open sequence at the end of a section or assembly is considered an error.
This patch adds a check at the end to ensure that all sequences have been closed
and if not reports a warning.
During disassembly it's not possible to detect this condition in the back-end so
the warning is only emitted from the assembler for now.
gas/
* config/tc-aarch64.c (force_automatic_sequence_close,
aarch64_frob_section): New.
* config/tc-aarch64.h (tc_frob_section, aarch64_frob_section): New.
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This patch adds the verification rules for move prefix constraints.
The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at
PC+4. Particularly the following constraints are handled by this patch
* MOVPRFX must be followed by an instruction.
* MOVPRFX can only be followed by non-layout altering directives.
* MOVPRFX destination register MUST be used as the destination register in the
instruction at PC+4, and is not allowed to be used in any other position other than
destructive input. This includes registers that architecturally overlap. e.g. x1
should be treated as z1.
* MOVPRFX must be followed by a restricted set of SVE instructions.
* The size of the destination register of MOVPRFX must be equal to that of
the operation at PC+4.
* The predicate register and operation of MOVPRFX must match that of the instruction
at PC+4
* The predicated instruction at PC+4 must use the merging predicate.
* Architectural aliases and pseudo-instructions need to be supported as well.
* MOVPRFX cannot be the last instruction in a sequence
Any failure to adhere to any of these constrains will emit an assembly warning
and a disassembly note.
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (aarch64_inst): Remove.
(enum err_type): Add ERR_VFI.
(aarch64_is_destructive_by_operands): New.
(init_insn_sequence): New.
(aarch64_decode_insn): Remove param name.
opcodes/
* aarch64-opc.c (init_insn_block): New.
(verify_constraints, aarch64_is_destructive_by_operands): New.
* aarch64-opc.h (verify_constraints): New.
gas/
* config/tc-aarch64.c (output_operand_error_report): Order warnings.
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This patch introduces aarch64_instr_sequence which is a structure similar to IT
blocks on Arm in order to track instructions that introduce a constraint or
dependency on instruction 1..N positions away from the instruction that opened
the block.
The struct is also wired through to the locations that require it.
gas/
* config/tc-aarch64.c (now_instr_sequence):
(*insn_sequence, now_instr_sequence): New.
(output_operand_error_record, do_encode): Add insn_sequence.
(md_assemble): Update insn_sequence.
(try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn):
Pass insn_sequence.
* config/tc-aarch64.h (struct aarch64_segment_info_type):
Add insn_sequence.
include/
* opcode/aarch64.h (struct aarch64_instr_sequence): New.
(aarch64_opcode_encode): Use it.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
* aarch64-dis.c (insn_sequence): New.
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Increase the fixup length to 4 for the 20 bit displacement.
gas/ChangeLog:
2018-09-25 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (md_apply_fix): Set fx_size to 4 for 20 bit
displacements.
* testsuite/gas/s390/s390.exp: Run new test.
* testsuite/gas/s390/zarch-z990-symbol-lay.s: New test.
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Fix a build error:
cc1: warnings being treated as errors
.../gas/config/tc-s12z.c: In function 'lex_opr':
.../gas/config/tc-s12z.c:617: warning: comparison between signed and unsigned
.../gas/config/tc-s12z.c:624: warning: comparison between signed and unsigned
make[4]: *** [config/tc-s12z.o] Error 1
observed with GCC 4.1.2 with the `s12z-elf' target.
Here we have a constant assembly instruction operand, whose value is
within the 24-bit unsigned range, to be placed in a machine instruction
such as to use the least space-consuming encoding. So the sign of that
value does not matter, because signed values are out of range and are
not supposed to appear here, and we only have this warning here because
the `X_add_number' member of `struct expressionS' is of the `offsetT'
type, which is signed.
Use an auxiliary variable of an unsigned data type then, observing that
both `offsetT' and `valueT' have the same width, as they correspond to
`bfd_signed_vma' and `bfd_vma' respectively.
gas/
* config/tc-s12z.c (lex_opr): Use an auxiliary unsigned variable
in encoding a constant operand.
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Fix a build error:
cc1: warnings being treated as errors
.../gas/config/tc-ppc.c: In function 'ppc_dwsect':
.../gas/config/tc-ppc.c:4091: warning: comparison between signed and unsigned
make[4]: *** [config/tc-ppc.o] Error 1
observed with GCC 4.1.2 with the `powerpc-beos' target.
Here `flag' identifies the type of a DWARF section, as used with the the
first operand to the `.dwsect' pseudo-op, and has no notion of a sign,
or for that matter being arithmetic in the first place[1]. We already
handle this correctly with the `flag' member of the `xcoff_dwsect_name'
structure, however not in the local variable used in GAS to hold the
parsed value of said `.dwsect' pseudo-op's operand.
Use an unsigned data type in GAS then too, observing that both `offsetT'
and `valueT' have the same width, as they correspond to `bfd_signed_vma'
and `bfd_vma' respectively.
References:
[1] "AIX Version 7.2: Assembler Language Reference", IBM Corporation
2015, 2018, Section ".dwsect pseudo-op", pp. 531-532
gas/
* config/tc-ppc.c (ppc_dwsect): Use `valueT' rather than
`offsetT' as the type of `flag'.
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Fix build errors:
cc1: warnings being treated as errors
In file included from .../opcodes/arc-opc.c:2630:
.../opcodes/arc-nps400-tbl.h:38: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:38: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:41: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:41: warning: integer constant is too large for 'long' type
[...]
.../opcodes/arc-nps400-tbl.h:712: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:712: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:715: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:715: warning: integer constant is too large for 'long' type
make[4]: *** [arc-opc.lo] Error 1
and:
cc1: warnings being treated as errors
.../gas/config/tc-arc.c: In function 'md_number_to_chars_midend':
.../gas/config/tc-arc.c:802: warning: integer constant is too large for 'long' type
.../gas/config/tc-arc.c:810: warning: integer constant is too large for 'long' type
make[4]: *** [config/tc-arc.o] Error 1
observed with GCC 4.1.2 and presumably other C89 compilers with the
`arc-elf' and `arc-linux-gnu' targets, caused by the use of constants
the values of which are outside the range of the `int' type (or the
`long' type if it is of the same with). In the C89 language standard
such constants are not implicitly converted to a wider type and an
explicit suffix is required for such constants.
Add a `ull' suffix then as with such constants used in other ports.
gas/
* config/tc-arc.c (md_number_to_chars_midend): Append `ull' to
large constants.
opcodes/
* arc-nps400-tbl.h: Append `ull' to large constants throughout.
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binutils on upstream!
We have not only removed all unsupported and obsolete code, but also supported lost of new features,
including better link-time relaxations and TLS implementations. Besides, the files generated by the
newly assembler and linker usually get higher performance and more optimized code size.
ld * emultempl/nds32elf.em (hyper_relax): New variable.
(nds32_elf_create_output_section_statements):
the parameters of bfd_elf32_nds32_set_target_option
(PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax.
* emultempl/nds32elf.em (nds32_elf_after_open): Updated.
* emultempl/nds32elf.em (tls_desc_trampoline): New variable.
* (nds32_elf_create_output_section_statements): Updated.
* (nds32_elf_after_parse): Disable relaxations when PIC is enable.
* (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline.
include * elf/nds32.h: Remove the unused target features.
* dis-asm.h (disassemble_init_nds32): Declared.
* elf/nds32.h (E_NDS32_NULL): Removed.
(E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
* opcode/nds32.h: Ident.
(N32_SUB6, INSN_LW): New macros.
(enum n32_opcodes): Updated.
* elf/nds32.h: Doc fixes.
* elf/nds32.h: Add R_NDS32_LSI.
* elf/nds32.h: Add new relocations for TLS.
gas * config/tc-nds32.c: Remove the unused target features.
(nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp,
nds32_set_elf_flags_by_insn, nds32_insert_relax_entry,
nds32_apply_fix): Likewise.
(nds32_no_ex9_begin): Removed.
* config/tc-nds32.c (add_mapping_symbol_for_align,
make_mapping_symbol, add_mapping_symbol): New functions.
* config/tc-nds32.h (enum mstate): New.
(nds32_segment_info_type): Likewise.
* configure.ac (--enable-dsp-ext, --enable-zol-ext): New options.
* config.in: Regenerated.
* configure: Regenerated.
* config/tc-nds32.c (nds32_dx_regs):
Set the value according to the configuration.
(nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext):
Likewise.
(nds32_dsp_ext): New variable. Set the value according to the
configuration.
(nds32_zol_ext): Likewise.
(asm_desc, nds32_pseudo_opcode_table): Make them static.
(nds32_set_elf_flags_by_insn): Updated.
(nds32_check_insn_available): Updated.
(nds32_str_tolower): New function.
* config/tc-nds32.c (relax_table): Updated.
(md_begin): Updated.
(md_assemble): Use XNEW macro to allocate space for `insn.info',
and then remember to free it.
(md_section_align): Cast (-1) to ValueT.
(nds32_get_align): Cast (~0U) to addressT.
(nds32_relax_branch_instructions): Updated.
(md_convert_frag): Add new local variable `final_r_type'.
(invalid_prev_frag): Add new bfd_boolean parameter `relax'.
All callers changed.
* config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field.
(struct nds32_hint_map): Add `option_list' field.
(struct suffix_name, suffix_table): Remove the unused `pic' field.
(do_pseudo_b, do_pseudo_bal): Remove the suffix checking.
(do_pseudo_la_internal, do_pseudo_pushpopm): Indent.
(relax_hint_bias, relax_hint_id_current): New static variables.
(reset_bias, relax_hint_begin): New variables.
(nds_itoa): New function.
(CLEAN_REG, GET_OPCODE): New macros.
(struct relax_hint_id): New.
(nds32_relax_hint): For .relax_hint directive, we can use `begin'
and `end' to mark the relax pattern without giving exactly id number.
(nds32_elf_append_relax_relocs): Handle the case that the .relax_hint
directives are attached to pseudo instruction.
(nds32_elf_save_pseudo_pattern): Change the second parameter from
instruction's opcode to byte code.
(nds32_elf_build_relax_relation): Add new bfd_boolean parameter
`pseudo_hint'.
(nds32_lookup_pseudo_opcode): Fix the overflow issue.
(enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT.
(nds32_elf_record_fixup_exp, relax_ls_table, hint_map,
nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name):
Updated.
* config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6.
(enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and
NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add
NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and
NDS32_RELAX_HINT_LA_GOTOFF.
* config/tc-nds32.h (relax_ls_table): Add floating load/store
to gp relax pattern.
(hint_map, nds32_find_reloc_table): Likewise.
* configure.ac: Define NDS32_LINUX_TOOLCHAIN.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-nds32.h (enum nds32_ramp): Updated.
(enum nds32_relax_hint_type): Likewise.
* config/tc-nds32.c: Include "errno.h" and "limits.h".
(relax_ls_table): Add TLS relax patterns.
(nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on
each instructions of TLS patterns.
(nds32_elf_record_fixup_exp): Updated.
(nds32_apply_fix): Likewise.
(suffix_table): Add TLSDESC suffix.
binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number
from 215 to 255 for NDS32.
bfd * elf32-nds32.c (nds32_elf_relax_loadstore):
Remove the unused target features.
(bfd_elf32_nds32_set_target_option): Remove the unused parameters.
(nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12,
nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls,
nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff
nds32_elf_relax_gotoff_suff, calculate_plt_memory_address,
calculate_plt_offset, calculate_got_memory_address,
nds32_elf_check_dup_relocs): Removed.
All callers changed.
* elf32-nds32.h: Remove the unused macros and defines.
(elf_nds32_link_hash_table): Remove the unused variable.
(bfd_elf32_nds32_set_target_option): Update prototype.
(nds32_elf_ex9_init): Removed.
* elf32-nds32.c (nds32_convert_32_to_16): Updated.
* elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros
to initialize array nds32_elf_howto_table in any order
without lots of EMPTY_HOWTO.
(nds32_reloc_map): Updated.
* reloc.c: Add BFD_RELOC_NDS32_LSI.
* bfd-in2.h: Regenerated.
* bfd/libbfd.h: Regenerated.
* elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI.
(nds32_reloc_map): Likewise.
(nds32_elf_relax_flsi): New function.
(nds32_elf_relax_section): Support floating load/store relaxation.
* elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset):
New macro.
(struct elf_nds32_link_hash_entry): New `offset_to_gp' field.
(struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields.
(elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard,
nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym):
New functions.
(nds32_info_to_howto_rel): Add BFD_ASSERT.
(bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc,
nds32_elf_link_hash_table_create, nds32_elf_relocate_section,
nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label,
bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated.
(nds32_elf_final_sda_base): Improve it to find the better gp value.
(insert_nds32_elf_blank): Must consider `len' when inserting blanks.
* elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype.
(struct elf_nds32_link_hash_table): Add new variable `hyper_relax'.
* elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function.
(create_got_section): Likewise.
(allocate_dynrelocs, nds32_elf_size_dynamic_sections,
nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated.
(nds32_elf_check_relocs): Fix the issue that the shared library may
has TEXTREL entry in the dynamic section.
(nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs
since the TEXTREL issue is fixed in the nds32_elf_check_relocs.
(nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ
dynamic entry.
(calculate_offset): Remove the unused parameter `pic_ext_target' and
related codes.
All callers changed.
(elf_backend_dtrel_excludes_plt): Disable it temporarily since it
will cause some errors for our test cases.
* elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the
generic object.
* reloc.c: Add TLS relocations.
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* elf32-nds32.h (struct section_id_list_t): New.
(elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model):
New prototypes.
(elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent):
New macro.
(nds32_insertion_sort, bfd_elf32_nds32_set_target_option,
elf_nds32_link_hash_table): Updated.
* elf32-nds32.c (enum elf_nds32_tls_type): New.
(struct elf32_nds32_relax_group_t, struct relax_group_list_t): New.
(elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type,
fls, ones32, list_insert, list_insert_sibling, dump_chain,
elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions.
(elf_nds32_obj_tdata): Add new fields.
(elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros.
(nds32_elf_howto_table): Add TLS relocations.
(nds32_reloc_map): Likewise.
(nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections,
nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info,
nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option,
nds32_elf_check_relocs, allocate_dynrelocs): Updated.
(nds32_elf_relax_section): Call nds32_elf_unify_tls_model.
(dtpoff_base): Rename it to `gottpof' and then update it.
opcodes * nds32-asm.c (operand_fields): Remove the unused fields.
(nds32_opcodes): Remove the unused instructions.
* nds32-dis.c (nds32_ex9_info): Removed.
(nds32_parse_opcode): Updated.
(print_insn_nds32): Likewise.
* nds32-asm.c (config.h, stdlib.h, string.h): New includes.
(LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
(nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
build_opcode_hash_table): New functions.
(nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
nds32_opcode_table): New.
(hw_ktabs): Declare it to a pointer rather than an array.
(build_hash_table): Removed.
* nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
SYN_ROPT and upadte HW_GPR and HW_INT.
* nds32-dis.c (keywords): Remove const.
(match_field): New function.
(nds32_parse_opcode): Updated.
* disassemble.c (disassemble_init_for_target):
Add disassemble_init_nds32.
* nds32-dis.c (eum map_type): New.
(nds32_private_data): Likewise.
(get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
(print_insn_nds32): Updated.
* nds32-asm.c (parse_aext_reg): Add new parameter.
(parse_re, parse_re2, parse_aext_reg): Only reduced registers
are allowed to use.
All callers changed.
* nds32-asm.c (keyword_usr, keyword_sr): Updated.
(operand_fields): Add new fields.
(nds32_opcodes): Add new instructions.
(keyword_aridxi_mx): New keyword.
* nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
and NASM_ATTR_ZOL.
(ALU2_1, ALU2_2, ALU2_3): New macros.
* nds32-dis.c (nds32_filter_unknown_insn): Updated.
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This fixes a small bug with the warning filtering code, which when a line has
generated a warning and a template decode error (due to the way templates are
resolved) which would not have been emitted and warnings are being suppressed
with -W it would erroneously emit the error.
I have no testcase for this because the only places we generate warnings during
encoding/decoding now is using msr/mrs and system registers. They don't have a
template that would trigger this.
However an upcoming patch series will have tests in it which would expose this bug.
gas/ChangeLog:
* config/tc-aarch64.c (output_operand_error_report): Apply filtering to
current instead of head message.
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Add -mvexwig=[0|1] option to x86 assembler to control how the assembler
should encode the VEX.W bit in WIG VEX instructions.
* gas/NEWS: Mention -mvexwig=[0|1] option.
* config/tc-i386.c (vexwig): New.
(build_vex_prefix): Set the VEX.W bit for -mvexwig=1 for WIG
VEX instructions.
(OPTION_MVEXWIG): New.
(md_longopts): Add -mvexwig=.
(md_parse_option): Handle OPTION_MVEXWIG.
(md_show_usage): Show -mvexwig=[0|1].
* doc/c-i386.texi: Document -mvexwig=[0|1].
* testsuite/gas/i386/avx-wig.d: New file.
* testsuite/gas/i386/avx-wig.s: Likewise.
* testsuite/gas/i386/avx2-wig.d: Likewise.
* testsuite/gas/i386/avx2-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.s: Likewise.
* testsuite/gas/i386/i386.exp: Run avx-wig, avx2-wig,
x86-64-avx-wig and x86-64-avx2-wig.
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Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is
ignored by such VEX/EVEX instructions, aka WIG instructions. Set
VexW=3 on VEX/EVEX WIG instructions. Update assembler to check
VEXWIG when setting the VEX.W bit.
gas/
PR gas/23642
* config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting
the VEX.W bit.
(build_evex_prefix): Check VEXWIG when setting the EVEX.W bit.
opcodes/
PR gas/23642
* i386-opc.h (VEXWIG): New.
* i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
* i386-tbl.h: Regenerated.
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Define DIFF_EXPR_OK to Support PC relative diff relocation,
and add CKCORE_PCREL32 relocation process
bfd/
* elf32-csky.c (csky_elf_howto_table): Fill special_function of
R_CKCORE_PCREL32.
(csky_elf_relocate_section): Add R_CKCORE_PCREL32 process.
gas/
* config/tc-csky.c (md_apply_fix): Transmit
BFD_RELOC_32_PCREL to BFD_RELOC_CKCORE_PCREL32.
(tc_gen_reloc): Trasmit BFD_RELOC_CKCORE_ADDR32 to
BFD_RELOC_CKCORE_PCREL32 while pc-relative.
* config/tc-csky.h (DIFF_EXPR_OK): Define to enable PC relative
diff relocs.
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Just like other insns having byte and word forms, these can also make
use of the W modifier, which at the same time allows simplifying some
other code a little bit.
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When encoding VEX, we can swap destination and source only if there are
more than 1 register operand.
* config/tc-i386.c (build_vex_prefix): Swap destination and
source only if there are more than 1 register operand.
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For now this is just for VMOVS{D,S}.
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Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.
Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.
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In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
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Revert commit 8744470deab and instead use the standard special_sections
support.
PR 23570
bfd/
* elf32-avr.c (elf_avr_special_sections): New.
(elf_backend_special_sections): Define.
gas/
* config/tc-avr.c: Revert 2018-09-03 change.
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Sparc V8 does not allow fpop2 instructions (floating point
comparisons) immediately before floating point branches. From the
SPARC Architecture Manual Version 8, section B.22 "Branch on
Floating-point Condition Codes Instructions":
"If the instruction executed immediately before an FBfcc is an FPop2
instruction, the result of the FBfcc is undefined. Therefore, at
least one non FPop2 instruction should be executed between the FPop2
instruction and the FBfcc instruction."
The existing check in GAS, however, does not allow any kind of
floating point instruction before the branch. This patch adds an
extra condition to only disallow fpop2 instructions.
gas/ChangeLog:
2018-09-04 Daniel Cederman <cederman@gaisler.com>
* config/tc-sparc.c (md_assemble): Allow non-fpop2 instructions
before floating point branches for Sparc V8 and earlier.
* testsuite/gas/sparc/sparc.exp: Execute the new test.
* testsuite/gas/sparc/v8branch.d: New test.
* testsuite/gas/sparc/v8branch.s: New test.
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section is always given the ELF NOBITS section type.
PR gas/23570
* config/tc-avr.c (md_pseudo_table): Add entry for "secction".
(avr_set_section): New function. Ensures that the .noinit section
gets the NOBITS ELF section type.
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There are occasions where someone might want to build a 64-bit
pc-relative offset from 16-bit pieces. This adds the necessary REL16
relocs corresponding to existing ADDR16 relocs that can be used to
build 64-bit absolute values.
include/
* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA),
(BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA),
(BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA):
Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos.
(ppc64_elf_reloc_type_lookup): Translate new REL16 relocs.
(ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16
HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs.
Group 16-bit relocs.
* config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs
to REL16 when pcrel. Sort relocs.
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Add -mx86-used-note=[yes|no] option to generate (or not) GNU property
notes with GNU_PROPERTY_X86_FEATURE_2_USED and GNU_PROPERTY_X86_ISA_1_USED
properties. If the assembly input contains no instructions, set the
GNU_PROPERTY_X86_UINT32_VALID bit in GNU_PROPERTY_X86_FEATURE_2_USED
property. Add a --enable-x86-used-note configure time option to set the
default behavior. Set the default if the configure option is not used
to "no".
* NEWS: Mention -mx86-used-note=[no|yes].
* configure.ac: Add --enable-x86-used-note. Define
DEFAULT_X86_USED_NOTE.
* config.in: Regenerated.
* configure: Likewise.
* config/tc-i386.c (x86_isa_1_used): New.
(x86_feature_2_used): Likewise.
(x86_used_note): Likewise.
(_i386_insn): Add has_regmmx, has_regxmm, has_regymm and
has_regzmm.
(build_modrm_byte): Set i.has_regmmx, i.has_regzmm.
i.has_regymm and i.has_regxmm.
(x86_cleanup): New function.
(output_insn): Update x86_isa_1_used and x86_feature_2_used.
(OPTION_X86_USED_NOTE): New.
(md_longopts): Add -mx86-used-note=.
(md_parse_option): Handle OPTION_X86_USED_NOTE.
(md_show_usage): Display -mx86-used-note=.
* config/tc-i386.h (x86_cleanup): New prototype.
(md_cleanup): New.
* doc/c-i386.texi: Document -mx86-used-note=.
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2018-08-29 Kito Cheng <kito@andestech.com>
gas/
* config/tc-riscv.c (riscv_subset_supports): New argument:
xlen_required.
(riscv_multi_subset_supports): New function, able to check more
than one extension.
(riscv_ip): Use riscv_multi_subset_supports instead of
riscv_subset_supports.
(riscv_set_arch): Update call-site for riscv_subset_supports.
(riscv_after_parse_args): Likewise.
include/
*opcode/riscv.h (MAX_SUBSET_NUM): New.
(riscv_opcode): Add xlen_requirement field and change type of
subset.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
riscv_opcode.xlen_requirement.
* riscv-opc.c (riscv_opcodes): Update for struct change.
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bfd/
* archures.c (bfd_architecture): New machine
bfd_mach_mips_gs264e.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
(arch_info_struct): Likewise.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle
E_MIPS_MACH_GS264E.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Map bfd_mach_mips_gs264e to
bfd_mach_mips_gs464e extension.
binutils/
* NEWS: Mention Loongson 2K1000 proccessor support.
* readelf.c (get_machine_flags): Handle gs264e.
elfcpp/
* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.
gas/
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
(mips_cpu_info_table): Add gs264e descriptors.
* doc/as.texi (march table): Add gs264e.
include/
* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
* opcode/mips.h (CPU_XXX): New CPU_GS264E.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
gs264e and gs464e.
opcodes/
* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
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bfd/
* archures.c (bfd_architecture): New machine
bfd_mach_mips_gs464e.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
(arch_info_struct): Likewise.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle
E_MIPS_MACH_GS464E.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Map bfd_mach_mips_gs464e to
bfd_mach_mips_gs464 extension.
binutils/
* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
* readelf.c (get_machine_flags): Handle gs464e.
elfcpp/
* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.
gas/
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
(mips_cpu_info_table): Add gs464e descriptors.
* doc/as.texi (march table): Add gs464e.
include/
* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
* opcode/mips.h (CPU_XXX): New CPU_GS464E.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
gs464e and gs464.
opcodes/
* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
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bfd/
* archures.c (bfd_architecture): Rename
bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
(arch_info_struct): Likewise.
* elfxx-mips.c (_bfd_elf_mips_mach): Likewise.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Likewise.
(bfd_mips_isa_ext_mach): Likewise.
(bfd_mips_isa_ext): Likewise.
(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.
binutils/
* NEWS: Mention Loongson 3A1000 proccessor support.
* readelf.c (get_machine_flags): Rename loongson-3a to gs464.
(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.
elfcpp/
* mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to
E_MIPS_MACH_GS464.
gas/
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename
CPU_LOONGSON_3A to CPU_GS464.
(mips_cpu_info_table): Add gs464 descriptors, Keep
loongson3a as an alias of gs464 for compatibility.
* doc/as.texi (march table): Rename loongson3a to gs464.
* testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension"
flag to None.
gold/
* mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach):
Rename loongson3a to gs464.
(mips_isa_ext_mach, mips_isa_ext): Delete loongson3a.
(infer_abiflags): Use ases instead of isa_ext for infer ABI
flags.
(elf_mips_mach_name): Rename loongson3a to gs464.
include/
* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
E_MIPS_MACH_GS464.
(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
* opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
(CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
* opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a
to gs464.
opcodes/
* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
loongson3a as an alias of gs464 for compatibility.
* mips-opc.c (mips_opcodes): Change Comments.
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bfd/
* elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension.
binutils/
* readelf.c (print_mips_ases): Add Loongson EXT2 extension.
gas/
* NEWS: Mention Loongson EXTensions R2 (EXT2) support.
* config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and
OPTION_NO_LOONGSON_EXT2.
(md_longopts): Likewise.
(mips_ases): Define availability for EXT.
(mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to
AFL_ASE_LOONGSON_EXT2.
(md_show_usage): Add help for -mloongson-ext2 and
-mno-loongson-ext2.
* doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2.
* doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2,
.set loongson-ext2 and .set noloongson-ext2.
* testsuite/gas/mips/loongson-ext2.d: New test.
* testsuite/gas/mips/loongson-ext2.s: New test.
* testsuite/gas/mips/mips.exp: Run loongson-ext2 test.
include/
* elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
* opcode/mips.h (ASE_LOONGSON_EXT2): New macro.
opcodes/
* mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
option.
(print_mips_disassembler_options): Document -M loongson-ext.
* mips-opc.c (LEXT2): New macro.
(mips_opcodes): Add cto, ctz, dcto, dctz instructions.
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bfd/
* elfxx-mips.c (infer_mips_abiflags): Use ases instead of
isa_ext for infer ABI flags.
(print_mips_ases): Add Loongson EXT extension.
binutils/
* readelf.c (print_mips_ases): Add Loongson EXT extension.
elfcpp/
* mips.h (AFL_ASE_LOONGSON_EXT): New enum.
gas/
* NEWS: Mention Loongson EXTensions (EXT) support.
* config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and
OPTION_NO_LOONGSON_EXT.
(md_longopts): Likewise.
(mips_ases): Define availability for EXT.
(mips_convert_ase_flags): Map ASE_LOONGSON_EXT to
AFL_ASE_LOONGSON_EXT.
(mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a.
(md_show_usage): Add help for -mloongson-ext and
-mno-loongson-ext.
* doc/as.texi: Document -mloongson-ext, -mno-loongson-ext.
* doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext,
.set loongson-ext and .set noloongson-ext.
* testsuite/gas/mips/loongson-mmi.d: Add ASE flag.
include/
* elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
* opcode/mips.h (ASE_LOONGSON_EXT): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add EXT to loongson3a
descriptors.
(parse_mips_ase_option): Handle -M loongson-ext option.
(print_mips_disassembler_options): Document -M loongson-ext.
* mips-opc.c (IL3A): Delete.
* mips-opc.c (LEXT): New macro.
(mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
instructions.
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bfd/
* elfxx-mips.c (print_mips_ases): Add CAM extension.
binutils/
* readelf.c (print_mips_ases): Add CAM extension.
gas/
* NEWS: Mention Loongson Content Address Memory (CAM)
support.
* config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and
OPTION_NO_LOONGSON_CAM.
(md_longopts): Likewise.
(mips_ases): Define availability for CAM.
(mips_convert_ase_flags): Map ASE_LOONGSON_CAM to
AFL_ASE_LOONGSON_CAM.
(mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a.
(md_show_usage): Add help for -mloongson-cam and
-mno-loongson-cam.
* doc/as.texi: Document -mloongson-cam, -mno-loongson-cam.
* doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam,
.set loongson-cam and .set noloongson-cam.
* testsuite/gas/mips/loongson-3a-2.d: Move cam test to ...
* testsuite/gas/mips/loongson-cam.d: Here. Add ISA/ASE
flag verification.
* testsuite/gas/mips/loongson-3a-2.s: Move cam test to ...
* testsuite/gas/mips/loongson-cam.s: Here.
* testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag.
* testsuite/gas/mips/mips.exp: Run loongson-cam test.
include/
* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
* opcode/mips.h (ASE_LOONGSON_CAM): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
descriptors.
(parse_mips_ase_option): Handle -M loongson-cam option.
(print_mips_disassembler_options): Document -M loongson-cam.
* mips-opc.c (LCAM): New macro.
(mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
instructions.
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gas/
2018-08-23 Kito Cheng <kito@andestech.com>
* config/tc-riscv.c (arg_lookup): Checking
length before look up.
* testsuite/gas/riscv/fence-fail.d: New file.
* testsuite/gas/riscv/fence-fail.l: Likewise.
* testsuite/gas/riscv/fence-fail.s: Likewise.
* testsuite/gas/riscv/rouding-fail.d: Likewise.
* testsuite/gas/riscv/rouding-fail.l: Likewise.
* testsuite/gas/riscv/rouding-fail.s: Likewise.
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* config/tc-z80.c: Correct treatment of undocumented instruction
sli/sll.
(emit_mr): Add argument unportable.
(emit_bit): Adapt call to emit_mr.
(emit_mr_z80): New function.
(emit_mr_unportable): New function.
(instab[]): Replace emit_mr with emit_mr_z80 or emit_mr_unportable
as appropriate.
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Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions. Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field. This patch
changes that to using the operand extract function to provide non-zero
defaults.
I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.
The patch does change the error you get on invalid assembly like
ld 3,4
You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".
gas/
* config/tc-ppc.c (md_assemble): Delay counting of optional
operands until one is encountered. Allow for the possibility
of optional base regs, ie. PPC_OPERAND_PARENS. Call
ppc_optional_operand_value with extra args.
include/
* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
Mention use of "extract" function to provide default value.
(PPC_OPERAND_OPTIONAL_VALUE): Delete.
(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
* ppc-dis.c (operand_value_powerpc): Init "invalid".
(skip_optional_operands): Count optional operands, and update
ppc_optional_operand_value call.
* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
(extract_vlensi): Likewise.
(extract_fxm): Return default value for missing optional operand.
(extract_ls, extract_raq, extract_tbr): Likewise.
(insert_sxl, extract_sxl): New functions.
(insert_esync, extract_esync): Remove Power9 handling and simplify.
(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
flag and extra entry.
(powerpc_operands <SXL>): Likewise, and use insert_sxl and
extract_sxl.
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opcodes/
* s12z.h: Delete.
* s12z-dis.c: Adjust path of included file.
include/
* opcode/s12z.h: New file.
gas/
* config/tc-s12z.c: Adjust path of included file.
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There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions. This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.
gas/
* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
(cpu_noarch): Add nocmov and nofxsr.
* doc/c-i386.texi: Document cmov and fxsr.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
(cpu_flags): Add CpuCMOV and CpuFXSR.
* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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For 32-bit x86 assembler, --64 and --x32 are unsupported if BFD64 is
undefined. Even if BFD64 is defined, --64 and --x32 still may not be
supported if x86-64 support isn't compiled in:
[hjl@gnu-hsw-1 gas]$ ./as-new --64 -o x.o x.s
Assembler messages:
Fatal error: no compiled in support for x86_64
[hjl@gnu-hsw-1 gas]$ ./as-new --x32 -o x.o x.s
Assembler messages:
Fatal error: no compiled in support for 32bit x86_64
[hjl@gnu-hsw-1 gas]$
This patch removes --32/--64/--x32 from md_show_usage if BFD64 is
undefined and runs code64-inval only if BFD64 is undefined.
* config/tc-i386.c (md_show_usage): Don't display --32/--64/--x32
if BFD64 is undefined.
* testsuite/gas/i386/i386.exp (gas_bfd64_check): New.
Run code64-inval if gas_bfd64_check fails.
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* config/tc-i386.c (md_show_usage): Display default options.
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|
PR 23481
* config/tc-pdp11.c (parse_op_noreg): Check for deferred register
addressing before assuming non-deferred addressing.
* testsuite/gas/pdp11/pr23481.s: New test source file.
* testsuite/gas/pdp11/pr23481.d: New test driver file.
* testsuite/gas/pdp11/pdp11.exp: Run the new test.
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Check if an input asm file is rf16 compliant; if not, and the tag says
otherwise, fix the tag and emit a warning.
gas/
2017-09-20 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (rf16_only): New static variable.
(autodetect_attributes): Check if we are rf16 compliant.
(arc_set_public_attributes): Fix and emit the warning is required.
* testsuite/gas/arc/attr-rf16.d: New file.
* testsuite/gas/arc/attr-rf16.err: Likewise.
* testsuite/gas/arc/attr-rf16.s: Likewise.
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Add a new tag (Tag_ARC_ATR_version) used to indicate if current
attributes are interpreted in GNU way. This attribute is used by
Synopsys custom compiler to correctly identify and interpret the
object attributes section as generated by GNU tools.
gas/
2017-08-02 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (arc_set_public_attributes): Add
Tag_ARC_ATR_version.
(arc_convert_symbolic_attribute): Likewise.
* testsuite/gas/arc/attr-arc600.d: Update test.
* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
* testsuite/gas/arc/attr-arc601.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
* testsuite/gas/arc/attr-arc700.d: Likewise.
* testsuite/gas/arc/attr-arcem.d: Likewise.
* testsuite/gas/arc/attr-archs.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
* testsuite/gas/arc/attr-cpu-em.d: Likewise.
* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
* testsuite/gas/arc/attr-em.d: Likewise.
* testsuite/gas/arc/attr-em4.d: Likewise.
* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
* testsuite/gas/arc/attr-hs.d: Likewise.
* testsuite/gas/arc/attr-hs34.d: Likewise.
* testsuite/gas/arc/attr-hs38.d: Likewise.
* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
* testsuite/gas/arc/attr-mul64.d: Likewise.
* testsuite/gas/arc/attr-name.d: Likewise.
* testsuite/gas/arc/attr-nps400.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
bfd/
2017-08-02 Claudiu Zissulescu <claziss@synopsys.com>
* elf32-arc.c (arc_elf_merge_attributes): Handle
Tag_ARC_ATR_version.
binutils/
2017-08-02 Claudiu Zissulescu <claziss@synopsys.com>
* readelf.c (display_arc_attribute): Print Tag_ARC_ATR_version.
include/
2017-08-02 Claudiu Zissulescu <claziss@synopsys.com>
* elf/arc.h (Tag_ARC_ATR_version): New tag.
ld/
2017-08-02 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/attr-merge-0.d: Update test.
* testsuite/ld-arc/attr-merge-1.d: Likewise.
* testsuite/ld-arc/attr-merge-2.d: Likewise.
* testsuite/ld-arc/attr-merge-3.d: Likewise.
* testsuite/ld-arc/attr-merge-5.d: Likewise.
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Update aux-registers data-base, and accept aux-registers names with
upper/lowercase names.
opcode/
2017-07-18 Claudiu Zissulescu <claziss@synopsys.com>
* arc-regs.h: Update aux-registers.
gas/
2017-07-18 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (find_opcode_match): Accept uppercase aux-regs
names.
* testsuite/gas/arc/ld2.d: Update test.
* testsuite/gas/arc/taux.d: Likewise.
* testsuite/gas/arc/taux.s: Likewise.
include/
2017-07-18 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (ARC_OPCODE_ARCV1): Define.
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This allows to simplify the code in a number of places.
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R_PPC64_REL24_NOTOC is used on calls like "bl foo@notoc" to tell the
linker that linkage stubs for PLT calls or long branches can't use r2
for pic addressing. Instead, new stubs that generate pc-relative
addresses are used. One complication is that pc-relative offsets to
the PLT may need to be 64-bit in large programs, in contrast to the
toc-relative addressing used by older PLT linkage stubs where a 32-bit
offset is sufficient until the PLT itself exceeds 2G in size.
.eh_frame info to cover the _notoc stubs is yet to be implemented.
bfd/
* elf64-ppc.c (ADDI_R12_R11, ADDI_R12_R12, LIS_R12),
(ADDIS_R12_R11, ORIS_R12_R12_0, ORI_R12_R12_0),
(SLDI_R12_R12_32, LDX_R12_R11_R12, ADD_R12_R11_R12): Define.
(ppc64_elf_howto_raw): Add R_PPC64_REL24_NOTOC entry.
(ppc64_elf_reloc_type_lookup): Support R_PPC64_REL24_NOTOC.
(ppc_stub_type): Add ppc_stub_long_branch_notoc,
ppc_stub_long_branch_both, ppc_stub_plt_branch_notoc,
ppc_stub_plt_branch_both, ppc_stub_plt_call_notoc, and
ppc_stub_plt_call_both.
(is_branch_reloc): Add R_PPC64_REL24_NOTOC.
(build_offset, size_offset): New functions.
(plt_stub_size): Support plt_call_notoc and plt_call_both.
(ppc_build_one_stub, ppc_size_one_stub): Support new stubs.
(toc_adjusting_stub_needed): Handle R_PPC64_REL24_NOTOC.
(ppc64_elf_size_stubs): Likewise, and new stubs.
(ppc64_elf_build_stubs, ppc64_elf_relocate_section): Likewise.
* reloc.c: Add BFD_RELOC_PPC64_REL24_NOTOC.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @notoc.
(ppc_force_relocation, ppc_fix_adjustable): Handle REL24_NOTOC.
ld/
* testsuite/ld-powerpc/ext.d,
* testsuite/ld-powerpc/ext.s,
* testsuite/ld-powerpc/ext.lnk,
* testsuite/ld-powerpc/notoc.d,
* testsuite/ld-powerpc/notoc.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
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A small rework of the PRU GCC port exposed that CIE data alignment is
erroneously set to 4 for PRU in GAS. In fact PRU stack must be aligned to 1.
Set the macro to -1, to allow output from GCC to be assembled without errors.
Also, while at it, set DWARF2 HW register numbering to follow latest
* config/tc-pru.c (pru_regname_to_dw2regnum): Return the starting HW
byte-register number.
(pru_frame_initial_instructions): Use byte-numbering for FP index.
* config/tc-pru.h (DWARF2_DEFAULT_RETURN_COLUMN): Use number from
latest GCC.
(DWARF2_CIE_DATA_ALIGNMENT): Set to -1.
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No template specifies this bit, so there's no point recording it in the
templates. Use a flags[] bit instead.
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auto increment.
PR 14480
* config/tc-pdp11.c (parse_op_noreg): Check for and handle auto
increment deferred.
* testsuite/gas/pdp11/pr14480.d: New test driver file.
* testsuite/gas/pdp11/pr14480.s: New test source file file.
* testsuite/gas/pdp11/pdp11.exp: Run the new test.
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* config/tc-ns32k.c (addr_mode): Replace "Drop through" comment
with "Fall through" so that it will be recognised by gcc's switch
statment error checker.
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These can be converted to 2-byte VEX encoding when both source registers
are the same, by using KXORW / KANDNW as replacement.
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There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for
handling the not uncommon case of insns allowing either form of masking
with register operands, but only merging masking with a memory operand.
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Instead of hitting the abort() in output_insn() (commented by "There
should be no other prefixes for instructions with VEX prefix"), report
a proper diagnostic instead, just like we do e.g. for invalid REP
prefixes.
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