aboutsummaryrefslogtreecommitdiff
path: root/gas/config
AgeCommit message (Collapse)AuthorFilesLines
2016-09-21[AArch64][SVE 09/32] Improve error messages for invalid floatsRichard Sandiford1-6/+14
Previously: fmov d0, #2 would give an error: Operand 2 should be an integer register whereas the user probably just forgot to add the ".0" to make: fmov d0, #2.0 This patch reports an invalid floating point constant unless the operand is obviously a register. The FPIMM8 handling is only relevant for SVE. Without it: fmov z0, z1 would try to parse z1 as an integer immediate zero (the res2 path), whereas it's more likely that the user forgot the predicate. This is tested by the final patch. gas/ * config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific low-severity error for registers. (parse_operands): Report an invalid floating point constant for if parsing an FPIMM8 fails, and if no better error has been recorded. * testsuite/gas/aarch64/diagnostic.s, testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands to FMOV.
2016-09-21[AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovableRichard Sandiford1-33/+29
SVE has single-bit floating-point constants that don't really have any relation to the AArch64 8-bit floating-point encoding. (E.g. one of the constants selects between 0 and 1.) The easiest way of representing them in the aarch64_opnd_info seemed to be to use the IEEE float representation directly, rather than invent some new scheme. This patch paves the way for that by making the code that converts IEEE doubles to IEEE floats accept any value in the range of an IEEE float, not just zero and 8-bit floats. It leaves the range checking to the caller (which already handles it). gas/ * config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename to... (can_convert_double_to_float): ...this. Accept any double-precision value that converts to single precision without loss of precision. (parse_aarch64_imm_float): Update accordingly.
2016-09-21[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_VRichard Sandiford1-22/+31
To remove parsing ambiguities and to avoid register names being accidentally added to the symbol table, the immediate parsing routines reject things like: .equ x0, 0 add v0.4s, v0.4s, x0 An explicit '#' must be used instead: .equ x0, 0 add v0.4s, v0.4s, #x0 Of course, it wasn't possible to predict what other register names might be added in future, so this behaviour was restricted to the register names that were defined at the time. For backwards compatibility, we should continue to allow things like: .equ p0, 0 add v0.4s, v0.4s, p0 even though p0 is now an SVE register. However, it seems reasonable to extend the x0 behaviour above to SVE registers when parsing SVE instructions, especially since none of the SVE immediate formats are relocatable. Doing so removes the same parsing ambiguity for SVE instructions as the x0 behaviour removes for base AArch64 instructions. As a prerequisite, we then need to be able to tell the parsing routines which registers to reject. This patch changes the interface to make that possible, although the set of rejected registers doesn't change at this stage. gas/ * config/tc-aarch64.c (parse_immediate_expression): Add a reg_type parameter. (parse_constant_immediate): Likewise, and update calls. (parse_aarch64_imm_float): Likewise. (parse_big_immediate): Likewise. (po_imm_nc_or_fail): Update accordingly, passing down a new imm_reg_type variable. (po_imm_of_fail): Likewise. (parse_operands): Likewise.
2016-09-21[AArch64][SVE 06/32] Generalise parse_neon_reg_listRichard Sandiford1-5/+8
Rename parse_neon_reg_list to parse_vector_reg_list and take in the required register type as an argument. Later patches will reuse the function for SVE registers. gas/ * config/tc-aarch64.c (parse_neon_reg_list): Rename to... (parse_vector_reg_list): ...this and take a register type as input. (parse_operands): Update accordingly.
2016-09-21[AArch64][SVE 05/32] Rename parse_neon_type_for_operandRichard Sandiford1-2/+2
Generalise the name of parse_neon_type_for_operand to parse_vector_type_for_operand. Later patches will add SVEisms to it. gas/ * config/tc-aarch64.c (parse_neon_type_for_operand): Rename to... (parse_vector_type_for_operand): ...this. (parse_typed_reg): Update accordingly.
2016-09-21[AArch64][SVE 04/32] Rename neon_type_el to vector_type_elRichard Sandiford1-16/+16
Similar to the previous patch, but this time for the neon_type_el structure. gas/ * config/tc-aarch64.c (neon_type_el): Rename to... (vector_type_el): ...this. (parse_neon_type_for_operand): Update accordingly. (parse_typed_reg): Likewise. (aarch64_reg_parse): Likewise. (vectype_to_qualifier): Likewise. (parse_operands): Likewise. (eq_neon_type_el): Likewise. Rename to... (eq_vector_type_el): ...this. (parse_neon_reg_list): Update accordingly.
2016-09-21[AArch64][SVE 03/32] Rename neon_el_type to vector_el_typeRichard Sandiford1-4/+4
Later patches will add SVEisms to neon_el_type, so this patch renames it to something more generic. gas/ * config/tc-aarch64.c (neon_el_type: Rename to... (vector_el_type): ...this. (neon_type_el): Update accordingly. (parse_neon_type_for_operand): Likewise. (vectype_to_qualifier): Likewise.
2016-09-21[AArch64][SVE 01/32] Remove parse_neon_operand_typeRichard Sandiford1-27/+4
A false return from parse_neon_operand_type had an overloaded meaning: either the parsing failed, or there was nothing to parse (which isn't necessarily an error). The only caller, parse_typed_reg, would therefore not consume the suffix if it was invalid but instead (successfully) parse the register without a suffix. It would still leave inst.parsing_error with an error about the invalid suffix. It seems wrong for a successful parse to leave an error message, so this patch makes parse_typed_reg return PARSE_FAIL instead. The patch doesn't seem to make much difference in practice. Most possible follow-on errors use set_first_error and so the error about the suffix tended to win despite the successful parse. gas/ * config/tc-aarch64.c (parse_neon_operand_type): Delete. (parse_typed_reg): Call parse_neon_type_for_operand directly.
2016-09-14gas: improve architecture mismatch diagnostics in sparcJose E. Marchesi1-1/+1
Merely dumping the mnemonic name in "architecture mismatch" errors may not provide enough information to determine what went wrong, as the same mnemonic can be used for different variants of an instruction pertaining to different architecture levels. This little patch makes the assembler to include the instruction arguments in the error message. gas/ChangeLog: 2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_ip): Print the instruction arguments in "architecture mismatch" error messages.
2016-09-14gas: detect DCTI couples in sparcJose E. Marchesi1-11/+45
Before SPARC V9 the effect of having a delayed branch instruction in the delay slot of a conditional delayed branch was undefined. In SPARC V9 DCTI couples are well defined. However, starting with the UltraSPARC Architecture 2005, DCTI couples (of all kind) are deprecated and should not be used, as they may be slow or behave differently to what the programmer expects. This patch adds a new command line option --dcti-couples-detect to `as', disabled by default, that makes the assembler to warn the user if an unpredictable DCTI couple is found. Tests and documentation are included. gas/ChangeLog: 2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (md_assemble): Detect and warning on unpredictable DCTI couples in certain arches. (dcti_couples_detect): New global. (md_longopts): Add command line option -dcti-couples-detect. (md_show_usage): Document -dcti-couples-detect. (md_parse_option): Handle OPTION_DCTI_COUPLES_DETECT. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run dcti-couples-v8, dcti-couples-v9 and dcti-couples-v9c tests. * testsuite/gas/sparc/dcti-couples.s: New file. * testsuite/gas/sparc/dcti-couples-v9c.d: Likewise. * testsuite/gas/sparc/dcti-couples-v8.d: Likewise. * testsuite/gas/sparc/dcti-couples-v9.d: Likewise. * testsuite/gas/sparc/dcti-couples-v9c.l: Likewise. * testsuite/gas/sparc/dcti-couples-v8.l: Likewise. * doc/as.texinfo (Overview): Document --dcti-couples-detect. * doc/c-sparc.texi (Sparc-Opts): Likewise.
2016-09-14[ARC] Fix parsing dtpoff relocation expression.Claudiu Zissulescu1-1/+1
The assembler accepts dtpoff complex relocation expression like identifier@dtpoff + const. However, it doesn't accept an expression such as identifier@dtpoff@base + const. This patch solves this issue, and adds a number of tests. ld/ 2016-09-14 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/tls-dtpoff.dd: New file. * testsuite/ld-arc/tls-dtpoff.rd: Likewise. * testsuite/ld-arc/tls-dtpoff.s: Likewise. * testsuite/ld-arc/tls-relocs.ld: Likewise. * testsuite/ld-arc/arc.exp: Add new tdpoff test. gas/ 2016-09-14 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/tls-relocs2.d: New file. * testsuite/gas/arc/tls-relocs2.s: Likewise. * config/tc-arc.c (tokenize_arguments): Accept offsets when base is used.
2016-09-12S/390: Add alternate processor names.Andreas Krebbel1-13/+31
This patch adds alternate CPU names which adhere to the number of the architecture document. So instead of having z196, zEC12, and z13 you can use arch9, arch10, and arch11. The old cpu names stay valid and should primarily be used. The alternate names are supposed to improve compatibility with the IBM XL compiler toolchain which uses the arch numbering. opcodes/ChangeLog: 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Support alternate arch strings. gas/ChangeLog: 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Support alternate arch strings. * doc/as.texinfo: Document new arch strings. * doc/c-s390.texi: Likewise.
2016-09-12S/390: Fix facility bit default.Andreas Krebbel1-1/+4
gas/ChangeLog: 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c: Set all facitily bits by default
2016-09-08Allow PROCESSOR_IAMCU for Intel MCUH.J. Lu1-1/+1
* config/tc-i386.c (i386_target_format): Allow PROCESSOR_IAMCU for Intel MCU.
2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu1-21/+2
Originally only Pentium integer instructions are allowed for IAMCU. This patch removes such a restriction. For example, 387 and SSE2 instructions can be enabled by passing "-march=iamcu+sse2+387" to assembler. gas/ * config/tc-i386.c (valid_iamcu_cpu_flags): Removed. (set_cpu_arch): Updated. (md_parse_option): Likewise. * testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5. Remove iamcu-inval-2 and iamcu-inval-3. * testsuite/gas/i386/iamcu-4.d: New file. * testsuite/gas/i386/iamcu-4.s: Likewise. * testsuite/gas/i386/iamcu-5.d: Likewise. * testsuite/gas/i386/iamcu-5.s: Likewise. * testsuite/gas/i386/iamcu-inval-2.l: Removed. * testsuite/gas/i386/iamcu-inval-2.s: Likewise. * testsuite/gas/i386/iamcu-inval-3.l: Likewise. * testsuite/gas/i386/iamcu-inval-3.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS. * i386-init.h: Regenerated.
2016-09-07[arm] Automatically enable CRC instructions on supported ARMv8-A CPUs.Richard Earnshaw1-9/+9
2016-09-07 Richard Earnshaw <rearnsha@arm.com> * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture. 2016-09-07 Richard Earnshaw <rearnsha@arm.com> * config/tc-arm.c ((arm_cpus): Use ARM_ARCH_V8A_CRC for all ARMv8-A CPUs except xgene1.
2016-08-31PowerPC VLE sh_flags and p_flagsAlan Modra1-5/+9
ELF section sh_flags SHF_PPC_VLE was being set based on arch/mach, which meant all code sections in an object file has the flag or all lacked it. We can do better than that. Only those code sections where VLE is enabled ought to have the flag, allowing an object file to contain both VLE and non-VLE code. Also, ELF header p_flags PF_PPC_VLE wasn't being set, and segments were being split unnecessarily. bfd/ * elf32-ppc.c (ppc_elf_section_processing): Delete. (elf_backend_section_processing): Don't define. (ppc_elf_modify_segment_map): Set p_flags and mark valid. Don't split on non-exec sections differing in SHF_PPC_VLE. When splitting segments, mark size invalid. gas/ * config/tc-ppc.c (md_assemble): Set sh_flags for VLE. Test ppc_cpu rather than calling ppc_mach to determine VLE mode. (ppc_frag_check, ppc_handle_align): Likewise use ppc_cpu.
2016-08-26Add missing ARMv8-M special registersThomas Preud'homme1-18/+27
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and their lowecase counterpart special registers. Write register identifier in hex. * testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per operation, special register and then case. Use different register for each operation. Add tests for new special registers. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result accordingly. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise. opcodes/ * arm-dis.c (psr_name): Use hex as case labels. Add detection for MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
2016-08-25Remove _S version of ARM MSR/MRS special registersThomas Preud'homme1-2/+2
2016-08-25 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (v7m_psrs): Remove msp_s, MSP_S, psp_s and PSP_S special registers. * testsuite/gas/arm/archv8m-cmse-msr.s: Remove test for above special registers. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+2
Implement ptwrite instruction defined in Intel64 and IA-32 Architectures Software Developer’s Manual, June 2016. gas/ * config/tc-i386.c (cpu_arch): Add .ptwrite. * doc/c-i386.texi: Document ptwrite and .ptwrite. * testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel, x86-64-ptwrite and x86-64-ptwrite-intel. * testsuite/gas/i386/ptwrite-intel.d: New file. * testsuite/gas/i386/ptwrite.d: Likewise. * testsuite/gas/i386/ptwrite.s: Likewise. * testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.s: Likewise. opcodes/ * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. (PREFIX_MOD_3_0FAE_REG_4): Likewise. (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS. (cpu_flags): Add CpuPTWRITE. * i386-opc.h (CpuPTWRITE): New. (i386_cpu_flags): Add cpuptwrite. * i386-opc.tbl: Add ptwrite instruction. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-08-19ARM: Issue a warning when the MRRC and MRRC2 instructions are used with the ↵Tamar Christina1-0/+8
same destination registers. * config/tc-arm.c (do_co_reg2c): Added constraint. * testsuite/gas/arm/dest-unpredictable.s: New. * testsuite/gas/arm/dest-unpredictable.l: New. * testsuite/gas/arm/dest-unpredictable.d: New.
2016-08-11[AArch64] Reject -0.0 as an 8-bit FP immediateRichard Sandiford1-1/+1
parse_aarch64_imm_float was accepting -0.0 even though that's not a valid immediate for any instruction. The FPIMM0 caller rejected it, but the FPIMM one would silently treat it as -2.0. This patch rejects -0.0 and adds testcases to illegal.[sd]. Before the patch, the final error emitted for illegal.s was: Error: cannot do 16-byte relocation which was matched by: [^:]*:569: Error: .* The error was reported against the last line of the file rather than the instruction that required the reloc. Adding more instructions meant that the line number also changed. Reporting against the wrong line isn't good from a QoI perspective but isn't what I'm trying to fix here. Until it's fixed, I thought it would be better to adjust the match to be against an end-of-file comment rather than against whatever the last instruction happens to be. gas/ * config/tc-aarch64.c (parse_aarch64_imm_float): Reject -0.0. * testsuite/gas/aarch64/illegal.s, testsuite/gas/aarch64/illegal.l: Add tests for -0.0. Add an end-of-file comment.
2016-08-05Ensure ARM VPUSH and VPOP instructions do not affect more than 16 registers.Nick Clifton2-37/+53
PR gas/20429 * config/tc-arm.c (do_vfp_nsyn_push): Check that no more than 16 registers are pushed. (do_vfp_nsyn_pop): Check that no more than 16 registers are popped. * testsuite/gas/arm/pr20429.s: New test. * testsuite/gas/arm/pr20429.d: New test driver. * testsuite/gas/arm/pr20429.1: Expected error output.
2016-08-05Fix the generation of alignment frags in code sections for AArch64.Nick Clifton1-3/+7
PR gas/20364 * config/tc-aarch64.c (s_ltorg): Change the mapping state after aligning the frag. (aarch64_init): Treat rs_align frags in code sections as containing code, not data. * testsuite/gas/aarch64/pr20364.s: New test. * testsuite/gas/aarch64/pr20364.d: New test driver.
2016-08-04Fix generation of relocs for 32-bit Sparc Solaris targets.Stefan Trleman1-0/+16
PR gas/20427 * config/tc-sparc.c (cons_fix_new_sparc): Prevent the generation of 64-bit relocation types when assembling for a 32-bit Solaris target.
2016-07-27MIPS/GAS: Implement microMIPS branch/jump compactionMaciej W. Rozycki1-51/+203
Convert microMIPS branches and jumps whose delay slot would be filled by a generated NOP instruction to the corresponding compact form where one exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap. Do so even where the transformation switches from a 16-bit to a 32-bit branch encoding for no benefit in code size reduction, as this is still advantageous. This is because a branch/NOP pair takes 2 pipeline slots or a 2-cycle completion latency except in superscalar implementations. Whereas a compact branch may or may not stall on its target fetch, so it will at most have a 2-cycle completion latency and may have only 1 even in scalar implementations, and in superscalar implementations it is expected to have no worse latency as a branch/NOP pair has. Also it won't stall and therefore take the extra latency cycle in the not-taken case. Technically this is the same as MIPS16 compaction: for the qualifying instruction encodings the APPEND_ADD_COMPACT machine code generation method is selected where APPEND_ADD_WITH_NOP otherwise would and tells the code generator in `append_insn' to convert the regular form of an instruction to its corresponding compact form. For this the opcode is tweaked as necessary and the microMIPS opcode table is scanned for the matching updated instruction. A non-$0 `rt' operand to BEQ and BNE instructions is moved to the `rs' operand field of BEQZC and BNEZC encodings as required. Unlike with MIPS16 compaction however we need to handle out-of-distance branch relaxation as well. We do this by deferring the generation of any delay-slot NOP required to relaxation made in `md_convert_frag', by converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD where a relaxed instruction is recorded. Relaxation then, depending on actual code produced, chooses between either using a compact branch or jump encoding and emitting the NOP outstanding if no compact encoding is possible. For code simplicity's sake the relaxation pass is retained even if the principle of preferring a compact encoding to a 16-bit branch/NOP pair means, in the absence of out-of-range branch relaxation, that a single compact branch machine code instruction will eventually be produced from a given assembly source instruction. gas/ * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag. (RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16) (RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16) (RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32) (RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits. (get_append_method): Also return APPEND_ADD_COMPACT for microMIPS instructions. (find_altered_mips16_opcode): Exclude macros from matching. Factor code out... (find_altered_opcode): ... to this new function. (find_altered_micromips_opcode): New function. (frag_branch_delay_slot_size): Likewise. (append_insn): Handle microMIPS branch/jump compaction. (macro_start): Likewise. (relaxed_micromips_32bit_branch_length): Likewise. (md_convert_frag): Likewise. * testsuite/gas/mips/micromips.s: Add conditional explicit NOPs for delay slot filling. * testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for delay slot filling. * testsuite/gas/mips/micromips-size-1.s: Likewise. * testsuite/gas/mips/micromips.l: Adjust line numbers. * testsuite/gas/mips/micromips-warn.l: Likewise. * testsuite/gas/mips/micromips-size-1.l: Likewise. * testsuite/gas/mips/micromips.d: Adjust padding. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips-insn32.d: Likewise. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips@beq.d: Update patterns for branch/jump compaction. * testsuite/gas/mips/micromips@bge.d: Likewise. * testsuite/gas/mips/micromips@bgeu.d: Likewise. * testsuite/gas/mips/micromips@blt.d: Likewise. * testsuite/gas/mips/micromips@bltu.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-4.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: Likewise. * testsuite/gas/mips/micromips@loc-swap.d: Likewise. * testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise. * testsuite/gas/mips/micromips@relax.d: Likewise. * testsuite/gas/mips/micromips@relax-at.d: Likewise. * testsuite/gas/mips/micromips@relax-swap3.d: Likewise. * testsuite/gas/mips/branch-extern-2.d: Likewise. * testsuite/gas/mips/branch-extern-4.d: Likewise. * testsuite/gas/mips/branch-section-2.d: Likewise. * testsuite/gas/mips/branch-section-4.d: Likewise. * testsuite/gas/mips/branch-weak-2.d: Likewise. * testsuite/gas/mips/branch-weak-5.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: Likewise. * testsuite/gas/mips/micromips-compact.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. ld/ * testsuite/ld-mips-elf/micromips-branch-absolute.d: Update patterns for branch compaction. * testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: Likewise. opcodes/ * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b", "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to "j".
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall1-35/+117
opcodes * arc-nps400-tbl.h: Change block comments to GNU format. * arc-dis.c: Add new globals addrtypenames, addrtypenames_max, and addtypeunknown. (get_addrtype): New function. (print_insn_arc): Print colons and address types when required. * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to define insert and extract functions for all address types. (arc_operands): Add operands for colon and all address types. * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table. * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands, insert_nps_bd_num_buff and extract_nps_bd_num_buff functions. * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table. * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands, insert_nps_pmu_num_job and extract_nps_pmu_num_job functions. include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE, ARC_OPERAND_COLON. Add the arc_nps_address_type enum and ARC_NUM_ADDRTYPES. * opcode/arc.h: Add BMU to insn_class_t enum. * opcode/arc.h: Add PMU to insn_class_t enum. gas * config/tc-arc.c: Add new global arc_addrtype_hash. Define O_colon and O_addrtype. (debug_exp): Add O_colon and O_addrtype. (tokenize_arguments): Handle colon and address type tokens. (declare_addrtype): New function. (md_begin): Initialise arc_addrtype_hash. (arc_parse_name): Add lookup of address types. (assemble_insn): Handle colons and address types by ignoring them. * testsuite/gas/arc/nps400-8.s: New file. * testsuite/gas/arc/nps400-8.d: New file. * testsuite/gas/arc/nps400-8.s: Add PMU instruction tests. * testsuite/gas/arc/nps400-8.d: Add expected PMU instruction output.
2016-07-26MIPS/GAS: Respect the `insn32' mode in branch relaxationMaciej W. Rozycki1-45/+85
Complement: commit 833794fc12d98139fc33f6b0b85feb03471007b7 Author: Maciej W. Rozycki <macro@linux-mips.org> Date: Tue Jun 25 18:02:34 2013 +0000 <https://sourceware.org/ml/binutils/2013-06/msg00104.html>, ("microMIPS insn32 mode support"), and fix an issue with microMIPS branch relaxation producing 16-bit instructions in the `insn32' mode. Use equivalent 32-bit instruction sequences. gas/ * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `insn32' flag. (RELAX_MICROMIPS_INSN32): New macro. (RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT) (RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_RELAX32) (RELAX_MICROMIPS_TOOFAR16, RELAX_MICROMIPS_MARK_TOOFAR16) (RELAX_MICROMIPS_CLEAR_TOOFAR16, RELAX_MICROMIPS_TOOFAR32) (RELAX_MICROMIPS_MARK_TOOFAR32, RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits. (append_insn): Record `mips_opts.insn32' with relaxed microMIPS branches. (relaxed_micromips_32bit_branch_length): Handle the `insn32' mode. (md_convert_frag): Likewise. * testsuite/gas/mips/micromips-branch-relax.s: Add `insn32' conditionals. * testsuite/gas/mips/micromips-branch-relax.l: Update line numbers accordingly. * testsuite/gas/mips/micromips-branch-relax-pic.l: Likewise. * testsuite/gas/mips/micromips-branch-relax-insn32.d: New test. * testsuite/gas/mips/micromips-branch-relax-insn32-pic.d: New test. * testsuite/gas/mips/micromips-branch-relax-insn32.l: New stderr output. * testsuite/gas/mips/micromips-branch-relax-insn32-pic.l: New stderr output. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-20MIPS/GAS: Remove erroneous ELF relocation referencesMaciej W. Rozycki1-7/+5
Remove R_MIPS_PC26_S2 and R_MIPS_PC21_S2 relocation references that went into `mips_force_relocation' with commit 9d862524f6ae ("MIPS: Verify the ISA mode and alignment of branch and jump targets") by mistake. Their BFD_RELOC_MIPS_26_PCREL_S2 and BFD_RELOC_MIPS_21_PCREL_S2 equivalents are already handled there. gas/ * config/tc-mips.c (mips_force_relocation): Remove R_MIPS_PC26_S2 and R_MIPS_PC21_S2.
2016-07-19MIPS: Convert cross-mode BAL to JALXMaciej W. Rozycki1-4/+14
Convert cross-mode regular MIPS and microMIPS BAL instructions to JALX, similarly to how JAL instructions are converted. bfd/ * elfxx-mips.c (mips_elf_perform_relocation): Convert cross-mode BAL to JALX. (_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add a corresponding error message. gas/ * config/tc-mips.c (mips_force_relocation, mips_fix_adjustable): Adjust comments for BAL to JALX linker conversion. (fix_bad_cross_mode_branch_p): Accept cross-mode BAL. * testsuite/gas/mips/unaligned-branch-1.l: Update error messages expected. * testsuite/gas/mips/unaligned-branch-micromips-1.l: Likewise. * testsuite/gas/mips/branch-local-4.d: New test. * testsuite/gas/mips/branch-local-n32-4.d: New test. * testsuite/gas/mips/branch-local-n64-4.d: New test. * testsuite/gas/mips/branch-addend.d: New test. * testsuite/gas/mips/branch-addend-n32.d: New test. * testsuite/gas/mips/branch-addend-n64.d: New test. * testsuite/gas/mips/branch-local-4.s: New test source. * testsuite/gas/mips/branch-addend.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/unaligned-branch-2.d: Update error messages expected. * testsuite/ld-mips-elf/unaligned-branch-r6-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-mips16.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-micromips.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-addend.d: New test. * testsuite/ld-mips-elf/bal-jalx-local.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic.d: New test. * testsuite/ld-mips-elf/bal-jalx-addend-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-addend-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-n64.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-2.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-3.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-2.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-3.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source. * testsuite/ld-mips-elf/unaligned-jalx-3.s: New test source. * testsuite/ld-mips-elf/unaligned-jalx-addend-2.s: New test source. * testsuite/ld-mips-elf/unaligned-jalx-addend-3.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-07-19MIPS: Verify the ISA mode and alignment of branch and jump targetsMaciej W. Rozycki1-16/+264
Verify that the ISA mode of branch targets is the same as the referring relocation, so that an attempt to produce a branch between instructions encoded in different ISA modes each causes an error rather than silently producing non-functional code. Make sure that no symbol or addend bits are silently truncated: terminate with an error if the relocation value calculated cannot be encoded in the relocatable field of a branch; for REL targets also applying to any intermediate addend. Also make jump target's alignment verification consistent with that for branches. This change will require an update to some obscure handcoded assembly sources which make branches to labels placed at data objects, however for microMIPS code only. These labels will have to be updated with the `.insn' directive for containing code to assemble and link successfully. Such code is broken as any such labels have always been required by the microMIPS architecture specification[1][2] to be annotated this way for correct interpretation, and with our old code missing `.insn' directives caused labels to present different semantics depending on whether they were referred with branch (ISA bit ignored) or other relocations (ISA bit respected). Enforcing these checks however will ensure errors in building software, like mixed regular MIPS and microMIPS code links with branches between, will be diagnosed at the build time rather than causing odd run-time errors such as intermittent crashes. It will also let cross-mode BAL instructions be converted to JALX instructions, with a separate change. References: [1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level Compatibility", p. 533 [2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level Compatibility", p. 623 bfd/ * elfxx-mips.c (b_reloc_p): Add R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC7_S1. (branch_reloc_p): New function. (mips_elf_calculate_relocation): Handle ISA mode determination for relocations against section symbols, against absolute symbols and absolute relocations. Also set `*cross_mode_jump_p' for branches. <R_MIPS16_26, R_MIPS_26, R_MICROMIPS_26_S1>: Suppress alignment checks for weak undefined symbols. Also check target alignment within the same ISA mode. <R_MIPS_PC16, R_MIPS_GNU_REL16_S2>: Handle cross-mode branches in the alignment check. <R_MICROMIPS_PC7_S1>: Add an alignment check. <R_MICROMIPS_PC10_S1>: Likewise. <R_MICROMIPS_PC16_S1>: Likewise. (mips_elf_perform_relocation): Report a failure for unsupported same-mode JALX instructions and cross-mode branches. (_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add error messages for jumps to misaligned addresses. gas/ * config/tc-mips.c (mips_force_relocation): Also retain branch relocations against MIPS16 and microMIPS symbols. (fix_bad_cross_mode_jump_p): New function. (fix_bad_same_mode_jalx_p): Likewise. (fix_bad_misaligned_jump_p): Likewise. (fix_bad_cross_mode_branch_p): Likewise. (fix_bad_misaligned_branch_p): Likewise. (fix_validate_branch): Likewise. (md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP> <BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5, etc. Verify the ISA mode and alignment of the jump target. <BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check with a call to `fix_validate_branch'. <BFD_RELOC_MIPS_26_PCREL_S2>: Likewise. <BFD_RELOC_16_PCREL_S2>: Likewise. <BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1> <BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend. Verify the ISA mode and alignment of the branch target. (md_convert_frag): Verify the ISA mode and alignment of resolved MIPS16 branch targets. * testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction branch targets with `.insn'. * testsuite/gas/mips/branch-misc-5.s: Likewise. * testsuite/gas/mips/micromips@branch-misc-5-64.d: Update accordingly. * testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise. * testsuite/gas/mips/micromips-branch-relax.s: Annotate non-instruction branch target with `.insn'. * testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets with external symbols. * testsuite/gas/mips/micromips-insn32.d: Update accordingly. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips.d: Likewise. * testsuite/gas/mips/mips16.s: Annotate non-instruction branch targets with `.insn'. * testsuite/gas/mips/mips16.d: Update accordingly. * testsuite/gas/mips/mips16-64.d: Likewise. * testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction branch target with `.insn'. * testsuite/gas/mips/relax-swap3.s: Likewise. * testsuite/gas/mips/branch-local-2.l: New list test. * testsuite/gas/mips/branch-local-3.l: New list test. * testsuite/gas/mips/branch-local-n32-2.l: New list test. * testsuite/gas/mips/branch-local-n32-3.l: New list test. * testsuite/gas/mips/branch-local-n64-2.l: New list test. * testsuite/gas/mips/branch-local-n64-3.l: New list test. * testsuite/gas/mips/unaligned-jump-1.l: New list test. * testsuite/gas/mips/unaligned-jump-2.l: New list test. * testsuite/gas/mips/unaligned-jump-3.d: New test. * testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test. * testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test. * testsuite/gas/mips/unaligned-jump-mips16-3.d: New test. * testsuite/gas/mips/unaligned-jump-micromips-1.l: New list test. * testsuite/gas/mips/unaligned-jump-micromips-2.l: New list test. * testsuite/gas/mips/unaligned-jump-micromips-3.d: New test. * testsuite/gas/mips/unaligned-branch-1.l: New list test. * testsuite/gas/mips/unaligned-branch-2.l: New list test. * testsuite/gas/mips/unaligned-branch-3.d: New test. * testsuite/gas/mips/unaligned-branch-r6-1.l: New list test. * testsuite/gas/mips/unaligned-branch-r6-2.l: New list test. * testsuite/gas/mips/unaligned-branch-r6-3.l: New list test. * testsuite/gas/mips/unaligned-branch-r6-4.l: New list test. * testsuite/gas/mips/unaligned-branch-r6-5.d: New test. * testsuite/gas/mips/unaligned-branch-r6-6.d: New test. * testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test. * testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test. * testsuite/gas/mips/unaligned-branch-mips16-3.d: New test. * testsuite/gas/mips/unaligned-branch-micromips-1.l: New list test. * testsuite/gas/mips/unaligned-branch-micromips-2.l: New list test. * testsuite/gas/mips/unaligned-branch-micromips-3.d: New test. * testsuite/gas/mips/branch-local-2.s: New test source. * testsuite/gas/mips/branch-local-3.s: New test source. * testsuite/gas/mips/branch-local-n32-2.s: New test source. * testsuite/gas/mips/branch-local-n32-3.s: New test source. * testsuite/gas/mips/branch-local-n64-2.s: New test source. * testsuite/gas/mips/branch-local-n64-3.s: New test source. * testsuite/gas/mips/unaligned-jump-1.s: New test source. * testsuite/gas/mips/unaligned-jump-2.s: New test source. * testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source. * testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source. * testsuite/gas/mips/unaligned-jump-micromips-1.s: New test source. * testsuite/gas/mips/unaligned-jump-micromips-2.s: New test source. * testsuite/gas/mips/unaligned-branch-1.s: New test source. * testsuite/gas/mips/unaligned-branch-2.s: New test source. * testsuite/gas/mips/unaligned-branch-r6-1.s: New test source. * testsuite/gas/mips/unaligned-branch-r6-2.s: New test source. * testsuite/gas/mips/unaligned-branch-r6-3.s: New test source. * testsuite/gas/mips/unaligned-branch-r6-4.s: New test source. * testsuite/gas/mips/unaligned-branch-mips16-1.s: New test source. * testsuite/gas/mips/unaligned-branch-mips16-2.s: New test source. * testsuite/gas/mips/unaligned-branch-micromips-1.s: New test source. * testsuite/gas/mips/unaligned-branch-micromips-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error message expected. * testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise. * testsuite/ld-mips-elf/undefweak-overflow.s: Add jumps, microMIPS BAL and MIPS16 instructions. * testsuite/ld-mips-elf/undefweak-overflow.d: Update accordingly. * testsuite/ld-mips-elf/unaligned-branch-2.d: New test. * testsuite/ld-mips-elf/unaligned-branch-r6-1.d: New test. * testsuite/ld-mips-elf/unaligned-branch-r6-2.d: New test. * testsuite/ld-mips-elf/unaligned-branch-mips16.d: New test. * testsuite/ld-mips-elf/unaligned-branch-micromips.d: New test. * testsuite/ld-mips-elf/unaligned-jump-mips16.d: New test. * testsuite/ld-mips-elf/unaligned-jump-micromips.d: New test. * testsuite/ld-mips-elf/unaligned-jump.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-07-19make the type of nds32_pseudo_opcode::pseudo_val unsignedTrevor Saunders1-32/+62
It can be initialized with values greater than 0x80000000, which don't fit in a signed int. Further it appears to be used as a set of bit flags where unsigned int is more typical. gas/ChangeLog: 2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-nds32.c (struct nds32_pseudo_opcode): Make pseudo_val unsigned int. (do_pseudo_b): Adjust. (do_pseudo_bal): Likewise. (do_pseudo_bge): Likewise. (do_pseudo_bges): Likewise. (do_pseudo_bgt): Likewise. (do_pseudo_bgts): Likewise. (do_pseudo_ble): Likewise. (do_pseudo_bles): Likewise. (do_pseudo_blt): Likewise. (do_pseudo_blts): Likewise. (do_pseudo_br): Likewise. (do_pseudo_bral): Likewise. (do_pseudo_la): Likewise. (do_pseudo_li): Likewise. (do_pseudo_ls_bhw): Likewise. (do_pseudo_ls_bhwp): Likewise. (do_pseudo_ls_bhwpc): Likewise. (do_pseudo_ls_bhwi): Likewise. (do_pseudo_move): Likewise. (do_pseudo_neg): Likewise. (do_pseudo_not): Likewise. (do_pseudo_pushpopm): Likewise. (do_pseudo_pushpop): Likewise. (do_pseudo_v3push): Likewise. (do_pseudo_v3pop): Likewise. (do_pseudo_pushpop_stack): Likewise. (do_pseudo_push_bhwd): Likewise. (do_pseudo_pop_bhwd): Likewise. (do_pseudo_pusha): Likewise. (do_pseudo_pushi): Likewise.
2016-07-19sparc: make a field type bfd_reloc_code_real_typeTrevor Saunders1-1/+1
gas/ChangeLog: 2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-sparc.c (struct pop_entry): Make the type of reloc bfd_reloc_code_real_type.
2016-07-19sparc: remove a sentinalTrevor Saunders1-16/+11
gas/ChangeLog: 2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-sparc.c (pop_table): Remove sentinel. (NUM_PERC_ENTRIES): Use ARRAY_SIZE on pop_table. (md_begin): Adjust.
2016-07-19tc-z8k.c: make some argument types bfd_reloc_code_real_typeTrevor Saunders1-3/+8
gas/ChangeLog: 2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-z8k.c (newfix): Make type of type argument bfd_reloc_code_real_type. (apply_fix): Likewise.
2016-07-16Don't include libbfd.h outside of bfd, part 2Alan Modra8-8/+0
Make bfd_default_set_arch_mach available to a bunch of gas backend files. bfd/ * archures.c (bfd_default_set_arch_mach): Make available in bfd.h. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-epiphany.c: Don't include libbfd.h. * config/tc-frv.c: Likewise. * config/tc-ip2k.c: Likewise. * config/tc-iq2000.c: Likewise. * config/tc-m32c.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mt.c: Likewise. * config/tc-nios2.c: Likewise.
2016-07-16Don't include libbfd.h outside of bfd, part 1Alan Modra5-8/+3
Make BFD_ALIGN available to objcopy. Fix assertions. Don't use bfd_log2 in ppc32elf.em or bfd_malloc in xtensaelf.em and bucomm.c. bfd/ * libbfd-in.h (BFD_ALIGN): Move to.. * bfd-in.h: ..here. * elf32-ppc.h (struct ppc_elf_params): Add pagesize. * elf32-ppc.c (default_params): Adjust init. (ppc_elf_link_params): Set pagesize_p2. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. binutils/ * ar.c: Don't include libbfd.h. * objcopy.c: Likewise. * bucomm.c (bfd_get_archive_filename): Use xmalloc rather than bfd_malloc. gas/ * config/bfin-parse.y: Don't include libbfd.h. * config/tc-bfin.c: Likewise. * config/tc-rl78.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-metag.c: Likewise. (create_dspreg_htabs, create_scond_htab): Use gas_assert not BFD_ASSERT. * Makefile.am: Update dependencies. * Makefile.in: Regenerate. ld/ * ldlang.c: Don't include libbfd.h. * emultempl/nds32elf.em: Likewise. * emultempl/ppc64elf.em: Likewise. * emultempl/ppc32elf.em: Likewise. (pagesize): Delete. (params): Update init. (ppc_after_open_output): Use params.pagesize. Don't call bfd_log2. (PARSE_AND_LIST_ARGS_CASES): Use params.pagesize. * emultempl/sh64elf.em: Don't include libbfd.h. (after_allocation): Use ASSERT, not BFD_ASSERT. * emultempl/xtensaelf.em: Don't include libbfd.h. (replace_insn_sec_with_prop_sec): Use xmalloc, not bfd_malloc. * Makefile.am: Update dependencies. * Makefile.in: Regenerate.
2016-07-14MIPS/GAS: Don't convert PC-relative REL relocs against absolute symbolsMaciej W. Rozycki2-0/+19
Don't convert PC-relative REL relocations against absolute symbols to section-relative references and retain the original symbol reference instead. Offsets into the absolute section may overflow the limited range of their in-place addend field, causing an assembly error, e.g.: $ cat test.s .text .globl foo .ent foo foo: b bar .end foo .set bar, 0x12345678 $ as -EB -32 -o test.o test.s test.s: Assembler messages: test.s:3: Error: relocation overflow $ With the original reference retained the source can now be assembled and linked successfully: $ as -EB -32 -o test.o test.s $ objdump -dr test.o test.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <foo>: 0: 1000ffff b 0 <foo> 0: R_MIPS_PC16 bar 4: 00000000 nop ... $ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o $ objdump -dr test test: file format elf32-tradbigmips Disassembly of section .text: 12340000 <foo>: 12340000: 1000159d b 12345678 <bar> 12340004: 00000000 nop ... $ For simplicity always retain the original symbol reference, even if it would indeed fit. Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch relocations against absolute symbols to be converted on RELA targets to section-relative references. This is an intended effect of this change. Absolute symbols carry no ISA annotation in their `st_other' field and their value is not going to change with linker relaxation, so it is safe to discard the original reference and keep the calculated final symbol value only in the relocation's addend. Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring absolute symbols can be safely converted even on REL targets, as there the in-place addend of these relocations covers the entire 32-bit address space so it can hold the calculated final symbol value, and likewise the value referred won't be affected by any linker relaxation. Add a set of suitable test cases and enable REL linker tests which now work and were previously used as dump patterns for RELA tests only. gas/ * config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro. (mips_force_relocation_abs): New prototype. * config/tc-mips.c (mips_force_relocation_abs): New function. * testsuite/gas/mips/branch-absolute.d: Adjust dump patterns. * testsuite/gas/mips/mips16-branch-absolute.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: Likewise. * testsuite/gas/mips/branch-absolute-addend.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend.d: New test. * testsuite/gas/mips/micromips-branch-absolute-addend.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips-elf.exp: Run `branch-absolute-addend', `mips16-branch-absolute', `mips16-branch-absolute-addend' and `micromips-branch-absolute-addend'.
2016-07-14MIPS/GAS: Keep the ISA bit in the addend of branch relocationsMaciej W. Rozycki1-9/+1
Correct a problem with the ISA bit being stripped from the addend of compressed branch relocations, affecting RELA targets. It has been there since microMIPS support has been added, with: commit df58fc944dbc6d5efd8d3826241b64b6af22f447 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Sun Jul 24 14:20:15 2011 +0000 <https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS: microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 relocations originally affected, and the R_MIPS16_PC16_S1 relocation recently added with commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually triggering a linker error, due to its heightened processing strictness level: $ cat test.s .text .set mips16 foo: b bar .set bar, 0x1235 .align 4, 0 $ as -EB -n32 -o test.o test.s $ objdump -dr test.o test.o: file format elf32-ntradbigmips Disassembly of section .text: 00000000 <foo>: 0: f000 1000 b 4 <foo+0x4> 0: R_MIPS16_PC16_S1 *ABS*+0x1230 ... $ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o test.o: In function `foo': (.text+0x0): Branch to a non-instruction-aligned address $ This is because the ISA bit of the branch target does not match the ISA bit of the referring branch, hardwired to 1 of course. Retain the ISA bit then, so that the linker knows this is really MIPS16 code referred: $ objdump -dr fixed.o fixed.o: file format elf32-ntradbigmips Disassembly of section .text: 00000000 <foo>: 0: f000 1000 b 4 <foo+0x4> 0: R_MIPS16_PC16_S1 *ABS*+0x1231 ... $ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o $ Add a set of MIPS16 tests to cover the relevant cases, excluding linker tests though which would overflow the in-place addend on REL targets and use them as dump patterns for RELA targets only. gas/ * config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1> <BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1> <BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the addend calculated. * testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit in `bar', export `foo'. * testsuite/gas/mips/mips16-branch-absolute.d: Adjust accordingly. * testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: Likewise. ld/ * testsuite/ld-mips-elf/mips16-branch-absolute.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except from `mips16-branch-absolute' and `mips16-branch-absolute-addend', referred indirectly only.
2016-07-11TLS: DTPOFF can accept offsets, stored into addendum. Remove the need of baseClaudiu Zissulescu1-23/+2
gas/ChangeLog: 2016-07-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_reloc_op_tag): Allow complex ops for dtpoff. (tc_gen_reloc): Remove passing DTPOFF base info into reloc addendum as it is no longer needed. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-07-08MIPS/GAS: Remove extraneous `install_insn' call from `append_insn'Maciej W. Rozycki1-1/+0
Complement: commit 1e91584932efd70020c8c98037d0cb93a0552a20 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Wed Mar 9 09:17:02 2005 +0000 <https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), and remove a call to `install_insn' from `append_insn', which as from that change has become redundant. This is because such a call, to place an instruction's bit pattern in output, is already made from `move_insn', called from `add_relaxed_insn' or `add_fixed_insn' as appropriate, either of which now always is and has to be made from `append_insn' before the repeated call to `install_insn' is made. Previously the place where this second invocation is made was the only one where the output stream was updated, although the update was made inline rather than with a function call. Remove the repeated call then, to reclaim some performance. gas/ * config/tc-mips.c (append_insn): Remove extraneous `install_insn' call.
2016-07-05x86: fix register check in check_qword_reg()Jan Beulich1-1/+1
A missing 'r' (or wrong 'e') register prefix needs to be complained about if the template allows for a 64-bit register, not a 32-bit one. I assume this was a copy-and-paste type of mistake (from check_long_reg()).
2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy1-17/+67
Feature flag handling was not perfect, +nofp16 disabled fp instructions too. New feature flag macros were added to check features with multiple bits set (matters for FP_F16 and SIMD_F16 opcode feature tests). The unused AARCH64_OPCODE_HAS_FEATURE was removed, all checks should use one of the AARCH64_CPU_HAS_* macros. AARCH64_CPU_HAS_FEATURE now checks all feature bits. The aarch64_features table now contains the dependencies as a separate field (so when the feature is enabled all dependencies are enabled and when it is disabled everything that depends on it is disabled). Note that armv8-a+foo+nofoo is not equivalent to armv8-a if +foo turns on dependent features that nofoo does not turn off. gas/ * config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add require field. (aarch64_features): Initialize require fields. (aarch64_parse_features): Handle dependencies. (aarch64_feature_enable_set, aarch64_feature_disable_set): New. (md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES. * testsuite/gas/aarch64/illegal-nofp16.s: New. * testsuite/gas/aarch64/illegal-nofp16.l: New. * testsuite/gas/aarch64/illegal-nofp16.d: New. include/ * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New. (AARCH64_CPU_HAS_ANY_FEATURES): New. (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES. (AARCH64_OPCODE_HAS_FEATURE): Remove.
2016-07-01x86-64/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich1-0/+17
Additionally warn about scaling factors other than 1 for the latter two, as those get ignored by the hardware.
2016-07-01x86/MPX: fix address size handlingJan Beulich1-4/+9
While address overrides are ignored in 64-bit mode (and hence shouldn't really result in an error, but upon v1 converting this to a warning I was told otherwise), trying to use 16-bit addressing is documented to result in #UD, and hence the assembler should reject the attempt. (The added test case at once also checks that bndc{l,n,u} won't accept 16-bit register operands.)
2016-07-01x86/Intel: don't accept bogus instructionsJan Beulich1-5/+27
... due to their last byte looking like a suffix, when after its stripping a matching instruction can be found. Since memory operand size specifiers in Intel mode get converted into suffix representation internally, we need to keep track of the actual mnemonic suffix which may have got trimmed off, and check its validity while looking for a matching template. I tripper over this quite some time again after support for AMD's SSE5 instructions got removed, as at that point some of the SSE5 mnemonics, other than expected, didn't fail to assemble. But the problem affects many more instructions, namely (almost) all MMX, SSE, and AVX ones as it looks. I don't think it makes sense to add a testcase covering all of them, nor do I think it makes sense to pick out some random examples for a new test case.
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich2-1/+57
The dual purpose mnemonic (string move vs scalar double move) breaks the assumption that the isstring flag would be set on both the first and last entry in the current set of templates, which results in bogus or missing diagnostics for the string move variant of the mnemonic. Short of mostly rewriting i386_index_check() and its interaction with the rest of the code, simply shrink the template set to just string instructions when encountering the second memory operand, and run i386_index_check() a second time for the first memory operand after that reduction.
2016-06-30MIPS/GAS: Fix a comment typo in `get_append_method'Maciej W. Rozycki1-1/+1
gas/ * config/tc-mips.c (get_append_method): Fix a comment typo.
2016-06-30MIPS16/GAS: Fix delay slot filling across fragsMatthew Fortune1-7/+2
Fix an assertion failure like: test.s: Assembler messages: test.s:3: Internal error! Assertion failure in append_insn at .../gas/config/tc-mips.c:7523. Please report this bug. triggered by assembling MIPS16 code like: hello: addiu $4, $4, 4 jr $31 with the generation of a listing file enabled, e.g.: $ as -mips16 -O2 -aln=test.lst The cause of the problem is the lack of support for moving instructions across frags in MIPS16 jump swapping, which triggers more easily with listing enabled as in that case every instruction gets placed in its own frag. It would trigger even with listing disabled though if the instruction to swap a MIPS16 jump with was unfortunately enough placed as last in a frag that became full. This scenario is already handled correctly with branch swapping in regular MIPS and microMIPS code, so reuse it for MIPS16 code as well, and now that all MIPS16 handling has become the same as the regular MIPS and microMIPS cases remove MIPS16 special casing altogether. This effectively complements: commit 464ab0e55ade01d2bb0b4fa45c429af7a2f85a26 Author: Maciej W. Rozycki <macro@linux-mips.org> Date: Mon Aug 6 20:33:00 2012 +0000 <https://sourceware.org/ml/binutils/2012-08/msg00043.html>, ("MIPS/GAS: Correct microMIPS branch swapping assertion") for the MIPS16 case. The assertion itself was introduced with: commit 1e91584932efd70020c8c98037d0cb93a0552a20 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Wed Mar 9 09:17:02 2005 +0000 <https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), but its introduction merely noted our existing lack of support for MIPS16 jump swapping across frags. gas/ * config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special case MIPS16 handling. * testsuite/gas/mips/branch-swap-3.d: New test. * testsuite/gas/mips/branch-swap-4.d: New test. * testsuite/gas/mips/mips16@branch-swap-3.d: New test. * testsuite/gas/mips/mips16@branch-swap-4.d: New test. * testsuite/gas/mips/micromips@branch-swap-3.d: New test. * testsuite/gas/mips/micromips@branch-swap-4.d: New test. * testsuite/gas/mips/branch-swap-3.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-30MIPS/GAS: Simplify non-MIPS16 branch swapping sequenceMaciej W. Rozycki1-3/+4
Simplify non-MIPS16 branch swapping by copying the MIPS16 variant, which sets the new position for the current instruction first and reduces the calculation of the new position of the previous instruction. Also refer to previous instruction's frag and position via `delay' for consistency. Reintroduce an explanatory comment, updated, previously removed with: commit 1e91584932efd70020c8c98037d0cb93a0552a20 Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Wed Mar 9 09:17:02 2005 +0000 <https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework MIPS nop-insertion code, add -mfix-vr4130 [5/11]"). gas/ * config/tc-mips.c (append_insn): Simplify non-MIPS16 branch swapping sequence.
generated by cgit v1.1 at 2025-02-23 15:06:20 +0000