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Except for very few insns mnemonic suffixes aren't permitted in Intel
syntax. Warn about such for now, indicating that they will be outright
refused down the road.
While fiddling with testcases to address fallout, drop a few things
which should never have been tested as valid Intel syntax.
Also add a previously missing line to simd-suffix.d.
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Since we uniformly permit D suffixes in Intel mode whenever in AT&T mode
an L suffix may be used, we need to be consistent with this.
Take the easy route, despite that still leading to an anomaly which is
also visible from the new testcase:
shld eax, ecx, 1
shld eax, ecx, cl
can mean two things with APX: SHL with a D suffix in NDD EVEX encoding,
or the traditional SHLD in legacy encoding.
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PR31796 is the result of lack of aarch64 support in obj-coff-seh.c.
Nick fixed this with commit 73c8603c3f. Make the seh support
consistently warn in future if some archictecture is missing, rather
than giving internal errors.
PR 31796
* config/obj-coff-seh.c (verify_target): New function.
(obj_coff_seh_handler, obj_coff_seh_endproc, obj_coff_seh_proc),
(obj_coff_seh_endprologue): Use it.
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Introduces instructions for the SVE2 lut extension for AArch64. They are documented in the following links:
* luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en
* luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en
These instructions use new SVE2 vector operands. They are called
SVE_Zm1_23_INDEX, SVE_Zm2_22_INDEX, and Zm3_12_INDEX and they have
1 bit, 2 bit, and 3 bit indices respectively.
The lsb and width of these new operands are the same as many existing
operands but the convention is to give different names to fields that
serve different purpose so we introduced new fields in aarch64-opc.c
and aarch64-opc.h.
We made a design choice for the second operand of the halfword variant of
luti4 with two register tables. We could have either defined a new operand,
like SVE_Znx2, or we could have use the existing operand SVE_ZnxN. With
the new operand, we would need to implement constraints on register
lists based on either operand or opcode flag. With existing operand, we
could just existing constraint checks using opcode flag. We chose
the second approach and went with SVE_ZnxN and added opcode flag to
enforce lengths of vector register list operands. This way, we can reuse
the existing constraint check logic.
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Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links:
* luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en
* luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en
These instructions needed definition of some new operands. We will first
discuss operands for the third operand of the instructions and then
discuss a vector register list operand needed for the second operand.
The third operands are vectors with bit indices and without type
qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12
and they have 1 bit, 2 bit, and 3 bit indices respectively. For these
new operands, we defined new parsing case branch. The lsb and width of
these operands are the same as many existing but the convention is to
give different names to fields that serve different purpose so we
introduced new fields in aarch64-opc.c and aarch64-opc.h for these new
operands.
For the second operand of these instructions, we introduced a new
operand called LVn_LUT. This represents a vector register list with
stride 1. We defined new inserter and extractor for this new operand and
it is encoded in FLD_Rn. We are enforcing the number of registers in the
reglist using opcode flag rather than operand flag as this is what other
SIMD vector register list operands are doing. The disassembly also uses
opcode flag to print the correct number of registers.
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PR 31796
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As already suggested during review, rather than having an extra
conditional in build_modrm_byte() (a code path used for quite a few
more insns, including even certain GPR ones), adjust the attribute in
the installed template to properly describe things with operands
swapped.
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These run after template matching. Therefore operands are already known
to match the template in use. With the loop bodies skipping anything not
a GPR in the actual operands, there's therefore no need to check the
template's operand type for permitting Reg or Accum.
At the same time bring the three functions in sync for the "byte" part
of the logic, as far as checking the template for other sizes (qword
specifically) goes. Plus drop a stale comment from check_qword_reg(),
when all three are now behaving the same in this regard.
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Properly reject inappropriate suffixes (No_lSuf / No_qSuf mistakenly
omitted by cf665fee1d6c ["x86: re-work AVX512 embedded rounding / SAE"]),
to avoid emitting bad or arbitrarily guessed instructions. Interestingly
check_{long,qword}_suffix() don't help here, which perhaps is another
indication that the way they work right now isn't quite appropriate.
Sadly correcting just the templates breaks operand ambiguity detection,
since so far that worked from a single template permitting more than one
suffix. Here we have ambiguity though which can now be noticed only when
taking all (matching) templates together. Therefore we need to determine
further matching templates (see code comments for constraints), to then
accumulate permitted suffixes across all of them.
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This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc.
Since the spec only recommends one form of setzu, I won't be adding
set<cc>reg32/reg64 support in this patch.
gas/ChangeLog:
* config/tc-i386.c (build_apx_evex_prefix): Handle ZU.
* testsuite/gas/i386/x86-64.exp: Added new tests for ZU.
* testsuite/gas/i386/x86-64.exp: Added new tests for ZU.
* testsuite/gas/i386/x86-64-apx-zu-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto.
* testsuite/gas/i386/x86-64-apx-zu.d: Ditto.
* testsuite/gas/i386/x86-64-apx-zu.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~
PREFIX_EVEX_MAP4_4F.
* i386-dis-evex.h: Ditto.
* i386-dis.c (struct dis386): Add new micro 'ZU'.
(putop): Handle %ZU.
* i386-gen.c: Added ZU.
* i386-opc.h: Ditto.
* i386-opc.tbl: Added new templates to support ZU.
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Resulting code will do better without the extra conditional branch.
Remove "i.rex" to eliminate extra conditional branch.
gas/ChangeLog:
* config/tc-i386.c (establish_rex): Remove i.rex.
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Since APX supports EVEX from legacy instructions, we need to check
the 8-bit old registers in EVEX format. And add test cases for it.
gas/ChangeLog:
* config/tc-i386.c (md_assemble): Add invalid check for old byte
registers in EVEX format.
* testsuite/gas/i386/x86-64-apx-inval.l: Add new test.
* testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
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Split "REX/REX2 old register checking" and "add empty rex prefix"
into two separate branches.
gas/ChangeLog:
* config/tc-i386.c (establish_rex): Split the judgments.
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With BFD not supporting that target anymore, GAS can't possibly support
it either.
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to DW_CFA_def_cfa
The DWARF specification (especially, DWARF4 and 5 [1,2]) states that
DW_CFA_def_cfa_register cannot be used as the first CFI operation.
It said DW_CFA_def_cfa_register as follows:
... This operation is valid only if the current CFA rule is defined
to use a register and offset.
So, DW_CFA_def_cfa_register can be used after that other definition
operation such as DW_CFA_def_cfa is called. However, the current gas
code emits DW_CFA_def_cfa_register as an initial CFI operation for RISCV.
In the libgcc, the unwinding function does not care about it, so it can
unwind the call stack. However, on the third party library such as
libunwindstack in Android, it causes a fatal error.
This patch changes the initial CFI operation to DW_CFA_def_cfa with
offset 0. It works as same as the previous one, but it does not have
any limitation so it satisfies the DWARF spec. This change resolves
the compatibility issue while preserving the original behaviour.
[1] DWARF4 specification, https://dwarfstd.org/doc/DWARF4.pdf
[2] DWARF5 specification, https://dwarfstd.org/doc/DWARF5.pdf
Signed-off-by: Sung-hun Kim <sfoon.kim@samsung.com>
Reviewed-By: Andrew Burgess <aburgess@redhat.com>
Approved-By: Nelson Chu <nelson@rivosinc.com>
gas/
PR 31733
config/tc-riscv.c (riscv_cfi_frame_initial_instructions): Use
DW_CFA_def_cfa rather than DW_CFA_def_cfa_register.
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Set DWARF2_CIE_DATA_ALIGNMENT (data alignment factors) to -8.
It helps to save space.
Data Alignment Factor
A signed LEB128 encoded value that is factored out of all offset
instructions that are associated with this CIE or its FDEs. This value
shall be multiplied by the register offset argument of an offset
instruction to obtain the new offset value.
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This hunk of code in move_or_literal_pool just looks wrong, but I
can't find a testcase that will tickle it to prove it. It looks a bit
like it was intended to catch cases where a bignum contained a
floating-point value, but there were a number of problems with it.
- It tested X_add_number == -1, but an FP bignum is indicated by any
value <= 0.
- It converted the floating-point value to extended precision, but
that's not used on Arm beyond the legacy FPA code. No attempt was
made to match the FP value to the intended memory/mov operation.
Since I can't construct a viable testcase, I've just removed the existing
code and made the function error out in this case: this seems more sensible
than generating wrong code or trying to write something more complex that
can't be tested anyway.
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We should revisit sysreg feature enablement and dependencies in future, but
this change should help until then.
OK for master?
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This matches the existing behaviour in GCC and LLVM, and also the current
documentation.
OK for master?
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Delete all the Maverick instructions and register handling from the
assembler. We continue to recognize -mcpu=ep9312, but treat it as an
alias for arm920t. We no-longer recognize -mfpu=maverick.
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gas/ChangeLog:
* config/tc-i386.c (build_modrm_byte): Dropped the use of
extension_opcode to encode the vvvv register.
* testsuite/gas/i386/x86-64-sse2avx.d: Added new testcases.
* testsuite/gas/i386/x86-64-sse2avx.s: Diito.
opcodes/ChangeLog:
* i386-opc.tbl: Added DstVVVV to some extension_opcode instructions.
* i386-tbl.h: Regenerated.
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gas/ChangeLog:
* config/tc-i386.c (build_modrm_byte): Dropped the use of
SWAP_SOURCES to encode the vvvv register.
opcodes/ChangeLog:
* i386-opc.h (SWAP_SOURCES): Dropped.
(NO_DEFAULT_MASK): Adjusted the value.
(ADDR_PREFIX_OP_REG): Ditto.
(DISTINCT_DEST): Ditto.
(IMPLICIT_STACK_OP): Ditto.
(VexVVVV_SRC2): New.
* i386-opc.tbl: Dropped SwapSources and replaced its VexVVVV
with Src1VVVV.
* i386-tbl.h: Regenerated.
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Use vexvvvv as the switch state, and replace VexVVVV with Src1VVVV.
Src1VVVV means using VEX.vvvv encodes the first source register
operand. The old logic did not check vexvvvv first, which made the
logic here very complicated.
gas/ChangeLog:
* config/tc-i386.c (optimize_encoding): Replaced 1 with Src1VVVV.
(build_modrm_byte): Used vexvvvv to encode the vvvv register.
(s_insn): Replaced 1 with Src1VVVV.
opcodes/ChangeLog:
* i386-opc.h (VexVVVV_DST): Adjusted the value.
(Src1VVVV): New.
* i386-opc.tbl: Replaced part VexVVVV with Src1VVVV.
* i386-tbl.h: Regenerated.
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Legacy encoded SIMD insns are converted to AVX ones in that mode. When
eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where
available; there are quite a few which can't be converted).
Note that LDDQU is represented as VMOVDQU32 (and the prior use of the
sse3 template there needs dropping, to get the order right).
Note further that in a few cases, due to the use of templates, AVX512VL
is used when AVX512F would suffice. Since AVX10 is the main reference,
this shouldn't be too much of a problem.
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In certain cases we were calculating the jump displacement incorrectly
when deciding whether to relax a branch. This meant for some branches,
such as a very long backwards conditional branch, relaxation was not
done when it should have been. The result was to error later, because
the actual jump displacement was too large to fit in the original
instruction.
This patch fixes up the displacement calculation so that those branches
are correctly relaxed and no longer result in an error. In addition, it
changes md_convert_frag to install fixups for the JAL instructions in
the resulting relaxations rather than encoding the displacement value
directly.
gas/
* config/tc-bpf.c (relaxed_branch_length): Correct displacement
calculation when relaxing.
(md_convert_frag): Likewise. Install fixups for JAL
instructions resulting from relaxation.
* testsuite/gas/bpf/jump-relax-ja-be.d: Correct and expand test.
* testsuite/gas/bpf/jump-relax-ja.d: Likewise.
* testsuite/gas/bpf/jump-relax-ja.s: Likewise.
* testsuite/gas/bpf/jump-relax-jump-be.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump.s: Likewise.
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Gas should not emit ADD/SUB relocation pairs for label differences
if they are in the same section without code flag even relax enabled.
Because the real value is not be affected by relaxation and it can be
compute out in assembly stage. Thus, correct the `TC_FORCE_RELOCATION
_SUB_SAME` and the label differences in same section without code
flag can be resolved in fixup_segment().
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gas/ChangeLog:
* config/tc-i386.c (build_apx_evex_prefix): Added invalid check for APX
X4.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added invalid
testcase.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (get_valid_dis386): Added invalid check for APX X4.
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Ignore .align at the start of a section may result in misalignment when
partial linking. Manually add -mignore-start-align option without partial
linking.
Gcc -falign-functions add .align 5 to the start of a section, it causes some
error message mismatch. Set these testcases to xfail on LoongArch target.
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Fix a memory leak in md_assemble where copy may be cleared and may be
the same as copy:
if (copy && !mnem_suffix)
{
line = copy;
copy = NULL;
no_match:
* config/tc-i386.c (md_assemble): Properly free the xstrdup
memory.
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Use long NOPs for Intel Core processors since they are faster than
multiple NOPs. Don't use them for 64-bit processors by default since
Intel Atom processors can only decode 4 prefixes in 1 cycle.
* config/tc-i386.c (alt64_9): New.
(alt64_10): Likewise.
(alt64_11): Likewise.
(alt64_12): Likewise.
(alt64_13): Likewise.
(alt64_14): Likewise.
(alt64_15): Likewise.
(alt64_patt): Likewise.
(i386_generate_nops): Use alt64_patt for Intel Core processors
in 64-bit mode.
* testsuite/gas/i386/x86-64-nops-1-core2.d: Expect long NOPs.
* testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Replace
../x86-64-nops-1.d with ../x86-64-nops-1-core2.d.
* testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Replace
../x86-64-nops-4.d with ../x86-64-nops-4-core2.d.
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As it stands, these insns are incorrectly encoded as vqrshr[u]n.
Concretely, the problem can be seen as follows:
$ cat t.s
vqrshrnb.s16 q0,q0,#8
vqshrnb.s16 q0,q0,#8
$ gas/as-new t.s -march=armv8.1-m.main+mve -o t.o
$ binutils/objdump -d t.o -m armv8.1-m.main
t.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <.text>:
0: ee88 0f41 vqrshrnb.s16 q0, q0, #0
4: ee88 0f41 vqrshrnb.s16 q0, q0, #0
Here we assemble these two instructions to the same opcode. The
encoding of the first is the correct, while the encoding of the second
is incorrect, and the bottom bit should be clear, see the Armv8-M ARM:
https://developer.arm.com/documentation/ddi0553/latest/
There is an additional problem here in that the disassembly of the
immediate is incorrect. llvm-objdump shows the correct disassembly
here:
t.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <$t>:
0: ee88 0f41 vqrshrnb.s16 q0, q0, #8
4: ee88 0f41 vqrshrnb.s16 q0, q0, #8
Note that we defer adding a test for the correct encoding of these insns
until the next patch which fixes the disassembly issue.
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Support zcmp extension push/pop/popret and popret zero instructions.
The `reg_list' is a list containing 1 to 13 registers, we can use:
"{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}"
to present this feature.
Passed gcc/binutils regressions of riscv-gnu-toolchain.
Most of work was finished by Sinan Lin.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp.
(riscv_supported_std_z_ext): Added zcmp with version 1.0.
(riscv_parse_check_conflicts): Zcmp conflicts with d/zcd.
(riscv_multi_subset_supports): Handle zcmp.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* config/tc-riscv.c (regno_to_reg_list): New function, used to map
register to reg_list number.
(reglist_lookup): Called reglist_lookup_internal. Return false if
reg_list number is zero, which is an invalid value.
(reglist_lookup_internal): Parse register list, and return the last
register by regno_to_reg_list.
(validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/march-help.l: Updated.
* testsuite/gas/riscv/zcmp-push-pop-fail.d: New test.
* testsuite/gas/riscv/zcmp-push-pop-fail.l: New test.
* testsuite/gas/riscv/zcmp-push-pop-fail.s: New test.
* testsuite/gas/riscv/zcmp-push-pop.d: New test.
* testsuite/gas/riscv/zcmp-push-pop.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp.
(MATCH/MASK_CM_POP): Ditto.
(MATCH/MASK_CM_POPRET): Ditto.
(MATCH/MASK_CM_POPRETZ): Ditto.
(DECLARE_INSN): New declarations for zcmp.
* opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm
operand for zcmp.
(OP_MASK_REG_LIST): Handle operand for zcmp register list.
(OP_SH_REG_LIST): Ditto.
(ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base.
(X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers.
(enum riscv_insn_class): Added INSN_CLASS_ZCMP.
(extern riscv_get_sp_base): Added.
opcodes/ChangeLog:
* riscv-dis.c (print_reg_list): New function, used to get zcmp
reg_list field.
(riscv_get_spimm): New function, used to get zcmp sp adjustment
immediate.
(print_insn_args): Handle new operands for zcmp.
* riscv-opc.c (riscv_get_sp_base): New function, used by gas and
objdump. Get sp base adjustment.
(riscv_opcodes): Added zcmp instructions.
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For the case when NDD and NF are both 0 in evex-promoted format,
we will fully support and test it in another patch.
gas/ChangeLog:
* NEWS: Support Intel APX NF.
* config/tc-i386.c (enum i386_error): Add unsupported_nf.
(struct _i386_insn): Add has_nf.
(is_apx_evex_encoding): Ditto.
(build_apx_evex_prefix): Encode the NF bit.
(md_assemble): Handle unsupported_nf.
(parse_insn): Handle Prefix_NF and report bad for illegal combination.
(can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf.
(match_template): Support D for APX_F insns and check NF support.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
* testsuite/gas/i386/x86-64-apx-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add apx nf tests.
* testsuite/gas/i386/x86-64-apx-nf-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-nf.d: Ditto.
* testsuite/gas/i386/x86-64-apx-nf.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex.h: Add %NF to the instructions that support APX NF and
add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table.
* i386-dis-evex-reg.h: Ditto.
* i386-dis.c (struct instr_info): Add nf.
(struct dis386): Add "NF" for EVEX.NF.
(get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case.
(print_insn): Handle ins.vex.nf.
(putop): Handle "%NF".
* i386-opc.h (Prefix_NF): New.
* i386-opc.tbl: Added new entries to support full APX NF instructions.
* i386-mnem.h: Regenerated.
* i386-tbl.h: Regenerated.
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APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4.
https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html
gas/ChangeLog:
* NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX
* MAP4.
* config/tc-i386.c (process_operands): Removed special handling of
* KEYLOCKER and SHA.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER
* and SHA instructions.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions.
* i386-dis-evex.h: Ditto.
* i386-opc.tbl: Ditto.
* i386-dis.c (print_vector_reg): Removed special handling of KEYLOCKER
* and SHA.
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Ignore .align if it is at the start of a section and the alignment
can be divided by the section alignment, the section alignment
can ensure this .align has a correct alignment.
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To represent the first and third expression of .align, R_LARCH_ALIGN need to
associate with a symbol. We define a local symbol for R_LARCH_AGLIN.
But if the section of the local symbol is discarded, it may result in
a undefined symbol error.
Instead, we use the section name symbols, and this does not need to
add extra symbols.
During partial linking (ld -r), if the symbol associated with a relocation is
STT_SECTION type, the addend of relocation needs to add the section output
offset. We prevent it for R_LARCH_ALIGN.
The elf_backend_data.rela_normal only can set all relocations of a target to
rela_normal. Add a new function is_rela_normal to elf_backend_data, it can
set part of relocations to rela_normal.
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It has always been looking a little odd to me that this was done deep
in cpu_flags_match(). Move it to match_template() itself - there's no
need to do anything complex when encountering such a template while it
cannot possibly be used.
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1) Without -msse2avx we unconditionally honor REX.W. Hence we ought to
also do so with -msse2avx, converting to VEX.W.
2) {rex} doesn't prevent conversion to VEX encodings. Thus {rex2}
shouldn't either.
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Removed since it's may have lots of conflicts with the newer extensions, but
still keep linker recognizes it in case of linking old objects.
gas/
* NEWS: Updated.
* config/tc-riscv.c (riscv_set_default_priv_spec): Regard 1.9.1 as
an unknown version.
(md_show_usage): Removed privileged spec 1.9.1 information.
* testsuite/gas/riscv/attribute-05.s: Updated since privileged spec
1.9.1 is unsupported.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-12.d: Likewise.
* testsuite/gas/riscv/attribute-13.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/csr.s: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Removed.
* testsuite/gas/riscv/csr-version-1p9p1.l: Removed.
include/
* opcode/riscv-opc.h: Updated since privileged spec 1.9.1 is
unsupported.
ld/
* testsuite/ld-riscv-elf/attr-merge-priv-spec-01.d: Updated since
privileged spec 1.9.1 is unsupported.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
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For one 0afc614c9938 ("x86: Warn .insn instruction with length > 15
bytes") introduced a .insn use involving a slash; such tests need to
have --divide passed to gas.
And then 5bc71c2a6b8e ("x86-64: Add R_X86_64_CODE_6_GOTTPOFF") broke
BFD_RELOC_X86_64_GOTTPOFF conversion to R_X86_64_CODE_4_GOTTPOFF, by
adding respective code in a section guarded by
generate_relax_relocations (the case of that not being required there
was limited to 32-bit object files). Re-arrange that block of code to
check generate_relax_relocations later.
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This relaxation is effective for both macro instructions (call36, tail36)
and explicit relocation instructions (pcaddu18i + jirl).
call36 f -> bl f
R_LARCH_CALL36 -> R_LARCH_B26
tail36 $t0, f -> b f
R_LARCH_CALL36 -> R_LARCH_B26
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The following instructions are added in this patch:
- ADDPT and SUBPT - Add/Subtract checked pointer
- MADDPT and MSUBPT - Multiply Add/Subtract checked pointer
These instructions are part of Checked Pointer Arithmetic extension.
This patch adds assembler and disassembler support for these instructions
with relevant checks. Tests are included as well.
A new flag "+cpa" added to documentation. This flag enables CPA extension.
Regression tested on the aarch64-none-linux-gnu target and no regressions
have been found.
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Irrespective of the encoding being EVEX, the usable SIMD register range
continues to be limited to %xmm0-%xmm15. Enforce this in gas (but
continue to generate code, as in principle we know how to encode
things) and recognize/flag the case in the disassembler.
Oddly enough wrong forms were actually used in the testsuite (register-
only forms are then really meaningless to test here, and are hence
dropped instead of adjusted).
Convert the POP2 test that needs touching anyway (due to a bad ModR/M
byte having been chosen) to .insn.
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Use -march=help for gas to print all supported extensions and versions.
Here is part of the output of `as -march=help`:
All available -march extensions for RISC-V:
e 1.9
i 2.1, 2.0
m 2.0
a 2.1, 2.0
f 2.2, 2.0
d 2.2, 2.0
q 2.2, 2.0
c 2.0
v 1.0
h 1.0
zicbom 1.0
zicbop 1.0
...
This patch assumes that the supported extensions with the same versions
are listed together. For example:
static struct riscv_supported_ext riscv_supported_std_ext[] =
{
...
{"i", ISA_SPEC_CLASS_20191213, 2, 1, 0 },
{"i", ISA_SPEC_CLASS_20190608, 2, 1, 0 },
{"i", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
...
};
For the "i" extension, 2.1.0 with different spec class are listed together.
This patch records the previous printed extension and version. If the
current extension and version are the same as the previous one, skip
printing.
bfd/
* elfxx-riscv.c (riscv_print_extensions): New function. Print
available extensions and versions.
* elfxx-riscv.h (riscv_print_extensions): New declaration.
gas/
* gas/config/tc-riscv.c (md_parse_option): Parse 'help' keyword in
-march option to print available extensions and versions.
* testsuite/gas/riscv/march-help.l: New testcase for -march=help.
* testsuite/gas/riscv/riscv.exp: Updated.
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Currently, gas will exit immediately and report an error when
it sees illegal operands, and will not process the remaining
instructions. Replace as_fatal with as_bad to check for all
illegal operands.
Add test cases for illegal operands of some instructions.
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Some of these have no explicit %xmm operand(s), yet they still act SSE-
like (in leaveing bits 128 and up untouched). Hence they want similarly
diagnosing, if that was asked for.
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These aren't useful, but can be encoded for their AVX forms and hence
should also be permitted for the APX surrogates. Extend the respective
conditional by a base opcode check, to restrict it to VROUND{P,S}{S,D}.
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