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2021-04-01Use startswith in gas subfolder.Martin Liska1-6/+5
gas/ChangeLog: * as.c (select_emulation_mode): Use startswith. * config/m68k-parse.y: Likewise. * config/obj-aout.c (obj_aout_type): Likewise. * config/obj-elf.c (elf_common_parse): Likewise. (obj_elf_section_type): Likewise. (obj_elf_section_word): Likewise. (obj_elf_section): Likewise. (obj_elf_symver): Likewise. (adjust_stab_sections): Likewise. * config/obj-evax.c (evax_shorten_name): Likewise. * config/obj-macho.c (obj_mach_o_is_frame_section): Likewise. * config/tc-aarch64.c (parse_aarch64_imm_float): Likewise. (aarch64_parse_features): Likewise. (create_register_alias): Likewise. (aarch64_data_in_code): Likewise. (md_parse_option): Likewise. * config/tc-alpha.c (s_alpha_section_word): Likewise. (s_alpha_pdesc): Likewise. * config/tc-arc.c (tokenize_extregister): Likewise. * config/tc-arm.c (create_register_alias): Likewise. (create_neon_reg_alias): Likewise. (parse_ifimm_zero): Likewise. (parse_qfloat_immediate): Likewise. (arm_elf_section_type): Likewise. (arm_parse_extension): Likewise. (aeabi_set_public_attributes): Likewise. (s_arm_arch_extension): Likewise. (arm_data_in_code): Likewise. (start_unwind_section): Likewise. * config/tc-avr.c (avr_ldi_expression): Likewise. * config/tc-csky.c (is_freglist_legal): Likewise. (csky_s_section): Likewise. * config/tc-d30v.c (do_assemble): Likewise. * config/tc-dlx.c (parse_operand): Likewise. * config/tc-epiphany.c (md_assemble): Likewise. * config/tc-h8300.c (h8300_elf_section): Likewise. (get_operand): Likewise. * config/tc-hppa.c (pa_ip): Likewise. (pa_level): Likewise. (pa_space): Likewise. * config/tc-i386.c (i386_mach): Likewise. (md_assemble): Likewise. (check_VecOperations): Likewise. (i386_target_format): Likewise. (i386_elf_section_type): Likewise. * config/tc-ia64.c (start_unwind_section): Likewise. (md_parse_option): Likewise. (is_taken_branch): Likewise. (idesc->name,): Likewise. (note_register_values): Likewise. (do_alias): Likewise. * config/tc-m32c.c (insn_to_subtype): Likewise. * config/tc-m68hc11.c (get_operand): Likewise. (md_assemble): Likewise. * config/tc-m68k.c (m68k_ip): Likewise. (m68k_elf_suffix): Likewise. * config/tc-mcore.c (mcore_s_section): Likewise. * config/tc-metag.c (parse_get_set): Likewise. (md_parse_option): Likewise. * config/tc-microblaze.c (parse_imm): Likewise. (check_got): Likewise. (md_apply_fix): Likewise. * config/tc-mips.c (CPU_HAS_MIPS16): Likewise. (md_begin): Likewise. (s_is_linkonce): Likewise. (check_regno): Likewise. (match_float_constant): Likewise. (classify_vr4120_insn): Likewise. (match_insn): Likewise. (mips_after_parse_args): Likewise. (s_change_sec): Likewise. (s_option): Likewise. (parse_code_option): Likewise. (md_section_align): Likewise. (nopic_need_relax): Likewise. * config/tc-mmix.c (mmix_handle_mmixal): Likewise. * config/tc-mn10300.c (mn10300_fix_adjustable): Likewise. (mn10300_end_of_match): Likewise. * config/tc-msp430.c (msp430_make_init_symbols): Likewise. * config/tc-nds32.c (nds32_parse_option): Likewise. * config/tc-nds32.h (md_do_align): Likewise. * config/tc-nios2.c (strprefix): Likewise. (nios2_special_relocation_p): Likewise. (nios2_parse_base_register): Likewise. (nios2_cons): Likewise. * config/tc-ns32k.c (addr_mode): Likewise. * config/tc-pdp11.c (set_option): Likewise. (parse_reg): Likewise. (parse_ac5): Likewise. (parse_op_no_deferred): Likewise. (set_cpu_model): Likewise. (set_machine_model): Likewise. * config/tc-pj.c (md_operand): Likewise. * config/tc-ppc.c (ppc_set_cpu): Likewise. (ppc_arch): Likewise. (ppc_section_type): Likewise. * config/tc-s12z.c (tb_reg_rel): Likewise. (tb_opr_rel): Likewise. * config/tc-s390.c (s390_parse_cpu): Likewise. (md_parse_option): Likewise. * config/tc-score.c (s3_nopic_need_relax): Likewise. (s3_pic_need_relax): Likewise. * config/tc-score7.c (s7_nopic_need_relax): Likewise. (s7_pic_need_relax): Likewise. * config/tc-sh.h (SUB_SEGMENT_ALIGN): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. (sparc_ip): Likewise. (s_reserve): Likewise. (s_common): Likewise. (s_seg): Likewise. (sparc_cons): Likewise. * config/tc-tic54x.c (stag_add_field): Likewise. (tic54x_endstruct): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * config/tc-v850.c (v850_comm): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-vax.c (vax_cons): Likewise. * config/tc-wasm32.c (wasm32_leb128): Likewise. * config/tc-xstormy16.c (md_operand): Likewise. * config/tc-xtensa.c (get_directive): Likewise. (xg_instruction_matches_option_term): Likewise. (is_unaligned_label): Likewise. (cache_literal_section): Likewise. * config/xtensa-relax.c (parse_precond): Likewise. (parse_option_cond): Likewise. (transition_applies): Likewise. (wide_branch_opcode): Likewise. * dw2gencfi.c: Likewise. * dwarf2dbg.c (dwarf2_directive_filename): Likewise. * ehopt.c (get_cie_info): Likewise. * input-file.c (input_file_open): Likewise. * listing.c (listing_newline): Likewise. (debugging_pseudo): Likewise. * read.c (read_a_source_file): Likewise. * write.c (adjust_reloc_syms): Likewise. (compress_debug): Likewise. (maybe_generate_build_notes): Likewise.
2021-03-31Use bool in gasAlan Modra1-204/+204
* as.h (POISON_BFD_BOOLEAN): Define. * as.c, * as.h, * atof-generic.c, * config/atof-ieee.c, * config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h, * config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c, * config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c, * config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c, * config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h, * config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c, * config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h, * config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c, * config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h, * config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c, * config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h, * config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c, * config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h, * config/tc-metag.c, * config/tc-metag.h, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c, * config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h, * config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c, * config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h, * config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h, * config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c, * config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c, * config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h, * config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c, * config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xstormy16.h, * config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c, * config/tc-z8k.c, * config/xtensa-istack.h, * config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c, * dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c, * frags.h, * listing.c, * macro.c, * output-file.c, * read.c, * read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true.
2021-03-31Remove bfd_stdint.hAlan Modra1-1/+1
If we require C99 for binutils then stdint.h is available. bfd/ * .gitignore: Delete bfd_stdint.h entry. * Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h. (BUILD_HFILES, LOCAL_H_DEPS): Likewise. * bfd-in.h: Include stdint.h in place of bfd_stdint.h. * configure.ac: Don't invoke GCC_HEADER_STDINT. * configure.com: Don't create bfd_stdint.h. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in2.h: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. binutils/ * coffdump.c: Include stdint.h in place of bfd_stdint.h. * dwarf.c: Likewise. gas/ * config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h. * config/tc-crx.c: Likewise. * config/tc-nds32.h: Likewise. include/ * cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h. * elf/nfp.h: Likewise. * opcode/aarch64.h: Likewise. * opcode/cgen.h: Likewise. * opcode/nfp.h: Likewise. * opcode/ppc.h: Likewise. ld/ * elf-hints-local.h: Include stdint.h in place of bfd_stdint.h. * emultempl/nds32elf.em: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise. * testsuite/ld-elf/pr18718.c: Likewise. * testsuite/ld-elf/pr18720a.c: Likewise. * testsuite/ld-elf/pr25749-1.c: Likewise. * testsuite/ld-elf/pr25749-1a.c: Likewise. * testsuite/ld-elf/pr25749-1b.c: Likewise. * testsuite/ld-elf/pr25749-1c.c: Likewise. * testsuite/ld-elf/pr25749-1d.c: Likewise. * testsuite/ld-elf/pr25749-2.c: Likewise. * testsuite/ld-elf/pr25754-1a.c: Likewise. * testsuite/ld-elf/pr25754-2a.c: Likewise. * testsuite/ld-elf/pr25754-3a.c: Likewise. * testsuite/ld-elf/pr25754-4a.c: Likewise. * testsuite/ld-elf/pr25754-5a.c: Likewise. * testsuite/ld-elf/pr25754-6a.c: Likewise. opcodes/ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. * aarch64-dis.h: Likewise. * aarch64-opc.c: Likewise. * avr-dis.c: Likewise. * csky-dis.c: Likewise. * nds32-asm.c: Likewise. * nds32-dis.c: Likewise. * nfp-dis.c: Likewise. * riscv-dis.c: Likewise. * s12z-dis.c: Likewise. * wasm32-dis.c: Likewise.
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-31/+0
This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-23aarch64: Add support for Cortex-A78CPrzemyslaw Wirkus1-0/+9
This patch adds support for -mcpu=cortex-a78c command line option. For more information about this processor, see [0]: [0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
2020-11-16aarch64: Add +pauth flag for Pointer Authentication featurePrzemyslaw Wirkus1-0/+2
New -march option +pauth enables PAuth vel PAC (Pointer Authentication) feature.
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus1-0/+2
Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A. Please note that FLAGM stays a Armv8.4-A feature but now can be assigned to other architectures or CPUs. New -march option +flagm is added to enable independently this feature.
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus1-1/+2
This patch: + Adds new ACCDATA_EL1 (Accelerator Data) system register, see [0]. + Adds LS64 instruction tests. + Update LS64 feature test with new register. + Fix comment for AARCH64_OPND_Rt_LS64. [0] https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/accdata_el1 Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default).
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+16
Atomic 64-byte load/store instructions limit Rt register number to values matching below condition (register <Xt> number must be even and <= 22): if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED; This patch adds check if Rt fulfills above requirement. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-0/+2
Armv8.7 architecture introduces the "accelerator extension", aka load/store of 64 bytes. New atomic load/store instructions are: LD64B, ST64B, ST64BV and ST64BV0. This patch adds: + New feature +ls64 to -march command line. + New atomic load/store instructions associated with above feature. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i
2020-10-29aarch64: Fix DSB instruction 'missing immediate expression' errorsPrzemyslaw Wirkus1-1/+5
This patch fixes errors with DSB instruction after introduction of DSB nXS variant. That change would cause GAS to reject valid DSB immediate string operands. gas/ChangeLog: 2020-10-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-aarch64.c (parse_operands): Check for C0-C15 value of DSB immediate string operand. * testsuite/gas/aarch64/system-4.d: Update test. * testsuite/gas/aarch64/system-4.s: Update test.
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-0/+31
This patch adds: + New feature +csre to -march command line. + New instruction CSR PDEC associated with CSRE feature. Please note that CSRE system registers were already upstreamed. This patch should finalize CSRE feature implementation. CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of a Call stack record) instruction. Although this instruction has operand (PDEC) it's instruction's only operand. PDEC forces instruction field Rt to be set to 0b1111. This results in fixed opcode of the instruction. gas/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * config/tc-aarch64.c (parse_csr_operand): New operand parser. (parse_operands): Call to CSR operand parser. * testsuite/gas/aarch64/csre_csr-invalid.d: New test. * testsuite/gas/aarch64/csre_csr-invalid.l: New test. * testsuite/gas/aarch64/csre_csr-invalid.s: New test. * testsuite/gas/aarch64/csre_csr.d: New test. * testsuite/gas/aarch64/csre_csr.s: New test. include/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature. (enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out. * aarch64-tbl.h (CSRE): New CSRE feature handler. (_CSRE_INSN): New CSRE instruction type. (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-0/+47
This patch adds new variant (nXS) of DSB memory barrier instruction available in Armv8.7-a. New nXS variant has different encoding in comparison with pre Armv8.7-a DSB memory barrier variant thus new instruction and new operand was added. DSB memory nXS barrier variant specifies the limitation on the barrier operation. Allowed values are: DSB SYnXS|#28 DSB ISHnXS|#24 DSB NSHnXS|#20 DSB OSHnXS|#16 Please note that till now, for barriers, barrier operation was encoded in 4-bit unsigned immediate CRm field (in the range 0 to 15). For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned assembly instruction immediate, encoded in instruction in two bits CRm<3:2>: CRm<3:2> #imm 00 16 01 20 10 24 11 28 This patch extends current AArch64 barrier instructions with above mapping. Notable patch changes include: + New DSB memory barrier variant encoding for Armv8.7-a. + New operand BARRIER_DSB_NXS for above instruction in order to distinguish between existing and new DSB instruction flavour. + New set of DSB nXS barrier options. + New instruction inserter and extractor map between instruction immediate 5-bit value and 2-bit CRm field of the instruction itself (see FLD_CRm_dsb_nxs). + Regeneration of aarch64-[asm|dis|opc]-2.c files. + Test cases to cover new instruction assembling and disassembling. For more details regarding DSB memory barrier instruction and its Armv8.7-a flavour please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 132-133 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (parse_operands): Add AARCH64_OPND_BARRIER_DSB_NXS handler. (md_begin): Add content of aarch64_barrier_dsb_nxs_options to aarch64_barrier_opt_hsh hash. * testsuite/gas/aarch64/system-4-invalid.d: New test. * testsuite/gas/aarch64/system-4-invalid.l: New test. * testsuite/gas/aarch64/system-4-invalid.s: New test. * testsuite/gas/aarch64/system-4.d: New test. * testsuite/gas/aarch64/system-4.s: New test. include/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_BARRIER_DSB_NXS. (aarch64_barrier_dsb_nxs_options): Declare DSB nXS options. opcodes/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_barrier_dsb_nx. * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_barrier_dsb_nx. * aarch64-opc.c (aarch64_print_operand): New options table aarch64_barrier_dsb_nxs_options. * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs. * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier Armv8.7-a instruction. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus1-0/+1
This patch adds support for AArch64 -march=armv8.7-a command line option in GAS. Please note that this change ONLY extends -march= command line interface with a new "armv8.7-a" option. Architectural changes like new instructions will be added in following patches. gas/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (armv8.7-a): New arch. * doc/c-aarch64.texi (-march=armv8.7-a): Update docs. include/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask. (AARCH64_ARCH_V8_7): New arch feature set. opcodes/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (ARMV8_7): New macro.
2020-10-06aarch64: Fix bogus type punning in parse_barrier() [PR26699]Alex Coplan1-7/+1
This patch fixes a bogus use of type punning in parse_barrier() which was causing an assembly failure on big endian LP64 hosts when attempting to assemble "isb sy" for AArch64. The type of the entries in aarch64_barrier_opt_hsh is aarch64_name_value_pair. We were incorrectly casting this to the locally-defined asm_barrier_opt which has a wider type (on LP64) for the second member. This happened to work on little-endian hosts but fails on LP64 big endian. The fix is to use the correct type in parse_barrier(). This makes the locally-defined asm_barrier_opt redundant, so remove it. gas/ChangeLog: * config/tc-aarch64.c (asm_barrier_opt): Delete. (parse_barrier): Fix bogus type punning. * testsuite/gas/aarch64/system.d: Update disassembly. * testsuite/gas/aarch64/system.s: Add isb sy test.
2020-10-05[PATCH][GAS][AArch64] Update Cortex-X1 feature flagsPrzemyslaw Wirkus1-2/+6
This is feature flags update for Cortex-X1 CPU. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x gas/ChangeLog: 2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-aarch64.c: Update Cortex-X1 feature flags.
2020-09-30[GAS][AArch64] Add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+14
* config/tc-aarch64.c: Add Cortex-A78 and Cortex-A78AE cores. * doc/c-aarch64.texi: Update docs. * NEWS: Update news.
2020-09-30aarch64: Add support for Neoverse N2 CPUAlex Coplan1-0/+10
This patch adds support for Arm's Neoverse N2 CPU to AArch64 binutils. gas/ChangeLog: * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2. * doc/c-aarch64.texi: Document support for Neoverse N2.
2020-09-28This patch adds support for Cortex-X1Przemyslaw Wirkus1-0/+3
gas * config/tc-aarch64.c: (aarch64_cpus): Add Cortex-X1. * doc/c-aarch64.texi: Document -mcpu=cortex-x1.
2020-09-28aarch64: Neoverse V1 tweaksAlex Coplan1-8/+9
This simple follow-on patch groups the Neoverse cores together and adds a missing feature bit (F16) to the entry for Neoverse V1. gas/ChangeLog: * config/tc-aarch64.c (aarch64_cpus): Group Neoverse cores together, add missing F16 bit to Neoverse V1.
2020-09-24aarch64: Add support for Neoverse V1 CPUAlex Coplan1-0/+8
This adds support for Arm's Neoverse V1 CPU to AArch64 binutils. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_cpu_option_table): Add Neoverse V1. * doc/c-aarch64.texi: Document Neoverse V1 support.
2020-09-16Tidy elf_symbol_fromAlan Modra1-1/+1
bfd/ * elf-bfd.h (elf_symbol_from): Remove unused ABFD parameter. * elf.c (ignore_section_sym, _bfd_elf_copy_private_symbol_data), (swap_out_syms): Adjust elf_symbol_from invocation. binutils/ * nm.c (print_symbol): Adjust elf_symbol_from invocation. * objcopy.c (is_hidden_symbol): Likewise. gas/ * config/obj-elf.c (obj_elf_visibility, elf_frob_symbol): Adjust elf_symbol_from invocation. * config/tc-aarch64.c (s_variant_pcs): Likewise. * config/tc-m68hc11.c (s_m68hc11_mark_symbol): Likewise. * config/tc-ppc.c (ppc_elf_localentry, ppc_force_relocation), (ppc_fix_adjustable): Likewise. * config/tc-xgate.c (xgate_frob_symbol): Likewise. ld/ * plugin.c (asymbol_from_plugin_symbol): Adjust elf_symbol_from invocation. opcodes/ * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
2020-09-08aarch64: Add -mcpu option for Cortex-R82Alex Coplan1-0/+1
This adds support for the Arm Cortex-R82 CPU in AArch64 GAS. For more information about this processor, see [0]. [0] : https://developer.arm.com/ip-products/processors/cortex-r/cortex-r82 gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add Cortex-R82. * doc/c-aarch64.texi: Document -mcpu=cortex-r82.
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan1-4/+5
This patch adds support for the system registers introduced in Armv8-R AArch64. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to validation function. (parse_sys_ins_reg): Likewise. (print_operands): Pass CPU features to aarch64_print_operand(). * testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test. * testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output. * testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input. * testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test. * testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output. * testsuite/gas/aarch64/v8-r-sysregs.d: New test. * testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (aarch64_sys_ins_reg_supported_p): Also take system register name in order to simplify validation for v8-R. (aarch64_print_operand): Also take CPU feature set, as disassembly for system registers now depends on arch variant. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (print_operands): Pass CPU features to aarch64_print_operand(). * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine preferred disassembly of system registers. (SR_RNG): Refactor to use new SR_FEAT2 macro. (SR_FEAT2): New. (SR_V8_1_A): New. (SR_V8_4_A): New. (SR_V8_A): New. (SR_V8_R): New. (SR_EXPAND_ELx): New. (SR_EXPAND_EL12): New. (aarch64_sys_regs): Specify which registers are only on A-profile, add R-profile system registers. (ENC_BARLAR): New. (PRBARn_ELx): New. (PRLARn_ELx): New. (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for Armv8-R AArch64.
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan1-0/+1
This patch adds the basic infrastructure needed to support Armv8-R in AArch64 binutils: new command-line flags, new feature bits, a new BFD architecture, and support for differentiating between architecture variants in the disassembler. The new command-line options added by this patch are -march=armv8-r in GAS and -m aarch64:armv8-r in objdump. The disassembler support is necessary since Armv8-R AArch64 introduces a system register (VSCTLR_EL2) which shares an encoding with a different system register (TTBR0_EL2) in Armv8-A. This also allows us to use the correct preferred disassembly for the new DFB alias introduced in Armv8-R. bfd/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * archures.c (bfd_mach_aarch64_8R): New. * bfd-in2.h: Regenerate. * cpu-aarch64.c (bfd_aarch64_arch_v8_r): New. (bfd_aarch64_arch_ilp32): Update tail pointer. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_archs): Add armv8-r. * doc/c-aarch64.texi: Document -march=armv8-r. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_A): New. (AARCH64_FEATURE_V8_R): New. (AARCH64_ARCH_V8): Include new A-profile feature bit. (AARCH64_ARCH_V8_R): New. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (arch_variant): New. (determine_disassembling_preference): Disassemble according to arch variant. (select_aarch64_variant): New. (print_insn_aarch64): Set feature set.
2020-08-24Remove "memory exhausted" messagesAlan Modra1-16/+15
Since we use xcalloc to set up hash table memory, htab_create won't ever return a failure. * config/tc-aarch64.c (md_begin): Don't bother checking for out of memory failure from str_htab_create. * config/tc-arc.c (arc_insert_opcode, md_begin): Likewise. (arc_extcorereg, arc_stralloc): Likewise. * config/tc-arm.c (md_begin): Likewise. * config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise. * config/tc-cris.c (md_begin): Likewise. * config/tc-crx.c (md_begin): Likewise. * config/tc-pdp11.c (md_begin): Likewise. * config/tc-score.c (s3_build_reg_hsh, s3_begin): Likewise. * config/tc-score7.c (s7_build_reg_hsh, s7_begin): Likewise.
2020-08-23PR26513, 629310abec breaks assembling PowerPC Linux kernelsAlan Modra1-2/+2
Inserting with replacement is wrong for some gas hash table uses. This patch implements an htab_insert that conditionally replaces, and similarly for str_hash_insert. str_hash_insert with replace=0 is roughly equivalent to the older hash_insert, and str_hash_insert with replace=1 to the older hash_jam, but return values are different. I found it useful to know whether the slot was occupied prior to inserting/replacing. I've also reinstated the fatal errors on messing up opcode tables with duplicates. PR 26513 * hash.h (htab_insert): Update prototype and comment. (struct string_tuple): Make "value" a const void*. (string_tuple_alloc): Likewise. (str_hash_find, str_hash_find_n): Cast returned value. (str_hash_insert): Add "replace" parameter, and return slot pointer. Free alloc'd element when not inserted. * hash.c (htab_insert): Likewise. Return slot when element exists, otherwise return NULL. * read.c (pop_insert): Insert into hash table without first searching. * config/tc-avr.c (md_begin): Likewise. * config/tc-msp430.c (md_begin): Likewise. * config/tc-nds32.c (nds32_init_nds32_pseudo_opcodes): Likewise. * config/tc-v850.c (md_begin): Likewise. * macro.c (do_formals, define_macro, macro_expand_body): Likewise. (delete_macro): Delete from hash table. * config/tc-tic54x.c (subsym_create_or_replace): Correct logic. * symbols.c (local_symbol_make, symbol_table_insert): Allow replacement of hash table entries. * config/obj-coff-seh.c (seh_hash_insert): Likewise. * config/obj-coff.c (tag_insert): Likewise. * config/tc-iq2000.c (iq2000_add_macro): Likewise. * config/tc-m68k.c (md_begin): Likewise for aliases. * config/tc-tic4x.c (tic4x_asg): Likewise. * config/tc-tic6x.c (md_begin): Likewise. * dw2gencfi.c (dwcfi_hash_find_or_make): Disallow replacement of hash table entries. * ecoff.c (add_string, get_tag): Likewise. * macro.c (expand_irp): Likewise. * config/obj-elf.c (build_additional_section_info): Likewise. * config/tc-aarch64.c (insert_reg_alias): Likewise. (checked_hash_insert): Likewise. * config/tc-alpha.c (get_alpha_reloc_tag, md_begin): Likewise. * config/tc-arc.c (arc_insert_opcode, declare_register): Likewise. (declare_addrtype, md_begin, arc_extcorereg): Likewise. * config/tc-arm.c (insert_reg_alias): Likewise. (arm_tc_equal_in_insn, md_begin): Likewise. * config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise. * config/tc-cris.c (md_begin): Likewise. * config/tc-crx.c (md_begin): Likewise. * config/tc-csky.c (md_begin): Likewise. * config/tc-d10v.c (md_begin): Likewise. * config/tc-dlx.c (md_begin): Likewise. * config/tc-ft32.c (md_begin): Likewise. * config/tc-h8300.c (md_begin): Likewise. * config/tc-hppa.c (md_begin): Likewise. * config/tc-i386.c (md_begin): Likewise. * config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise. (md_begin, dot_alias): Likewise. * config/tc-m68hc11.c (md_begin): Likewise. * config/tc-m68k.c (md_begin): Likewise. * config/tc-mcore.c (md_begin): Likewise. * config/tc-microblaze.c (md_begin): Likewise. * config/tc-mips.c (md_begin): Likewise. * config/tc-mmix.c (md_begin): Likewise. * config/tc-mn10200.c (md_begin): Likewise. * config/tc-mn10300.c (md_begin): Likewise. * config/tc-moxie.c (md_begin): Likewise. * config/tc-nds32.c (nds32_relax_hint, md_begin): Likewise. * config/tc-nios2.c (md_begin): Likewise. * config/tc-ns32k.c (md_begin): Likewise. * config/tc-pdp11.c (md_begin): Likewise. * config/tc-pj.c (fake_opcode, md_begin): Likewise. * config/tc-ppc.c (ppc_setup_opcodes): Likewise. * config/tc-pru.c (md_begin): Likewise. * config/tc-riscv.c (init_ext_version_hash): Likewise. (init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise. (riscv_init_csr_hash): Likewise. * config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise. * config/tc-score.c (s3_insert_reg): Likewise. (s3_build_score_ops_hsh, s3_build_dependency_insn_hsh): Likewise. * config/tc-score7.c (s7_build_score_ops_hsh): Likewise. (s7_build_dependency_insn_hsh, s7_insert_reg): Likewise. * config/tc-sh.c (md_begin): Likewise. * config/tc-sparc.c (md_begin): Likewise. * config/tc-spu.c (md_begin): Likewise. * config/tc-tic30.c (md_begin): Likewise. * config/tc-tic4x.c (tic4x_inst_insert): Likewise. * config/tc-tic54x.c (stag_add_field_symbols, md_begin): Likewise. (tic54x_endstruct, tic54x_var, tic54x_macro_info): Likewise. (subsym_substitute): Likewise. * config/tc-tilegx.c (md_begin): Likewise. * config/tc-tilepro.c (md_begin): Likewise. * config/tc-vax.c (vip_begin): Likewise. * config/tc-wasm32.c (md_begin): Likewise. * config/tc-xgate.c (md_begin): Likewise. * config/tc-z8k.c (md_begin): Likewise. * testsuite/gas/ppc/dcbt.d, * testsuite/gas/ppc/dcbt.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. * ecoff.c (add_string): Report fatal error on duplicates. * config/tc-alpha.c (md_begin): Likewise. * config/tc-arc.c (arc_insert_opcode, declare_register): Likewise. (declare_addrtype, md_begin, arc_extcorereg): Likewise. * config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise. * config/tc-cris.c (md_begin): Likewise. * config/tc-crx.c (md_begin): Likewise. * config/tc-dlx.c (md_begin): Likewise. * config/tc-hppa.c (md_begin): Likewise. * config/tc-i386.c (md_begin): Likewise. * config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise. (md_begin): Likewise. * config/tc-m68k.c (md_begin): Likewise. * config/tc-mips.c (md_begin): Likewise. * config/tc-nios2.c (md_begin): Likewise. * config/tc-ns32k.c (md_begin): Likewise. * config/tc-ppc.c (ppc_setup_opcodes): Likewise. * config/tc-pru.c (md_begin): Likewise. * config/tc-riscv.c (init_ext_version_hash): Likewise. (init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise. * config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise. * config/tc-sparc.c (md_begin): Likewise. * config/tc-tic30.c (md_begin): Likewise. * config/tc-tic4x.c (tic4x_inst_insert): Likewise. * config/tc-tilegx.c (md_begin): Likewise. * config/tc-tilepro.c (md_begin): Likewise. * config/tc-vax.c (vip_begin): Likewise. * config/tc-alpha.c, * config/tc-arm.c, * config/tc-avr.c, * config/tc-cr16.c, * config/tc-csky.c, * config/tc-i386.c, * config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-microblaze.c, * config/tc-ns32k.c, * config/tc-pj.c, * config/tc-ppc.c, * config/tc-score.c, * config/tc-score7.c, * config/tc-tic4x.c, * config/tc-tic54x.c, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-xgate.c: Formatting.
2020-08-21Rearrange symbol_create parametersAlan Modra1-3/+3
These functions take an offset within frag, frag within section, and section parameter. So it makes sense to order the parameters as section, frag, offset. * symbols.h (symbol_new, symbol_create, local_symbol_make), (symbol_temp_new): Arrange params as section, frag, offset. * symbols.c: Adjust to suit. * as.c: Likewise. * cgen.c: Likewise. * dwarf2dbg.c: Likewise. * ecoff.c: Likewise. * expr.c: Likewise. * itbl-ops.c: Likewise. * read.c: Likewise. * stabs.c: Likewise. * subsegs.c: Likewise. * config/obj-coff.c: Likewise. * config/obj-elf.c: Likewise. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-csky.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xtensa.c: Likewise.
2020-08-20Port gas/config/* to str_htab.Martin Liska1-62/+57
* config/obj-coff-seh.c (seh_hash_insert): Port to use new str_htab type. (seh_hash_find): Likewise. (seh_hash_find_or_make): Likewise. * config/obj-coff.c (tag_init): Likewise. (tag_insert): Likewise. (tag_find): Likewise. * config/obj-elf.c (struct group_list): Likewise. (build_additional_section_info): Likewise. (free_section_idx): Likewise. (elf_adjust_symtab): Likewise. (elf_frob_file_after_relocs): Likewise. * config/tc-aarch64.c (INSN_SIZE): Likewise. (parse_reg): Likewise. (insert_reg_alias): Likewise. (create_register_alias): Likewise. (s_unreq): Likewise. (parse_shift): Likewise. (parse_pldop): Likewise. (parse_barrier): Likewise. (parse_barrier_psb): Likewise. (parse_bti_operand): Likewise. (parse_sys_reg): Likewise. (parse_sys_ins_reg): Likewise. (lookup_mnemonic): Likewise. (opcode_lookup): Likewise. (parse_operands): Likewise. (checked_hash_insert): Likewise. (sysreg_hash_insert): Likewise. (fill_instruction_hash_table): Likewise. (md_begin): Likewise. * config/tc-alpha.c (struct alpha_reloc_tag): Likewise. (get_alpha_reloc_tag): Likewise. (assemble_tokens_to_insn): Likewise. (assemble_tokens): Likewise. (md_begin): Likewise. * config/tc-arc.c (arc_find_opcode): Likewise. (arc_insert_opcode): Likewise. (find_opcode_match): Likewise. (declare_register): Likewise. (declare_addrtype): Likewise. (md_begin): Likewise. (arc_parse_name): Likewise. (tc_arc_regname_to_dw2regnum): Likewise. (arc_extcorereg): Likewise. * config/tc-arm.c (MVE_BAD_QREG): Likewise. (arm_reg_parse_multi): Likewise. (parse_reloc): Likewise. (insert_reg_alias): Likewise. (create_register_alias): Likewise. (s_unreq): Likewise. (parse_shift): Likewise. (parse_psr): Likewise. (parse_cond): Likewise. (parse_barrier): Likewise. (do_vfp_nsyn_opcode): Likewise. (opcode_lookup): Likewise. (arm_tc_equal_in_insn): Likewise. (md_begin): Likewise. * config/tc-avr.c (md_begin): Likewise. (avr_ldi_expression): Likewise. (md_assemble): Likewise. (avr_update_gccisr): Likewise. (avr_emit_insn): Likewise. * config/tc-cr16.c (get_register): Likewise. (get_register_pair): Likewise. (get_index_register): Likewise. (get_index_register_pair): Likewise. (get_pregister): Likewise. (get_pregisterp): Likewise. (initialise_reg_hash_table): Likewise. (md_begin): Likewise. (cr16_assemble): Likewise. (md_assemble): Likewise. * config/tc-cris.c (cris_insn_first_word_frag): Likewise. (md_begin): Likewise. (cris_process_instruction): Likewise. * config/tc-crx.c (get_register): Likewise. (get_copregister): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-csky.c (md_begin): Likewise. (parse_opcode): Likewise. (get_operand_value): Likewise. (v1_work_jbsr): Likewise. (v2_work_rotlc): Likewise. (v2_work_bgeni): Likewise. (v2_work_not): Likewise. * config/tc-d10v.c (sizeof): Likewise. (md_begin): Likewise. (do_assemble): Likewise. (md_apply_fix): Likewise. * config/tc-d30v.c (sizeof): Likewise. (md_begin): Likewise. (do_assemble): Likewise. * config/tc-dlx.c (RELOC_DLX_VTENTRY): Likewise. (md_begin): Likewise. (machine_ip): Likewise. * config/tc-ft32.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-h8300.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-hppa.c (pa_ip): Likewise. (md_begin): Likewise. * config/tc-i386.c (md_begin): Likewise. (i386_print_statistics): Likewise. (parse_insn): Likewise. (process_operands): Likewise. (i386_index_check): Likewise. (parse_real_register): Likewise. * config/tc-ia64.c (dot_rot): Likewise. (dot_entry): Likewise. (declare_register): Likewise. (md_begin): Likewise. (ia64_parse_name): Likewise. (md_assemble): Likewise. (dot_alias): Likewise. (do_alias): Likewise. (ia64_adjust_symtab): Likewise. (do_secalias): Likewise. (ia64_frob_file): Likewise. * config/tc-m68hc11.c (m68hc11_print_statistics): Likewise. (md_begin): Likewise. (print_insn_format): Likewise. (md_assemble): Likewise. * config/tc-m68k.c (tc_gen_reloc): Likewise. (m68k_ip): Likewise. (md_begin): Likewise. * config/tc-mcore.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-microblaze.c (md_begin): Likewise. (md_assemble): Likewise. (md_apply_fix): Likewise. * config/tc-mips.c (nopic_need_relax): Likewise. (md_begin): Likewise. (macro_build): Likewise. (mips16_macro_build): Likewise. (mips_lookup_insn): Likewise. (mips_ip): Likewise. (mips16_ip): Likewise. * config/tc-mmix.c (sizeof): Likewise. (mmix_md_begin): Likewise. (md_assemble): Likewise. * config/tc-mn10200.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-mn10300.c (HAVE_AM30): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-moxie.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-msp430.c (md_begin): Likewise. (msp430_operands): Likewise. (md_assemble): Likewise. * config/tc-nds32.c (PV_DONT_CARE): Likewise. (builtin_isreg): Likewise. (builtin_regnum): Likewise. (nds32_init_nds32_pseudo_opcodes): Likewise. (nds32_lookup_pseudo_opcode): Likewise. (nds32_relax_hint): Likewise. (md_begin): Likewise. (nds32_find_reloc_table): Likewise. (nds32_elf_append_relax_relocs_traverse): Likewise. (nds32_relax_branch_instructions): Likewise. (md_convert_frag): Likewise. (nds32_elf_analysis_relax_hint): Likewise. (tc_nds32_regname_to_dw2regnum): Likewise. * config/tc-nios2.c (nios2_opcode_lookup): Likewise. (nios2_reg_lookup): Likewise. (nios2_ps_lookup): Likewise. (md_begin): Likewise. * config/tc-ns32k.c (struct hash_control): Likewise. (parse): Likewise. (md_begin): Likewise. * config/tc-pdp11.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-pj.c (fake_opcode): Likewise. (alias): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-ppc.c (ppc_setup_opcodes): Likewise. (md_assemble): Likewise. * config/tc-pru.c (pru_opcode_lookup): Likewise. (pru_reg_lookup): Likewise. (md_begin): Likewise. (md_end): Likewise. * config/tc-riscv.c (init_ext_version_hash): Likewise. (riscv_get_default_ext_version): Likewise. (riscv_set_arch): Likewise. (init_opcode_names_hash): Likewise. (opcode_name_lookup): Likewise. (enum reg_class): Likewise. (hash_reg_name): Likewise. (riscv_init_csr_hash): Likewise. (reg_csr_lookup_internal): Likewise. (reg_lookup_internal): Likewise. (init_opcode_hash): Likewise. (md_begin): Likewise. (DECLARE_CSR): Likewise. (macro_build): Likewise. (riscv_ip): Likewise. * config/tc-s390.c (register_name): Likewise. (s390_setup_opcodes): Likewise. (md_begin): Likewise. (md_assemble): Likewise. (s390_insn): Likewise. * config/tc-score.c (struct s3_reg_map): Likewise. (s3_score_reg_parse): Likewise. (s3_dependency_type_from_insn): Likewise. (s3_parse_16_32_inst): Likewise. (s3_parse_48_inst): Likewise. (s3_insert_reg): Likewise. (s3_build_reg_hsh): Likewise. (s3_build_score_ops_hsh): Likewise. (s3_build_dependency_insn_hsh): Likewise. (s3_begin): Likewise. * config/tc-score7.c (struct s7_reg_map): Likewise. (s7_score_reg_parse): Likewise. (s7_dependency_type_from_insn): Likewise. (s7_parse_16_32_inst): Likewise. (s7_build_score_ops_hsh): Likewise. (s7_build_dependency_insn_hsh): Likewise. (s7_insert_reg): Likewise. (s7_build_reg_hsh): Likewise. (s7_begin): Likewise. * config/tc-sh.c (EMPTY): Likewise. (md_begin): Likewise. (find_cooked_opcode): Likewise. * config/tc-sparc.c (md_begin): Likewise. (sparc_ip): Likewise. * config/tc-spu.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-tic30.c (md_begin): Likewise. (tic30_operand): Likewise. (tic30_parallel_insn): Likewise. (md_assemble): Likewise. * config/tc-tic4x.c (TIC4X_ALT_SYNTAX): Likewise. (tic4x_asg): Likewise. (tic4x_inst_insert): Likewise. (tic4x_inst_add): Likewise. (md_begin): Likewise. (tic4x_operand_parse): Likewise. (md_assemble): Likewise. * config/tc-tic54x.c (MAX_SUBSYM_HASH): Likewise. (stag_add_field_symbols): Likewise. (tic54x_endstruct): Likewise. (tic54x_tag): Likewise. (tic54x_remove_local_label): Likewise. (tic54x_clear_local_labels): Likewise. (tic54x_var): Likewise. (tic54x_macro_start): Likewise. (tic54x_macro_info): Likewise. (tic54x_macro_end): Likewise. (subsym_isreg): Likewise. (subsym_structsz): Likewise. (md_begin): Likewise. (is_mmreg): Likewise. (is_type): Likewise. (encode_condition): Likewise. (encode_cc3): Likewise. (encode_cc2): Likewise. (encode_operand): Likewise. (tic54x_parse_insn): Likewise. (tic54x_parse_parallel_insn_firstline): Likewise. (subsym_create_or_replace): Likewise. (subsym_lookup): Likewise. (subsym_substitute): Likewise. (tic54x_undefined_symbol): Likewise. * config/tc-tic6x.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-tilegx.c (O_hw2_last_plt): Likewise. (INSERT_SPECIAL_OP): Likewise. (md_begin): Likewise. (tilegx_parse_name): Likewise. (parse_reg_expression): Likewise. (md_assemble): Likewise. * config/tc-tilepro.c (O_tls_ie_load): Likewise. (INSERT_SPECIAL_OP): Likewise. (tilepro_parse_name): Likewise. (parse_reg_expression): Likewise. (md_assemble): Likewise. * config/tc-v850.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-vax.c (md_ri_to_chars): Likewise. (vip_begin): Likewise. (vip): Likewise. (main): Likewise. (md_begin): Likewise. * config/tc-wasm32.c (md_begin): Likewise. (md_assemble): Likewise. * config/tc-xgate.c (xgate_parse_operand): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-z8k.c (md_begin): Likewise. (md_assemble): Likewise.
2020-08-10aarch64: Don't assert on long sysreg namesAlex Coplan1-13/+30
This patch fixes an assertion failure on long system register operands in the AArch64 backend. See the new testcase for an input which reproduces the issue. gas/ChangeLog: * config/tc-aarch64.c (parse_sys_reg): Don't assert when parsing a long system register. (parse_sys_ins_reg): Likewise. (sysreg_hash_insert): New. (md_begin): Use sysreg_hash_insert() to ensure all system registers are no longer than the maximum length at startup. * testsuite/gas/aarch64/invalid-sysreg-assert.d: New test. * testsuite/gas/aarch64/invalid-sysreg-assert.l: Error output. * testsuite/gas/aarch64/invalid-sysreg-assert.s: Input. include/ChangeLog: * opcode/aarch64.h (AARCH64_MAX_SYSREG_NAME_LEN): New.
2020-08-10[aarch64] GAS doesn't validate the architecture version for any tlbi ↵Przemyslaw Wirkus1-4/+12
registers. Fixed with this patch. * gas/config/tc-aarch64.c (parse_sys_reg): Call to aarch64_sys_ins_reg_supported_p instead of aarch64_sys_reg_supported_p. (parse_sys_ins_reg): Add aarch64_sys_reg_deprecated_p check. * include/opcode/aarch64.h (aarch64_sys_reg_deprecated_p): Functions paramaters changed. (aarch64_sys_reg_supported_p): Function removed. (aarch64_sys_ins_reg_supported_p): Functions paramaters changed. * opcodes/aarch64-opc.c (aarch64_print_operand): (aarch64_sys_reg_deprecated_p): Functions paramaters changed. (aarch64_sys_reg_supported_p): Function removed. (aarch64_sys_ins_reg_supported_p): Functions paramaters changed. (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p into this function. * gas/testsuite/gas/aarch64/illegal-sysreg-5.d: New test. * gas/testsuite/gas/aarch64/illegal-sysreg-5.l: New test. * gas/testsuite/gas/aarch64/sysreg-5.s: New test.
2020-07-02aarch64: Fix segfault on unicode symbolsAlex Coplan1-1/+1
This patch fixes a segfault which occurs when the AArch64 backend parses a symbol operand that begins with a register name and ends with a unicode byte (byte value > 127). For example, the following input causes the crash: x0é: udf x0é gas/ChangeLog: 2020-07-02 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (reg_name_p): Fix cast so that we don't segfault on negative chars. * testsuite/gas/aarch64/reglike-label-unicode-segv.d: New test. * testsuite/gas/aarch64/reglike-label-unicode-segv.s: Input.
2020-05-21Replace "if (x) free (x)" with "free (x)", gasAlan Modra1-4/+2
* atof-generic.c: Replace "if (x) free (x)" with "free (x)" throughout. * config/obj-elf.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-tic30.c: Likewise. * ecoff.c: Likewise. * read.c: Likewise. * stabs.c: Likewise. * symbols.c: Likewise. * testsuite/gas/all/test-gen.c: Likewise.
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-1/+3
binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new disassembly. * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise. ld/ * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly. * testsuite/ld-aarch64/farcall-b-section.d: Likewise. * testsuite/ld-aarch64/farcall-back.d: Likewise. * testsuite/ld-aarch64/farcall-bl-section.d: Likewise. gas/ * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED. (parse_operands): Implement for AARCH64_OPND_UNDEFINED. * testsuite/gas/aarch64/udf.s: New. * testsuite/gas/aarch64/udf.d: New. * testsuite/gas/aarch64/udf-invalid.s: New. * testsuite/gas/aarch64/udf-invalid.l: New. * testsuite/gas/aarch64/udf-invalid.d: New. include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED. opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2. * aarch64-opc.c (fields): Add entry for FLD_imm16_2. (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED. * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for FLD_imm16_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-2/+2
This patch implements the TSB instructions: https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/ tsb-csync-trace-synchronization-barrier Since TSB and PSB both use the same (and only) argument "CSYNC", this patch reuses it for TSB. However, the same argument would imply different value for CRm:Op2 which are anyway fixed values, so I have diverted the inserter/extracter function to dummy versions instead of the "hint" version. The operand checker part still uses the existing infratructure for AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly. gas/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_barrier_psb): Update error messages to include TSB. * testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests. * testsuite/gas/aarch64/system-2.s: Add new tsb tests. * testsuite/gas/aarch64/system.d: Update. opcodes/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_none): New. * aarch64-asm.h (ins_none): New declaration. * aarch64-dis.c (aarch64_ext_none): New. * aarch64-dis.h (ext_none): New declaration. * aarch64-opc.c (aarch64_print_operand): Update case for AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_opcode_table): Add tsb. (AARCH64_OPERANDS): Update inserter/extracter for AARCH64_OPND_BARRIER_PSB to use new dummy functions. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-02-26Indent labelsAlan Modra1-7/+7
Labels don't go in the first column according to standard emacs C indent rules, and I got annoyed enough at seeing diff -p show a label rather than the function name to fix this. bfd/ * aoutx.h: Indent labels correctly. Format error strings. * archive.c: Likewise. * archive64.c: Likewise. * coff-arm.c: Likewise. * coff-rs6000.c: Likewise. * coff-stgo32.c: Likewise. * cpu-arm.c: Likewise. * dwarf2.c: Likewise. * elf-ifunc.c: Likewise. * elf-properties.c: Likewise. * elf-s390-common.c: Likewise. * elf-strtab.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-csky.c: Likewise. * elf32-i386.c: Likewise. * elf32-m68k.c: Likewise. * elf32-msp430.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-pru.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-x86-64.c: Likewise. * elfcode.h: Likewise. * elfcore.h: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-x86.c: Likewise. * i386lynx.c: Likewise. * merge.c: Likewise. * pdp11.c: Likewise. * plugin.c: Likewise. * reloc.c: Likewise. binutils/ * elfedit.c: Indent labels correctly. * readelf.c: Likewise. * resres.c: Likewise. gas/ * config/obj-elf.c: Indent labels correctly. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s12z.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * read.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. ld/ * emultempl/cskyelf.em: Indent labels correctly. * ldfile.c: Likewise. * ldlang.c: Likewise. * plugin.c: Likewise. opcodes/ * aarch64-asm.c: Indent labels correctly. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. * alpha-dis.c: Likewise. * i386-dis.c: Likewise. * nds32-asm.c: Likewise. * nfp-dis.c: Likewise. * visium-dis.c: Likewise.
2020-01-13[gas][aarch64] Turn on SVE when using f32mm or f64mm extensionsMatthew Malcomson1-2/+2
There are no instructions under these matrix multiply extensions that can be used without having SVE enabled. Since these extensions require SVE, we make that explicit in the options table. Tested on aarch64-none-elf without regressions. gas/ChangeLog: 2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature dependency.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-12gas signed overflow fixesAlan Modra1-1/+2
* config/tc-aarch64.c (get_aarch64_insn): Avoid signed overflow. * config/tc-metag.c (parse_dalu): Likewise. * config/tc-tic4x.c (md_pcrel_from): Likewise. * config/tc-tic6x.c (tic6x_output_unwinding): Likewise. * config/tc-csky.c (parse_fexp): Use an unsigned char temp buffer. Don't use register keyword. Avoid signed overflow and remove now unneccesary char masks. Formatting. * config/tc-ia64.c (operand_match): Don't use shifts to sign extend. * config/tc-mep.c (mep_apply_fix): Likewise. * config/tc-pru.c (md_apply_fix): Likewise. * config/tc-riscv.c (load_const): Likewise. * config/tc-nios2.c (md_apply_fix): Likewise. Don't potentially truncate fixup before right shift. Tidy BFD_RELOC_NIOS2_HIADJ16 calculation.
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich1-3/+1
This, at the assembler level, is just a "brace" feature covering both AES and SHA2. Hence there's no need for it to have a separate feature flag, freeing up a bit for future re-use. Along these lines there are also a number of dead definitions/variables in the opcode table file.
2019-12-05Arm64: correct "sha3" arch-extension directive handlingJan Beulich1-3/+2
SHA2 is a prereq to SHA3, not part of it aiui. Hence disabling the latter should not also disable the former. In the course of adding respective tests also do away with the duplication of crypto.d's contents in crypto-directive.d.
2019-11-25Fix "psb CSYNC" and "bti C".Andrew Pinski1-3/+6
psb CYSNC was not finding that CSYNC was a correct spelling. The problem was upper case version was being put in the wrong hashtable. This fixes the problem by using the correct hashtable. Also adds testcases for the upper case versions. * config/tc-aarch64.c (md_begin): Use correct hash table for uppercase version of hint. * testsuite/gas/aarch64/system-2.s: Extend psb case to uppercase. * testsuite/gas/aarch64/system-2.d: Update. Change-Id: If43f8b85cacd24840d596c3092b0345e5f212766
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+7
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the aarch64 backend. The following instructions are added: {s/u}mmla, usmmla, {us/su}dot, fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension. (parse_operands): Add new operand. * testsuite/gas/aarch64/i8mm.s: New test. * testsuite/gas/aarch64/i8mm.d: New test. * testsuite/gas/aarch64/f32mm.s: New test. * testsuite/gas/aarch64/f32mm.d: New test. * testsuite/gas/aarch64/f64mm.s: New test. * testsuite/gas/aarch64/f64mm.d: New test. * testsuite/gas/aarch64/sve-movprfx-mm.s: New test. * testsuite/gas/aarch64/sve-movprfx-mm.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New. (AARCH64_FEATURE_F32MM): New. (AARCH64_FEATURE_F64MM): New. (AARCH64_OPND_SVE_ADDR_RI_S4x32): New. (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for instructions that do not require special handling. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, aarch64_feature_f64mm): New feature sets. (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply instructions. (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set macros. (QL_MMLA64, OP_SVE_SBB): New qualifiers. (OP_SVE_QQQ): New qualifier. (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. (aarch64_opcode_table): Define new instructions smmla, ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod uzip{1/2}, trn{1/2}. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new S4x32 operand. * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson1-0/+49
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat' directive for the AArch64 backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on aarch64-none-elf and aarch64-none-linux-gnu with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-29 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-aarch64.c (md_atof): Add encoding for the bfloat16 format. * testsuite/gas/aarch64/bfloat16-directive-le.d: New test. * testsuite/gas/aarch64/bfloat16-directive-be.d: New test. * testsuite/gas/aarch64/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+6
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the following BFloat16 instructions to the aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b], bfcvtn2. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Special case the S_2H operand qualifier. * doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions. * testsuite/gas/aarch64/bfloat16.d: New test. * testsuite/gas/aarch64/bfloat16.s: New test. * testsuite/gas/aarch64/illegal-bfloat16.d: New test. * testsuite/gas/aarch64/illegal-bfloat16.l: New test. * testsuite/gas/aarch64/illegal-bfloat16.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros. (AARCH64_ARCH_V8_6): Include BFloat16 feature macros. (enum aarch64_opnd_qualifier): Introduce new operand qualifier AARCH64_OPND_QLF_S_2H. (enum aarch64_insn_class): Introduce new class "bfloat16". (BFLOAT16_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-opc.c (struct operand_qualifier_data): Add data for new AARCH64_OPND_QLF_S_2H qualifier. * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve, aarch64_feature_bfloat16_bfmmla4): New feature sets. (BFLOAT_SVE, BFLOAT): New feature set macros. (BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros to define BFloat16 instructions. (aarch64_opcode_table): Define new instructions bfdot, bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] bfcvtn2, bfcvt. Regression tested on aarch64-elf. Is it ok for trunk? Regards, Mihail
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson1-0/+1
Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. This first patch adds the Armv8.6-A flag to binutils. No instructions are behind it at the moment. Commited on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (armv8.6-a): New arch. * doc/c-aarch64.texi (armv8.6-a): Document new arch. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_6): New. (AARCH64_ARCH_V8_6): New. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (ARMV8_6): New macro. Is it ok for trunk? Regards, Mihail
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument ↵Delia Burduv1-15/+29
for the writeback form of the LDRAA and LDRAB mnemonics This is a shorthand for the immediate argument being 0, as described here: https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication This is because the instructions still have a use with an immediate argument of 0, unlike loads without the PAC functionality. Currently, the mnemonics are LDRAA Xt, [Xn, #<simm10>]! LDRAB Xt, [Xn, #<simm10>]! After this patch they become LDRAA Xt, [Xn {, #<simm10>}]! LDRAB Xt, [Xn {, #<simm10>}]! gas * config/tc-aarch64.c (parse_address_main): Accept the omission of the immediate argument for ldraa and ldrab as a shorthand for the immediate being 0. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test. * testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the writeback form with no offset. * testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset error. opcodes * aarch64-opc.c (print_immediate_offset_address): Don't print the immediate for the writeback form of ldraa/ldrab if it is 0. * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10. * aarch64-opc-2.c: Regenerated.
2019-09-19bfd_section_* macrosAlan Modra1-1/+1
This large patch removes the unnecessary bfd parameter from various bfd section macros and functions. The bfd is hardly ever used and if needed for the bfd_set_section_* or bfd_rename_section functions can be found via section->owner except for the com, und, abs, and ind std_section special sections. Those sections shouldn't be modified anyway. The patch also removes various bfd_get_section_<field> macros, replacing their use with bfd_section_<field>, and adds bfd_set_section_lma. I've also fixed a minor bug in gas where compressed section renaming was done directly rather than calling bfd_rename_section. This would have broken bfd_get_section_by_name and similar functions, but that hardly mattered at such a late stage in gas processing. bfd/ * bfd-in.h (bfd_get_section_name, bfd_get_section_vma), (bfd_get_section_lma, bfd_get_section_alignment), (bfd_get_section_size, bfd_get_section_flags), (bfd_get_section_userdata): Delete. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment): Lose bfd parameter. (bfd_section_flags, bfd_section_userdata): New. (bfd_is_com_section): Rename parameter. * section.c (bfd_set_section_userdata, bfd_set_section_vma), (bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section), (bfd_set_section_size): Delete bfd parameter, rename section parameter. (bfd_set_section_lma): New. * bfd-in2.h: Regenerate. * mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param, update callers. * aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h, * elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c, * elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c, * elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c, * elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c, * mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c, * peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c, * xcofflink.c: Update throughout for bfd section macro and function changes. binutils/ * addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c, * objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c, * od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c, * resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update throughout for bfd section macro and function changes. gas/ * as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c, * read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c, * config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c, * config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c, * config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c, * config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c, * config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c, * config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c, * config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for bfd section macro and function changes. * write.c (compress_debug): Use bfd_rename_section. gdb/ * aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c, * coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c, * dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c, * exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h, * hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c, * i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c, * maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c, * mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c, * objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c, * ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c, * rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c, * s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c, * solib-spu.c, * solib-svr4.c, * solib-target.c, * spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c, * symmisc.c, * symtab.c, * target.c, * windows-nat.c, * xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c, * mi/mi-interp.c: Update throughout for bfd section macro and function changes. * gcore (gcore_create_callback): Use bfd_set_section_lma. * spu-tdep.c (spu_overlay_new_objfile): Likewise. gprof/ * corefile.c, * symtab.c: Update throughout for bfd section macro and function changes. ld/ * ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c, * emultempl/aarch64elf.em, * emultempl/aix.em, * emultempl/armcoff.em, * emultempl/armelf.em, * emultempl/cr16elf.em, * emultempl/cskyelf.em, * emultempl/m68hc1xelf.em, * emultempl/m68kelf.em, * emultempl/mipself.em, * emultempl/mmix-elfnmmo.em, * emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em, * emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update throughout for bfd section macro and function changes. libctf/ * ctf-open-bfd.c: Update throughout for bfd section macro changes. opcodes/ * arc-ext.c: Update throughout for bfd section macro changes. sim/ * common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c, * erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c, * m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c, * rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c, * rx/trace.c: Update throughout for bfd section macro changes.
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point ↵Barnaby Wilks1-1/+2
numbers for the AArch64 assembler. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 0.5 .float16 10.2, NaN, 452.09 The floats will always be encoded using the binary16 format as described in the IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision format since AArch64 only supports the IEEE format. gas * config/tc-aarch64.c: Add float16 directive and add "Hh" to acceptable float characters. * doc/c-aarch64.texi: Documentation for float16 directive. * testsuite/gas/aarch64/float16-be.d: New test. * testsuite/gas/aarch64/float16-le.d: New test. * testsuite/gas/aarch64/float16.s: New test. * NEWS: Add NEWS entry.
generated by cgit v1.1 at 2025-01-27 16:25:36 +0000