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2019-04-19s12z and h8300 no-print-map-discarded failsAlan Modra2-1/+4
This tidies the remaining --no-print-map-discarded fails. h8300-elf warns on a section without flags, and s12z doesn't support --gc-sections. bfd/ * elf32-s12z.c (elf_backend_can_gc_sections): Don't define ld/ * testsuite/ld-gc/skip-map-discarded.s: Add section attributes. * testsuite/lib/ld-lib.exp (check_gc_sections_available): Add s12z to list of targets not supporting --gc-sections.
2019-04-19Automatic date update in version.inGDB Administrator1-1/+1
2019-04-18Automatic date update in version.inGDB Administrator1-1/+1
2019-04-17x86: Suggest -fPIE when not building shared objectH.J. Lu3-7/+23
When PIC is needed, linker should suggest -fPIE, instead of -fPIC, when not building shared object. bfd/ * elf64-x86-64.c (elf_x86_64_need_pic): Suggest -fPIE when not building shared object. * elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Likewise. ld/ * testsuite/ld-i386/i386.exp: Run pr18801a and pr18801b instead of pr18801. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr18801.d: Removed. * testsuite/ld-x86-64/pr18801.d: Likewise. * testsuite/ld-i386/pr18801a.d: New file. * testsuite/ld-i386/pr18801b.d: Likewise. * testsuite/ld-x86-64/pr18801a.d: Likewise. * testsuite/ld-x86-64/pr18801b.d: Likewise. * testsuite/ld-x86-64/pie2.d: Suggest -fPIE instead of -fPIC. * testsuite/ld-x86-64/pie2.d: Likewise. * testsuite/ld-x86-64/pr19719.d: Likewise. * testsuite/ld-x86-64/pr19807-2a.d: Likewise. * testsuite/ld-x86-64/pr19969.d: Likewise. * testsuite/ld-x86-64/pr21997-1a.err: Likewise. * testsuite/ld-x86-64/pr21997-1b.err: Likewise. * testsuite/ld-x86-64/pr22001-1a.err: Likewise. * testsuite/ld-x86-64/pr22001-1b.err: Likewise. * testsuite/ld-x86-64/pr22791-1.err: Likewise.
2019-04-17x86: Also check x86 linker_def for non-shared definitionH.J. Lu2-0/+7
Since elf_x86_linker_defined sets linker_def in elf_x86_link_hash_entry for linker defined symbols, SYMBOL_DEFINED_NON_SHARED_P should also check linker_def in elf_x86_link_hash_entry. bfd/ PR ld/24458 * elfxx-x86.h (SYMBOL_DEFINED_NON_SHARED_P): Also check x86 linker_def. ld/ PR ld/24458 * testsuite/ld-x86-64/x86-64.exp: Run PR ld/24458 tests. * testsuite/ld-x86-64/pr24458.s: New file. * testsuite/ld-x86-64/pr24458a-x32.d: Likewise. * testsuite/ld-x86-64/pr24458a.d: Likewise. * testsuite/ld-x86-64/pr24458b-x32.d: Likewise. * testsuite/ld-x86-64/pr24458b.d: Likewise. * testsuite/ld-x86-64/pr24458c-x32.d: Likewise. * testsuite/ld-x86-64/pr24458c.d: Likewise.
2019-04-17Automatic date update in version.inGDB Administrator1-1/+1
2019-04-16Automatic date update in version.inGDB Administrator1-1/+1
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira4-0/+11
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case. Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg (). A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match. ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal relocation. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (parse_sys_vldr_vstr): New function. (OP_VLDR): New enum operand_parse_code enumerator. (parse_operands): Add logic for OP_VLDR. (do_t_vldr_vstr_sysreg): New function. (do_vldr_vstr): Likewise. (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode. (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset. Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad uses of VLDR and VSTR. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for above bad uses. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and VSTR valid uses. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the above examples. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %J and %K format specifier. Add entries for VLDR and VSTR of system registers. (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in coprocessor instructions on Armv8.1-M Mainline targets. Add handling of %J and %K format specifier.
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M ↵Andre Vieira4-0/+15
Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira4-0/+15
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum. ChangeLog entries are as follows: 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. (insns): New instruction for bfcsel. (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BFCSEL. (md_appdy_fix): Likewise (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: New. * testsuite/gas/arm/armv8_1-m-bfcsel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfcsel.s: New. * testsuite/ld-arm/bfcsel.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z.
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc ↵Andre Vieira5-1/+78
R_ARM_THM_BF12 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira5-1/+80
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc ↵Andre Vieira5-1/+134
R_ARM_THM_BF16 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them. This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16. The inconsistency between external R_ARM_THM_BF16 and internal BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17 and R_ARM_THM_BF16 together. (get_value_helper): New reloc helper. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF16): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF17. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2019-04-15[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real ↵Andre Vieira4-0/+15
for fallback branch This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. This is the first infrastructure patch that adds a new bfd_reloc_code_real enum for the fallback branch offset. This is common for all such instructions and needs to be resolvable by the assembler. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (v8_1_branch_value_check): New function to check branch offsets. (md_appdy_fix): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (tc_gen_reloc): Likewise. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira5-6/+59
The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2019-04-15Automatic date update in version.inGDB Administrator1-1/+1
2019-04-14Automatic date update in version.inGDB Administrator1-1/+1
2019-04-13Automatic date update in version.inGDB Administrator1-1/+1
2019-04-12Automatic date update in version.inGDB Administrator1-1/+1
2019-04-11x86: Add -z cet-report=[none|warning|error]H.J. Lu3-2/+78
Add -z cet-report=[none|warning|error] to report the missing Intel Indirect Branch Tracking (IBT) and Shadow Stack (SHSTK) properties in input .note.gnu.property section. -z cet-report=none, which is the default, will make the linker not report missing properties in input files. -z cet-report=warning will make the linker issue a warning for missing properties in input files. -z cet-report=error will make the linker issue an error for missing properties in input files. Note that -z ibt will turn off the missing IBT property report and -z shstk will turn off the missing SHSTK property report. Supported for Linux/i386 and Linux/x86_64. bfd/ * elf-linker-x86.h (elf_x86_cet_report): New. (elf_linker_x86_params): Add cet_report. * elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Report missing IBT and SHSTK properties if needed. ld/ * ld.texi: Document -z cet-report=[none|warning|error]. * emulparams/cet.sh: Add -z cet-report=[none|warning|error]. * testsuite/ld-i386/i386.exp: Run -z cet-report=[warning|error] tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/property-x86-cet1.d: New file. * testsuite/ld-i386/property-x86-cet2a.d: Likewise. * testsuite/ld-i386/property-x86-cet2b.d: Likewise. * testsuite/ld-i386/property-x86-cet3a.d: Likewise. * testsuite/ld-i386/property-x86-cet3b.d: Likewise. * testsuite/ld-i386/property-x86-cet4a.d: Likewise. * testsuite/ld-i386/property-x86-cet4b.d: Likewise. * testsuite/ld-i386/property-x86-cet5a.d: Likewise. * testsuite/ld-i386/property-x86-cet5b.d: Likewise. * testsuite/ld-i386/property-x86-cet6.d: Likewise. * testsuite/ld-x86-64/property-x86-cet.s: Likewise. * testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2b.d: Likewise. * testsuite/ld-x86-64/property-x86-cet3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet3a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet3b.d: Likewise. * testsuite/ld-x86-64/property-x86-cet4a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet4a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet4b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet4b.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b.d: Likewise. * testsuite/ld-x86-64/property-x86-cet6-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet6.d: Likewise.
2019-04-11Add PR ld/24436 to ChangeLog entryH.J. Lu1-0/+1
2019-04-11Check corrupt VTENTRY entry in bfd_elf_gc_record_vtentryH.J. Lu33-98/+80
Instead of BFD_ASSERT (h != NULL) with ld: BFD ... assertion fail .../bfd/elf64-x86-64.c:2562 ld: bad.o: invalid string offset 50331648 >= 371 for section `nterp' check corrupt VTENTRY entry in bfd_elf_gc_record_vtentry with ld: bad.o: section 'g': corrupt VTENTRY entry * elf-m10300.c (mn10300_elf_check_relocs): Remove BFD_ASSERT of "h != NULL". Don't check "h != NULL" before calling. bfd_elf_gc_record_vtentry. * elf32-arm.c (elf32_arm_check_relocs): Likewise. * elf32-bfin.c (bfin_check_relocs): Likewise. * elf32-cris.c (cris_elf_check_relocs): Likewise. * elf32-csky.c (csky_elf_check_relocs): Likewise. * elf32-d10v.c (elf32_d10v_check_relocs): Likewise. * elf32-dlx.c (elf32_dlx_check_relocs): Likewise. * elf32-fr30.c (fr30_elf_check_relocs): Likewise. * elf32-frv.c (elf32_frv_check_relocs): Likewise. * elf32-hppa.c (elf32_hppa_check_relocs): Likewise. * elf32-i386.c (elf_i386_check_relocs): Likewise. * elf32-iq2000.c (iq2000_elf_check_relocs): Likewise. * elf32-m32r.c (m32r_elf_check_relocs): Likewise. * elf32-m68hc1x.c (elf32_m68hc11_check_relocs): Likewise. * elf32-m68k.c (elf_m68k_check_relocs): Likewise. * elf32-mcore.c (mcore_elf_check_relocs): Likewise. * elf32-metag.c (elf_metag_check_relocs): Likewise. * elf32-or1k.c (or1k_elf_check_relocs): Likewise. * elf32-ppc.c (ppc_elf_check_relocs): Likewise. * elf32-s390.c (elf_s390_check_relocs): Likewise. * elf32-sh.c (sh_elf_check_relocs): Likewise. * elf32-v850.c (v850_elf_check_relocs): Likewise. * elf32-vax.c (elf_vax_check_relocs): Likewise. * elf32-xstormy16.c (xstormy16_elf_check_relocs): Likewise. * elf32-xtensa.c (elf_xtensa_check_relocs): Likewise. * elf64-mmix.c (mmix_elf_check_relocs): Likewise. * elf64-ppc.c (ppc64_elf_check_relocs): Likewise. * elf64-s390.c (elf_s390_check_relocs): Likewise. * elf64-x86-64.c (elf_s390_check_relocs): Likewise. * elfxx-mips.c (_bfd_mips_elf_check_relocs): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise. * elflink.c (bfd_elf_gc_record_vtinherit): Check for corrupt VTENTRY entry.
2019-04-11PR24435, buffer overflow reading dynamic entriesAlan Modra2-1/+7
PR 24435 * elflink.c (elf_link_add_object_symbols): Don't read partial dynamic entries from fuzzed objects.
2019-04-11AArch64: When DF_BIND_NOW don't use TLSDESC GOT value.Tamar Christina2-5/+15
When using DF_BIND_NOW on AArch64 we don't reserve the GOT slot for a TLSDESC, but we still emitted DT_TLSDESC_GOT and DT_TLSDESC_PLT. This caused random memory corruption as the "special" value of (bfd_vma)-1 would be set for dt_tlsdesc_got. Since we don't have a value of dt_tlsdesc_got I also don't emit DT_TLSDESC_PLT now becuase it would point to an incomplete PLT. To be able to write the PLT entry DT_TLSDESC_GOT is needed and since we don't have one we can't write the PLT entry either. It is my understanding that GLIBC doesn't need these two entries when not lazy loading. Conversely AArch32 does not reserve neither the GOT not the PLT slot when doing DF_BIND_NOW. AArch32 does not need these checks because these values are initialized to 0 and so the if (...) checks don't pass, but on AArch64 these are initialized to (bfd_vma)-1 and thus we need some extra checks. bfd/ChangeLog: PR ld/24302 * elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Don't emit DT_TLSDESC_GOT and DT_TLSDESC_PLT when DF_BIND_NOW. (elfNN_aarch64_finish_dynamic_sections): Don't write PLT if DF_BIND_NOW. ld/ChangeLog: PR ld/24302 * testsuite/ld-aarch64/aarch64-elf.exp: Add new test. * testsuite/ld-aarch64/tls-relax-gdesc-le-now.d: New test.
2019-04-11Automatic date update in version.inGDB Administrator1-1/+1
2019-04-10PR24427, bfd/doc/chew.c reads uninitialized memory and subtracts from ↵Michael Forney2-2/+7
function pointer PR 24427 * doc/chew.c (free_words): Correctly free "push_text" strings.
2019-04-10Automatic date update in version.inGDB Administrator1-1/+1
2019-04-09Automatic date update in version.inGDB Administrator1-1/+1
2019-04-08x86: Remove i386-*-kaos* and i386-*-chaos targetsH.J. Lu2-8/+4
Remove i386-*-kaos* and i386-*-chaos targets since they are no longer supported by config.sub: $ .../config.sub i386-kaos Invalid configuration `i386-kaos': system `kaos' not recognized $ .../config.sub i386-chaos Invalid configuration `i386-chaos': system `chaos' not recognized $ bfd/ * config.bfd: Remove i[3-7]86-*-kaos* and i[3-7]86-*-chaos targets. gas/ * configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets. * testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos* check. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_chaos.c. (eelf_i386_chaos.c): Removed. * Makefile.in: Regenerated. * configure.tgt: Remove i[3-7]86-*-kaos*. * emulparams/elf_i386_chaos.sh: Removed.
2019-04-08Fix x86_64-rdos build failAlan Modra3-26/+33
x86_64-rdos is one of the few x86_64 targets that is 64-bit only and the x86_64 configure entries don't depend on elf-vxworks.lo. This results in undefined references from elfxx-x86.o. * configure.ac (elfxx_x86): Define and use. * configure: Regenerate.
2019-04-08Automatic date update in version.inGDB Administrator1-1/+1
2019-04-07Automatic date update in version.inGDB Administrator1-1/+1
2019-04-06x86: Move x86-specific linker options to elf_linker_x86_paramsH.J. Lu6-19/+109
Remove x86-specific linker options from bfd_link_info and put them in elf_linker_x86_params. Add _bfd_elf_linker_x86_set_options to pass x86-specific linker options from ld to bfd. bfd/ * elf-linker-x86.h: New file. * elf32-i386.c (elf_i386_convert_load_reloc): Use htab->params to get x86-specific linker options. * elf64-x86-64.c (elf_x86_64_convert_load_reloc): Likewise. (elf_x86_64_check_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_link_setup_gnu_properties): Likewise. * elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Likewise. (_bfd_x86_elf_link_setup_gnu_properties): Likewise. (_bfd_elf_linker_x86_set_options): New function. * elfxx-x86.h: Include "elf-linker-x86.h". (elf_x86_link_hash_table): Add params. include/ * bfdlink.h (bfd_link_info): Remove x86-specific linker options. ld/ * Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emultempl/elf-x86.em. (eelf_i386_sol2.c): Also depend on $(srcdir)/emultempl/solaris2-x86.em. (eelf_x86_64_sol2.c): Likewise. * Makefile.in: Regenerated. * emulparams/call_nop.sh: Set x86-specific linker options via params. * emulparams/cet.sh: Likewise. * emulparams/reloc_overflow.sh: Likewise. * emulparams/elf32_x86_64.sh (EXTRA_EM_FILE): New. Set to "elf-x86". * emulparams/elf_i386.sh: Likewise. * emulparams/elf_i386_be.sh: Likewise. * emulparams/elf_i386_chaos.sh: Likewise. * emulparams/elf_i386_ldso.sh: Likewise. * emulparams/elf_i386_vxworks.sh: Likewise. * emulparams/elf_iamcu.sh: Likewise. * emulparams/elf_k1om.sh: Likewise. * emulparams/elf_l1om.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emulparams/elf_i386_sol2.sh (EXTRA_EM_FILE): Changed to "solaris2-x86". * emulparams/elf_x86_64_sol2.sh: Likewise. * emultempl/elf-x86.em: New file. * emultempl/solaris2-x86.em: Likewise. * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Don't set link_info.call_nop_byte.
2019-04-06Automatic date update in version.inGDB Administrator1-1/+1
2019-04-05Automatic date update in version.inGDB Administrator1-1/+1
2019-04-04Automatic date update in version.inGDB Administrator1-1/+1
2019-04-03BFD whitespace fixesAlan Modra24-188/+197
* coff-i386.c, * coff-x86_64.c, * coffgen.c, * dwarf2.c, * elf-m10200.c, * elf.c, * elf32-arm.c, * elf32-bfin.c, * elf32-csky.c, * elf32-m32r.c, * elf32-microblaze.c, * elf32-pru.c, * elf32-rx.c, * elf32-xgate.c, * elf64-sparc.c, * elfnn-ia64.c, * elfxx-riscv.c, * elfxx-sparc.c, * linker.c, * mach-o.c, * pe-x86_64.c, * pei-x86_64.c, * plugin.c: Whitespace fixes.
2019-04-03Automatic date update in version.inGDB Administrator1-1/+1
2019-04-02RISC-V: Don't check ABI flags if no code section.Jim Wilson2-2/+39
This fixes a glib build failure reported in PR 24389. Using ld -b binary creates an object file with no elf header flags set which has the wrong ABI info for riscv64-linux. But the file also has no code sections, so I added code borrowed from the arm port that only checks the ELF header ABI flags if there is a code section. bfd/ PR 24389 * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Move read of ELF header flags to after check for ELF object file. Loop through sections looking for code sections, if none, then skip ABI checks.
2019-04-02Automatic date update in version.inGDB Administrator1-1/+1
2019-04-01Automatic date update in version.inGDB Administrator1-1/+1
2019-03-31Automatic date update in version.inGDB Administrator1-1/+1
2019-03-30RISC-V: Relax tail/j to c.j for RV64.Jim Wilson2-2/+10
2019-03-30 Andrew Waterman <andrew@sifive.com> bfd/ * elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for rd == X_RA case.
2019-03-30Automatic date update in version.inGDB Administrator1-1/+1
2019-03-29bfd: xtensa: fix shrink_dynamic_reloc_sections for export-dynamicMax Filippov2-1/+7
shrink_dynamic_reloc_sections must remove PLT entry that was created for an undefined weak symbol in the presence of --export-dynamic option when relaxation coalesces literals pointing to that symbol. This fixes the following assertion: ld: BFD (GNU Binutils) 2.31.1 internal error, aborting at elf32-xtensa.c:3292 in elf_xtensa_finish_dynamic_sections 2019-03-29 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (shrink_dynamic_reloc_sections): Add info->export_dynamic to the conditional. ld/ * testsuite/ld-xtensa/relax-undef-weak-pie-export-dynamic.d: New test definition. * testsuite/ld-xtensa/xtensa.exp (relax-undef-weak-pie-export-dynamic): Add new test.
2019-03-29Automatic date update in version.inGDB Administrator1-1/+1
2019-03-28PR24392, Clang warning Wtautological-constant-out-of-range-compareAlan Modra7-29/+53
PR 24392 * configure.ac: Invoke AC_CHECK_SIZEOF(int). * configure: Regenerate. * coffgen.c (coff_get_reloc_upper_bound): Replace gcc diagnostic workaround with SIZEOF_LONG vs. SIZEOF_INT check. * elf.c (_bfd_elf_get_reloc_upper_bound): Likewise. * elf64-sparc.c (elf64_sparc_get_reloc_upper_bound): Likewise. * mach-o.c (bfd_mach_o_get_reloc_upper_bound): Likewise.
2019-03-28Automatic date update in version.inGDB Administrator1-1/+1
2019-03-27Automatic date update in version.inGDB Administrator1-1/+1
2019-03-26Automatic date update in version.inGDB Administrator1-1/+1
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