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2025-05-09aarch64: Add new test mov-wide.dAlice Carlotti2-0/+86
Only movn was previously untested.
2025-05-09aarch64: Add new test exception-generation.dAlice Carlotti2-0/+54
svc and dcps* were already tested, but are included here as part of the same encoding group.
2025-05-09aarch64: Add new test conditional-compare.dAlice Carlotti2-0/+153
The register form of ccmp was already tested.
2025-05-09aarch64: Add new test branch-cond-pseudos.dAlice Carlotti2-0/+73
beq, bne, bcs and bcc were already tested, and bge and ble are also used in scfi tests.
2025-05-09aarch64: Add new test ldst-unpriv.dAlice Carlotti2-0/+125
All instructions were previously untested.
2025-05-09aarch64: Add new test ldst-extend-general.dAlice Carlotti2-0/+307
All instructions were previously untested.
2025-05-09aarch64: Add new test dp-general-two-source.dAlice Carlotti2-0/+178
lsl was already tested but is included here as part of the same encoding group.
2025-05-09aarch64: Add new test dp-general-one-source.dAlice Carlotti2-0/+88
rev16 and the 64-bit rev/rev64 instructions were already tested, but are included here as part of the same encoding group.
2025-05-09aarch64: Add new test addsub-carry.dAlice Carlotti2-0/+102
All instructions were previously untested.
2025-05-09aarch64: Add new test advsimd-scalar-doubling-mul.dAlice Carlotti2-0/+194
All instructions were previously untested.
2025-05-09aarch64: Add new test advsimd-scalar-two-reg-misc.dAlice Carlotti2-0/+221
sqabs, sqneg, abs and neg were already tested, but are included here as part of the same encoding group.
2025-05-09aarch64: Add new test advsimd-scalar-shift-immediate.dAlice Carlotti2-0/+356
All instructions were previously untested.
2025-05-09aarch64: Add new test advsimd-scalar-three-same.dAlice Carlotti2-0/+414
All instructions were previously untested.
2025-05-09aarch64: Add new test advsimd-copy.dAlice Carlotti2-0/+359
Only smov and the second dup variant were previously untested. However, the only test for umov was a disassembly test with -M no-aliases, and the first dup variant was only tested in assembly in diagnostic.d with the non-architectural syntax `dup v0.2d, v1.2d[0]`.
2025-05-09aarch64: Add new test advsimd-permute.dAlice Carlotti2-0/+501
All instructions were previously untested.
2025-05-09aarch64: Add new test advsimd-modified-immediate.dAlice Carlotti2-0/+201
All instructions (7 opcode table entries) were previously untested.
2025-05-09aarch64: Add new test advsimd-two-reg-misc-hilo.dAlice Carlotti4-0/+1454
All instructions were previously untested.
2025-05-09aarch64: Add new test advsimd-two-reg-misc.dAlice Carlotti2-0/+830
sqabs, abs, not, mvn, sqneg and neg were already tested, and cmeq was already assembled in an error test (sve-reg-diagnostic.d), but they are all included here as part of the same encoding group.
2025-05-09aarch64: Add new test advsimd-mul-element.dAlice Carlotti2-0/+750
All instructions were previously untested.
2025-05-09aarch64: Add new test advsimd-widening-narrowing.dAlice Carlotti2-0/+1210
All instructions were previously untested.
2025-05-09aarch64: Add new test advsimd-three-same.dAlice Carlotti2-0/+2453
All instructions except orr/mov were previously untested.
2025-05-09aarch64: Add missing widening fmops testAlice Carlotti3-10/+8
Also remove the valid instructions from the test for invalid instructions - this meant that the instruction was previously being tested for assembly but not disassembly.
2025-05-09aarch64: Add tests for fabd, urecpe and ursqrtAlice Carlotti2-2/+22
Other instructions in the encoding group are tested in advsimd-fp16.d, so add these instructions to the existing test file.
2025-05-09aarch64: Add tests for fcvt, fcvtzs and fcvtzuAlice Carlotti2-2/+52
Other instructions in the encoding group are tested in float-fp16.d, so add these instructions to the existing test file.
2025-05-09aarch64: Add tests for csdb and eret to system.dAlice Carlotti2-0/+4
2025-05-09aarch64: Add test for ands and bicsAlice Carlotti2-0/+107
The other instructions in the encoding group are tested in shifted.d, so add these to the existing test file.
2025-05-09aarch64: Adjust float-fp16.d test patternsAlice Carlotti1-164/+164
Adjust the test to match instruction addresses of any length.
2025-05-09aarch64: Adjust advsimd-fp16.d test patternsAlice Carlotti1-569/+569
Adjust the test to match instruction addresses of any length, and escape literal '.' characters for a stricter match.
2025-05-09aarch64: Adjust shifted.d test patternsAlice Carlotti1-727/+727
Adjust the test to match any instruction addresses, so that the test can be extended more easily.
2025-05-09aarch64: Eliminate AARCH64_OPND_SVE_ADDR_RAlice Carlotti7-2325/+2286
Adjust parsing for AARCH64_OPND_SVE_ADDR_RR{_LSL*} operands to accept implicit XZR offsets. Add new AARCH64_OPND_SVE_ADDR_RM{_LSL*} operands to support instructions where an XZR offset is allowed but must be specified explicitly. This allows the removal of the duplicate opcode table entries using AARCH64_OPND_SVE_ADDR_R.
2025-05-09aarch64: Disallow invalid SVE addressing modesAlice Carlotti6-9/+106
The fix for PR22988 in 2018 added a new operand AARCH64_OPND_SVE_ADDR_R to support implicit XZR offsets, but this fix had several flaws that meant it accepted several invalid addressing modes: 1. The base register type wasn't properly checked when the optional register offset was omitted. This meant that ldff1b {z1.s}, p1/z,[z1.d] was parsed as if it were ldff1b z1.d, p1/z, [x1.d, xzr]. 2. The explicit offset parsing didn't include a shift type, so the new operand would incorrectly parse ldff1h{z0.s}, p0/z, [x0, x0] as if it were ldff1h{z0.s}, p0/z, [x0, x0, lsl #1]. 3. Regardless of the above correctness issues, support for implicit offsets should have been added by amending the operands in the existing opcode table entries, instead of adding new duplicate table entires. Issue 1 can be fixed by using an "if" instead of an "else if" in parse_operands, while issue 2 can be fixed by failing when the first condition is false. This patch applies just these two fixes, leaving issue 3 to be addressed in a subsequent more invasive patch. The instructions removed from the test sme-5.d are architecturally invalid. The new tests cover all of the affected ldff1 variants; the issue also affected SME ZA ld1*/st1* instructions using the same operand type.
2025-05-09RISC-V: Support Zce 1.0Jerry Zhang Jian6-1/+35
Zce is the extension defined in code-size-reduction Ref: https://github.com/riscvarchive/riscv-code-size-reduction Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2025-05-09RISC-V: Base for complex extension implicationsTsukasa OI1-4/+7
Thanks to the commit 48558a5e5471 ("RISC-V: Allow nested implications for extensions"), we can write complex extension implications in theory. However, to actually do that, we need to pass more information to check_func. For example, we want to imply 'Zcf' from 'F' if and only if the 'Zce' extension is also enabled and XLEN is 32. Passing rps is a way to enable this. This commit prepares for such complex extension implications.
2025-05-09RISC-V: Add augmented hypervisor extension 'sha' support.Jiawei5-1/+9
The augmented hypervisor extension 'sha'[1] is a new profile-defined extension that captures the full set of features that are mandated to be supported along with the H extension. https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile bfd/ChangeLog: * elfxx-riscv.c: New extension and implies. gas/ChangeLog: * NEWS: New extension. * testsuite/gas/riscv/imply.d: New test for sha. * testsuite/gas/riscv/imply.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension.
2025-05-09RISC-V: Add Privileged Architecture 1.13 CSRs.Jiawei19-5/+2525
This patch support RISC-V Privileged Architecture 1.13 CSRs 'medelegh' and 'hedelegh'. More details between 1.12 and 1.13 see [1]. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv-preface.adoc Version log: Remove gas/po changes. bfd/ChangeLog: * cpu-riscv.c: New option. * cpu-riscv.h (enum riscv_spec_class): Ditto. binutils/ChangeLog: * doc/binutils.texi: New option. gas/ChangeLog: * NEWS: Add priv-1.13 support. * config/tc-riscv.c: New option. * configure: Ditto. * configure.ac: Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: New warning. * testsuite/gas/riscv/csr-version-1p11.d: New CSR. * testsuite/gas/riscv/csr-version-1p11.l: New warning. * testsuite/gas/riscv/csr-version-1p12.d: New CSR. * testsuite/gas/riscv/csr-version-1p12.l: New warning. * testsuite/gas/riscv/csr.s: New CSR. * testsuite/gas/riscv/attribute-15.d: New test. * testsuite/gas/riscv/attribute-16.d: New test. * testsuite/gas/riscv/csr-version-1p13.d: New test. * testsuite/gas/riscv/csr-version-1p13.l: New test. include/ChangeLog: * opcode/riscv-opc.h (CSR_MEDELEGH): New CSR. (CSR_HEDELEGH): Ditto. (DECLARE_CSR): Ditto.
2025-05-09RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslspChao-ying Fu11-0/+329
Spec: https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp with verison 1.0. Passed binutils testsuites of targets elf32/elf64/linux32/linux64. Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
2025-05-09Automatic date update in version.inGDB Administrator1-1/+1
2025-05-08Change substitute_path_component to use std::stringTom Tromey1-43/+24
This changes substitute_path_component to use std::string and std::string_view, simplifying it greatly and removing some manual memory management. Approved-By: Simon Marchi <simon.marchi@efficios.com>
2025-05-08Move substitute_path_componentTom Tromey5-108/+85
This moves substitute_path_component out of utils.c. I considered making a new file for this (still could if someone wants that), but since the only caller is in auto-load.c, I moved it there instead. I've also moved the tests into auto-load.c as well. This way substitute_path_component can be static. Approved-By: Simon Marchi <simon.marchi@efficios.com>
2025-05-08Automatic date update in version.inGDB Administrator1-1/+1
2025-05-08windres: buffer overflowAlan Modra1-0/+5
bin_to_res_menuexitems can be called with random data offsets (and thus remaining lengths), confusing code that expects 4-byte aligned data. Prevent an item length adjustment for alignment exceeding the remaining length and then overflowing.
2025-05-08Remove unnecessary use of pragma once in pr25618 testAlan Modra2-2/+0
2025-05-07s390: Fix format specifier for VR in disassemblerJens Remus1-1/+1
Vector register (VR) numbers are unsigned. Use format specifier %u instead of %i. Reported-by: Florian Krohm <flo2030@eich-krohm.de> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-05-07Automatic date update in version.inGDB Administrator1-1/+1
2025-05-06Do not set yydebug in cp-name-parser.yTom Tromey1-3/+5
This reverts the change to cp-name-parser.y, avoiding a TSan report. Approved-By: Simon Marchi <simon.marchi@efficios.com>
2025-05-06Remove kfail from templates.expTom Tromey1-4/+1
templates.exp has one remaining kfail. However, the output in question has been stabilized ever since the cp-name-parser.y work -- the test just wasn't updated. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=8617 Reviewed-By: Keith Seitz <keiths@redhat.com>
2025-05-06Rewrite bug references in templates.expTom Tromey1-22/+22
templates.exp has many kfails that refer to old GNATS bug numbers. This patch updates them to refer to Bugzilla instead. Reviewed-By: Keith Seitz <keiths@redhat.com>
2025-05-06Revert "gdb: support zero inode in generate-core-file command"Andrew Burgess1-1/+1
This reverts commit 1e21c846c275fc6e387ca903a129096be2a53d0b. This change was causing unexpected mappings to be included in the core files generated by GDB, which was triggering warnings when GDB opened a core file, like this: warning: Can't open file [stack] during file-backed mapping note processing warning: Can't open file [vvar] during file-backed mapping note processing For now I'm reverting the above commit and will come to the list again when I have a solution that addresses the original issue without also including the unexpected mappings.
2025-05-06Handle field with dynamic bit offsetTom Tromey5-22/+161
I discovered that GCC emitted incorrect DWARF for the test case included in this patch. Eric wrote a fix for GCC, but then he found that gdb crashed on the resulting file. This test has a field that is at a non-constant bit offset from the start of the type. DWARF 5 does not allow for this situation (I've sent a report to the DWARF list), but DWARF 3 did allow for this via a combination of an expression for the byte offset and then the use of DW_AT_bit_offset. This looks like: <5><117a>: Abbrev Number: 17 (DW_TAG_member) <117b> DW_AT_name : (indirect string, offset: 0x1959): another_field ... <1188> DW_AT_bit_offset : 6 <1189> DW_AT_data_member_location: 6 byte block: 99 3d 1 0 0 22 (DW_OP_call4: <0x1193>; DW_OP_plus) ... <3><1193>: Abbrev Number: 2 (DW_TAG_dwarf_procedure) <1194> DW_AT_location : 15 byte block: 97 94 1 37 1a 32 1e 23 7 38 1b 31 1c 23 3 (DW_OP_push_object_address; DW_OP_deref_size: 1; DW_OP_lit7; DW_OP_and; DW_OP_lit2; DW_OP_mul; DW_OP_plus_uconst: 7; DW_OP_lit8; DW_OP_div; DW_OP_lit1; DW_OP_minus; DW_OP_plus_uconst: 3) Now, that combination is not fully general, in that the bit offset must be a constant -- only the byte offset may really vary. However, I couldn't come up with a situation where full generality is needed, mainly because GNAT won't seem to pack fields into the padding of a variable-length array. Meanwhile, the reason for the gdb crash is that the code handling DW_AT_bit_offset assumes that the byte offset is a constant. This causes an assertion failure. This patch arranges for DW_AT_bit_offset to be applied during field resolution, when needed.
2025-05-06Introduce apply_bit_offset_to_field helper functionTom Tromey3-40/+72
This patch makes a new function, apply_bit_offset_to_field, that is used to handle the logic of DW_AT_bit_offset. Currently there is just a single caller, but the next patch will change this.
generated by cgit v1.1 at 2025-07-13 14:38:56 +0000