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2022-12-23ld: Write DEBUG_S_LINES entries in PDB fileMark Harmstone5-6/+204
2022-12-23ld: Fix segfault in populate_publics_streamMark Harmstone1-0/+3
2022-12-23ld: Write DEBUG_S_FILECHKSMS entries in PDBsMark Harmstone8-12/+709
2022-12-23ld: Generate PDB string tableMark Harmstone6-6/+472
2022-12-23pdb build fixesAlan Modra5-101/+156
Enable compilation of ld/pdb.c just for x86, as is done for bfd/pdb.c. This reduces the size of ld and is necessary with the following patches that call a COFF-only bfd function from ld/pdb.c. Without it we'd break every non-COFF target build.
2022-12-23sim: lm32/m32r: drop redundant opcode/cgen.h includeMike Frysinger2-2/+0
The xxx-desc.h header file already includes this, and it's how the other cgen ports are getting it, so drop it from these two.
2022-12-23sim: ppc: drop unused types from sim-main.hMike Frysinger1-7/+0
The common sim headers should define these for us already, so there's no need for the ppc header to set them up.
2022-12-23sim: cgen: move symcat.h include to where it's usedMike Frysinger10-5/+9
Move this out of the global sim-main.h and to the few files that actually use functions from it. Only the cgen ports were pulling this, so this makes cgen & non-cgen behave more the same.
2022-12-23sim: cgen: move cgen-types.h include to cgen-defs.hMike Frysinger8-7/+2
The cgen-types.h header sets up types that are needed by cgen-defs.h, so move the include out of sim-main.h and to that header. It might be needed in other specific modules, but for now let's kick it out of sim-main.h to make some progress. Things still build with just this.
2022-12-23Revert "sim: mn10300: drop unused sim-main.c"Mike Frysinger1-0/+9
This reverts commit 681a422b855e4b20086554b170dae051361f00c7. I missed that this was included via common/sim-inline.c. I thought I had grepped the top of the tree, but I must have only done mn10300. Add a comment to make it clear where/how this file is used.
2022-12-22sim: mn10300: drop unused sim-main.cMike Frysinger1-4/+0
Nothing compiles or references this, so punt it.
2022-12-22sim: endian: move bfd.h from header to sourceMike Frysinger2-2/+2
The bfd APIs are used only by sim-n-endian.h which is only included by sim-endian.c, so move the bfd.h include there and out of sim-endian.h which is included by many other modules.
2022-12-22sim: move bfd.h include out of sim-main.hMike Frysinger20-13/+16
Not all arches include this in sim-main.h, and the ones that do don't actually use bfd defines in the sim-main.h header. Prune it to make sim-main.h simpler so we can kill it off entirely in the future. We add the include to the files that utilize e.g. bfd_vma though.
2022-12-22sim: mcore: replace custom "word" type with int32_tMike Frysinger2-33/+30
This is a 32-bit architecture with 32-bit registers, so replace the custom "word" long int typedef with an explicit int32_t. This is a correctness fix since long will be 64-bits on most 64-bit hosts.
2022-12-22sim: moxie: replace custom "word" type with int32_tMike Frysinger1-13/+11
This is a 32-bit architecture with 32-bit registers, so replace the custom "word" int typedef with an explicit int32_t. Practically speaking, this produces the same code, but it should hopefully make it easier to merge common code in the future.
2022-12-22sim: cr16/d10v/mcore/moxie: clean up unused word & uword typesMike Frysinger4-10/+0
Nothing actually uses these, so punt them. Some of the ports are using local "word" types, but we'll clean those up in a follow up.
2022-12-22sim: mips: trim redundant igen settingsMike Frysinger2-18/+0
These variables are setting the same value as the defaults. Trim this redundant logic to make it easier to see the real differences so we can try to keep unifying cases.
2022-12-22sim: mips: merge mips64* with existing multi-run buildMike Frysinger2-10/+4
Change the default (unhandled) mips64* targets to use the existing mips64 multi-run build. It already handles the formats, we just have to list the mips8000 bfd for it.
2022-12-22sim: mips: merge mips64vr5000 with existing multi-run buildMike Frysinger2-8/+2
The existing mips64vr-* multi-run build already handles mips5000 targets, so reuse that for mips64vr5* targets too. This moves more logic from build-time to runtime so we can have a single binary that supports many targets.
2022-12-23RISC-V: Relax the order checking for the architecture stringNelson Chu8-149/+83
* riscv-toolchain-conventions, PR, https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14 Issue, https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11 * Refer to the commit afc41ffb, RISC-V: Reorder the prefixed extensions which are out of order. In the past we only allow to reorder the prefixed extensions. But according to the PR 14 in the riscv-toolchain-convention, we can also relax the order checking to allow the whole extensions be written out of orders, including the single standard extensions and the prefixed multi-letter extensions. Just that we still need to follow the following rules as usual, 1. prefixed extensions need to be seperated with `_'. 2. prefixed extensions need complete <major>.<minor> version if set. Please see the details in the march-ok-reorder gas testcase. Passed the riscv-gnu-toolchain regressions. bfd/ * elfxx-riscv.c (enum riscv_prefix_ext_class): Changed RV_ISA_CLASS_UNKNOWN to RV_ISA_CLASS_SINGLE, since everything that does not belong to the multi-keyword will possible be a single extension for the current parser. (parse_config): Likewise. (riscv_get_prefix_class): Likewise. (riscv_compare_subsets): Likewise. (riscv_parse_std_ext): Removed, and merged with riscv_parse_prefixed_ext into riscv_parse_extensions. (riscv_parse_prefixed_ext): Likewise. (riscv_parse_subset): Only need to call riscv_parse_extensions to parse both single standard and prefixed extensions. gas/ * testsuite/gas/riscv/march-fail-order-std.d: Removed since the relaxed order checking. * testsuite/gas/riscv/march-fail-order-std.l: Likewise. * testsuite/gas/riscv/march-fail-order-x-std.d: Likewise. * testsuite/gas/riscv/march-fail-order-z-std.d: Likewise. * testsuite/gas/riscv/march-fail-order-zx-std.l: Likewise. * testsuite/gas/riscv/march-fail-unknown-std.l: Updated. * testsuite/gas/riscv/march-ok-reorder.d: New testcase.
2022-12-22sim: drop unused SIM_ADDR type [PR sim/7504]Mike Frysinger1-6/+0
Now that sim APIs either use 64-bit addresses all the time, or more appropriate target-specific types, drop this now-unused 32-bit-only address type. Bug: https://sourceware.org/PR7504
2022-12-22sim: mips: switch from SIM_ADDR to address_wordMike Frysinger2-31/+13
The latter type matches the address size configured for this sim. Also take the opportunity to simplify printf logic by leveraging PRI* macros.
2022-12-22sim: v850: switch from SIM_ADDR to address_wordMike Frysinger2-4/+4
The latter type matches the address size configured for this sim.
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger14-60/+64
We've been using SIM_ADDR which has always been 32-bit. This means the upper 32-bit address range in 64-bit sims is inaccessible. Use 64-bit addresses all the time since we want the APIs to be stable regardless of the active arch backend (which can be 32 or 64-bit). The length is also 64-bit because it's completely feasible to have a program that is larger than 4 GiB in size/image/runtime. Forcing the caller to manually chunk those accesses up into 4 GiB at a time doesn't seem useful to anyone. Bug: https://sourceware.org/PR7504
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger11-12/+12
Since SIM_ADDR is always 32-bit, it might truncate the address with 64-bit ELFs. Since we load that addr from the bfd, use the bfd_vma type which matches the bfd_get_start_address API.
2022-12-22sim: m32r: include sim-hw.h for sim_hw_parseMike Frysinger1-0/+1
2022-12-23COFF build-id writes uninitialised data to fileAlan Modra3-9/+5
1) The first write in write_build_id wrote rubbish past the struct external_IMAGE_DEBUG_DIRECTORY, which was later overwritten with correct data. No user visible problem there, except that tools like valgrind complain. 2) The size for the pdb name was incorrectly calculated. * emultempl/pe.em (write_build_id): Write the debug directory, not the entire section contents. (setup_build_id): Add size for the base name of pdb_name, not the full path. * emultempl/pep.em: Likewise. * testsuite/ld-pe/pdb2-section-contrib.d: Update.
2022-12-22sim: mips: merge mips64vr4300 with existing multi-run buildMike Frysinger2-8/+2
The existing mips64vr-* multi-run build already handles mips4300 targets, so reuse that for mips64vr43* targets too. This moves more logic from build-time to runtime so we can have a single binary that supports many targets.
2022-12-23Automatic date update in version.inGDB Administrator1-1/+1
2022-12-22sframe: doc: update documentation for pauth key in SFrame FDEIndu Bhagat1-1/+7
ChangeLog: * libsframe/doc/sframe-spec.texi
2022-12-22gas: sframe: testsuite: add testcase for .cfi_b_key_frameIndu Bhagat3-0/+64
This is actually a composite test that checks SFrame unwind information generation for both the .cfi_negate_ra_state and .cfi_b_key_frame directives on aarch64. ChangeLog: * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d: New test. * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.s: Likewise. * testsuite/gas/cfi-sframe/cfi-sframe.exp: Run new test.
2022-12-22objdump/readelf: sframe: emit marker for SFrame FDE with B keyIndu Bhagat1-0/+19
ChangeLog: * libsframe/sframe-dump.c (is_sframe_abi_arch_aarch64): New definition. (dump_sframe_func_with_fres): Emit a string if B key is used.
2022-12-22gas: sframe: add support for .cfi_b_key_frameIndu Bhagat3-5/+26
Gather the information from the DWARF FDE on whether frame's return addresses are signed using the B key or A key. Reflect the information in the SFrame counterpart data structure, the SFrame FDE. ChangeLog: * gas/gen-sframe.c (get_dw_fde_pauth_b_key_p): New definition. (sframe_v1_set_func_info): Add new argument for pauth_key. (sframe_set_func_info): Likewise. (output_sframe_funcdesc): Likewise. * gas/gen-sframe.h (struct sframe_version_ops): Add new argument to the function pointer declaration. * gas/sframe-opt.c (sframe_convert_frag): Handle pauth_key.
2022-12-22sframe.h: add support for .cfi_b_key_frameIndu Bhagat1-6/+19
ARM 8.3 provides five separate keys that can be used to authenticate pointers. There are two key for executable (instruction) pointers. The enum pointer_auth_key in gas/config/tc-aarch64.h currently holds two keys: enum pointer_auth_key { AARCH64_PAUTH_KEY_A, AARCH64_PAUTH_KEY_B }; Analogous to the above, in SFrame format V1, a bit is reserved in the SFrame FDE to indicate which key is used for signing the frame's return addresses: - SFRAME_AARCH64_PAUTH_KEY_A has a value of 0 - SFRAME_AARCH64_PAUTH_KEY_B has a value of 1 Note that the information in this bit will always be used along with the mangled_ra_p bit, the latter indicates whether the return addresses are mangled/contain PAC auth bits. include/ChangeLog: * sframe.h (SFRAME_AARCH64_PAUTH_KEY_A): New definition. (SFRAME_AARCH64_PAUTH_KEY_B): Likewise. (SFRAME_V1_FUNC_INFO): Adjust to accommodate pauth_key. (SFRAME_V1_FUNC_PAUTH_KEY): New macro. (SFRAME_V1_FUNC_INFO_UPDATE_PAUTH_KEY): Likewise.
2022-12-22gas: re-arrange listing output for .irp and alikeJan Beulich2-14/+14
It is kind of odd to have the expansions of such constructs ahead of their definition in listings with macro expansion enabled. Adjust this by pulling ahead the output of the definition lines, taking care to avoid producing a listing line for (non-existing) line 0 when the source is stdin. Note that with the code movement the conditional operator isn't necessary anymore - list->line now match up.
2022-12-22x86: correct/improve TSX controlsJan Beulich4-5/+38
TSXLDTRK takes RTM as a prereq. Additionally introduce an umbrella "tsx" extension option covering both RTM and HLE, paralleling the "abm" one we already have.
2022-12-22x86: add dependencies on SVMEJan Beulich3-11/+53
SEV-ES is an extension to SVME. SNP in turn is an extension to SEV-ES, and yet in turn RMPQUERY is a SNP extension. Note that cpu_arch[] has no SNP entry, so CPU_ANY_SNP_FLAGS remains unused (just like CPU_SNP_FLAGS already is).
2022-12-22x86: add dependencies on VMXJan Beulich3-5/+36
Both EPT and VMFUNC are extensions to VMX.
2022-12-22x86: correct XSAVE* dependenciesJan Beulich2-8/+10
Like various other features AMX-TILE takes XSAVE as a prereq. XSAVES, unconditionally using compacted format, in turn effectively takes XSAVEC as a prereq (an SDM clarification to this effect is in the works).
2022-12-22x86: correct dependencies of a few AVX512 sub-featuresJan Beulich3-16/+16
Like AVX512-FP16, several other extensions require wider than 16-bit mask registers. As a result they take AVX512BW as a prereq, not (just) AVX512F. Which in turn points out wrong expectations in the noavx512-1 testcase.
2022-12-22x86: rework noavx512-1 testcaseJan Beulich3-587/+415
So far the set of ".noavx512*" has been accumulating, which isn't ideal. In particular this hides issues with dependencies between features. Switch back to the default ISA before disabling a particular subset. Furthermore limit redundancy by wrapping the repeated block of insns in an .irp.
2022-12-22x86: add dependencies on AVX2Jan Beulich3-11/+33
Like AVX-VNNI both VAES and VPCLMUL take AVX2 as a prereq, for operating on up to 256-bit packed integer vectors.
2022-12-22x86: correct SSE dependenciesJan Beulich3-52/+96
SSE itself takes FXSR as a prereq. Like AES, PCLMUL, and SHA both GFNI and KL take SSE2 as a prereq, for operating on packed integers. And while correcting KL also record it as a prereq to WIDEKL.
2022-12-22x86: correct what gets disabled by certain ".arch .no*"Jan Beulich1-18/+18
Features with prereqs as well as features with dependents cannot re-use CPU_*_MASK for the 3rd argument of SUBARCH() - they need to use CPU_ANY_*_MASK in order to avoid disabling too many (when there are prereqs) and/or too few (when there are dependents) features. Generally any CPU_ANY_*_MASK which exist should not remain unused. Exceptions are - FISTTP which has no corresponding entry in cpu_arch[], - IAMCU which is a base architecture and hence uses ARCH(), not SUBARCH() (only extensions can be disabled, but unlike for Cpu*86 it would be a little more clumsy to suppress generating of the #define).
2022-12-22x86: re-work ISA extension dependency handlingJan Beulich3-1024/+910
Getting both forward and reverse ISA dependencies right / consistent has been a permanent source of mistakes. Reduce what needs specifying manually to just the direct forward dependencies. Transitive forward dependencies as well as reverse ones are now derived and hence cannot go out of sync anymore (at least in the vast majority of cases; there are a few special cases to still take care of manually). In the course of this several CPU_ANY_*_FLAGS disappear, requiring adjustment to the assembler's cpu_arch[]. Note that to retain the correct reverse dependency of AVX512F wrt AVX512-VP2INTERSECT, the latter has the previously missing AVX512F prereq added. Note further that to avoid adding the following undue prereqs: * ATHLON, K8, and AMDFAM10 gain CMOV and FXSR, * IAMCU gains 387, auxiliary table entries (including a colon-separated modifier) are introduced in addition to the ones representing from converting the old table. To maintain forward-only dependencies between AVX (XOP) and SSE* (SSE4a) (i.e. "nosse" not disabling AVX), reverse dependency tracking is artifically suppressed. As a side effect disabling of SSE or SSE2 will now also disable AES, PCLMUL, and SHA (respective elements were missing from CPU_ANY_SSE2_FLAGS).
2022-12-21sim: mips: match target on cpu settingsMike Frysinger2-26/+26
We don't need to enforce larger target settings when the only thing the sim should care about is the CPU target. So reduce most of the target matches to only check the CPU.
2022-12-21sim: mips: move fpu bitsize defines to top-level configureMike Frysinger8-71/+44
This drops support for the --enable-sim-float configure option, but it's not clear anyone ever actually used that. Eventually we'll want this to be a runtime option anyways.
2022-12-21sim: mips: move bitsize defines to top-level configureMike Frysinger8-99/+48
Since the msb value is always defined as the wordsize-1, stop hardcoding that value directly, and use a CPP value instead.
2022-12-21sim: mips: move subtarget defines to top-level configureMike Frysinger8-43/+68
We want to kill off mips/configure entirely. Move this small part out now to get started.
2022-12-21sim: mips: always resolve active bfd mach dynamicallyMike Frysinger3-106/+3
Don't assume that the default bfd that we configured for is the one that is always active when running a program. We already have access to the real runtime value, so use it directly. This simplifies the code quite a bit, and will make it easier to support multiple mach's in a single binary.
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