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2017-05-31Make libiberty/waitpid.c compile without warnings on MinGWEli Zaretskii2-0/+10
libiberty/ChangeLog: 2017-05-31 Eli Zaretskii <eliz@gnu.org> * waitpid.c (wait) [__MINGW32__]: Define as a macro that calls _cwait, so that this function works on MinGW.
2017-05-31Fix MinGW compilation warnings due to environ.hEli Zaretskii2-0/+6
include/ChangeLog: 2017-05-31 Eli Zaretskii <eliz@gnu.org> * environ.h: Add #ifndef guard.
2017-05-31Automatic date update in version.inGDB Administrator1-1/+1
2017-05-30Fix calculation of R_ARM_RHM_ALU_PREL_11_0 relocation when used with a SUB ↵Casey Smith2-1/+9
instruction. PR ld/21523 * elf32-arm.c (elf32_arm_final_link_relocate): Install an absolute value when processing the R_ARM_THM_ALU_PREL_11_0 reloc.
2017-05-30[ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov4-26/+126
Currently print_insn_arc relies on BFD mach and ELF private headers to distinguish between various ARC architectures. Sometimes those values are not correct or available, mainly in the case of debugging targets without and ELF file available. Changing a BFD mach is not a problem for the debugger, because this is a generic BFD field, and GDB, for example, already sets it according to information provided in XML target description or specified via GDB 'set arch' command. However, things are more complicated for ELF private headers, since it requires existing of an actual ELF file. To workaround this problem this patch allows CPU model to be specified via disassemble info options. If CPU is specified in options, then it will take a higher precedence than whatever might be specified in ELF file. This is mostly needed for ARC EM and ARC HS, because they have the same "architecture" (mach) ARCv2 and differ in their private ELF headers. Other ARC architectures can be distinguished between each other purely via "mach" field. Proposed disassemble option format is "cpu=<CPU>", where CPU can be any valid ARC CPU name as supported by GAS. Note that this creates a seeming redundancy with objdump -m/--architecture option, however -mEM and -mHS still result in "ARCv2" architecture internally, while -Mcpu={HS,EM} would have an actual effect on disassembler. opcodes/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * arc-dis.c (enforced_isa_mask): Declare. (cpu_types): Likewise. (parse_cpu_option): New function. (parse_disassembler_options): Use it. (print_insn_arc): Use enforced_isa_mask. (print_arc_disassembler_options): Document new options. binutils/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * doc/binutils.texi: Document new cpu=... disassembler options for ARC.
2017-05-30[ARC] Add arc-cpu.def with processor definitionsAnton Kolesov4-26/+60
This patch extracts ARC CPU definitions from gas/config/tc-arc.c (cpu_types) into a separate file arc-cpu.def. This will allow reuse of CPU type definition in multiple places where it might be needed, for example in disassembler. This will help ensure that gas and disassembker use same option values for CPUs. arc-cpu.def file relies on preprocessor macroses which are defined somewhere else. This for example multiple C files to include arc-cpu.def, but define different macroses, therefore creating different structures. include/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * elf/arc-cpu.def: New file. gas/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * config/tc-arc.c (cpu_types): Include arc-cpu.def Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
2017-05-30[ARC] Implement compatible function for ARC BFD architecturesAnton Kolesov2-1/+50
The general rule for bfd_arch_info_type->compatible (A, B) is that if A and B are compatible, then this function should return architecture that is more "feature-rich", that is, can run both A and B. ARCv2, EM and HS all has same mach number, so bfd_default_compatible assumes they are the same, and returns an A. That causes issues with GDB, because GDB assumes that if machines are compatible, then "compatible ()" always returns same machine regardless of argument order. As a result GDB gets confused because, for example, compatible(ARCv2, EM) returns ARCv2, but compatible(EM, ARCv2) returns EM, hence GDB is not sure if they are compatible and prints a warning. bfd/ChangeLog: yyyy-mm-dd Anton Kolesov Anton.Kolesov@synopsys.com cpu-arc.c (arc_compatible): New function.
2017-05-30[ARC] Remove duplicate ARC600 entryAnton Kolesov2-7/+10
ARC600 is already defined as the head of the bfd_arch_arc. bfd/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * cpu-arc.c (arch_info_struct): Remove duplicate ARC600 entry.
2017-05-30Add bfd_get_file_size to get archive element sizeH.J. Lu6-54/+170
We can't use stat() to get archive element size. Add bfd_get_file_size to get size for both normal files and archive elements. bfd/ PR binutils/21519 * bfdio.c (bfd_get_file_size): New function. * bfd-in2.h: Regenerated. binutils/ PR binutils/21519 * objdump.c (dump_relocs_in_section): Replace get_file_size with bfd_get_file_size to get archive element size. * testsuite/binutils-all/objdump.exp (test_objdump_f): New proc. (test_objdump_h): Likewise. (test_objdump_t): Likewise. (test_objdump_r): Likewise. (test_objdump_s): Likewise. Add objdump tests on archive.
2017-05-30btrace: Store function segments as objects.Tim Wiederhake4-57/+82
2017-05-30btrace: Remove bfun_s vector.Tim Wiederhake2-67/+43
2017-05-30btrace: Replace struct btrace_function::segment.Tim Wiederhake5-37/+57
This used to hold a pair of pointers to the previous and next function segment that belong to this function call. Replace with a pair of indices into the vector of function segments.
2017-05-30btrace: Remove struct btrace_function::flow.Tim Wiederhake3-23/+32
This used to hold a pair of pointers to the previous and next function segment in execution flow order. It is no longer necessary as the previous and next function segments now are simply the previous and next elements in the vector of function segments.
2017-05-30btrace: Replace struct btrace_function::up.Tim Wiederhake5-64/+130
This used to hold a function segment pointer. Change it to hold an index into the vector of function segments instead.
2017-05-30btrace: Remove struct btrace_thread_info::{begin,end}.Tim Wiederhake4-113/+107
These are no longer needed and might hold invalid addresses once we change the vector of function segment pointers into a vector of function segment objects where a reallocation of the vector changes the address of its elements.
2017-05-30btrace: Remove constant arguments.Tim Wiederhake2-47/+51
2017-05-30btrace: Use function segment index in insn iterator.Tim Wiederhake4-29/+50
Remove FUNCTION pointer in struct btrace_insn_iterator and use an index into the list of function segments instead.
2017-05-30btrace: Use function segment index in call iterator.Tim Wiederhake4-119/+101
Remove FUNCTION pointer in struct btrace_call_iterator and use an index into the list of function segments instead.
2017-05-30btrace: Add btinfo to instruction interator.Tim Wiederhake3-0/+12
This will serve as the access path to the vector of function segments once the FUNCTION pointer in struct btrace_insn_iterator is removed.
2017-05-30btrace: Transfer ownership of pointers.Tim Wiederhake2-48/+66
Directly insert new btrace_function pointers into the vector and have the vector own these pointers. This allows us to later retrieve these objects by their number directly after creation whereas at the moment we have to wait until the vector is fully populated. This requires to pull btrace_thread_info through different functions but cleans up the code for freeing the trace.
2017-05-30btrace: Use std::vector in struct btrace_thread_information.Tim Wiederhake3-13/+18
2017-05-30S/390: Fix indentationAndreas Krebbel1-5/+5
gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (md_gather_operands): Fix indentation.
2017-05-30Fix NEWS formatting in GDB 8.0 sectionSimon Marchi2-16/+21
Change the GDB 8.0 section of the NEWS file to try to follow this order: * Functional changes * Added and removed configurations and targets * New commands * New options * MI changes In particular, there were two "New commands" sections. gdb/ChangeLog: * NEWS (Changes in GDB 8.0): Remove extra empty line. Move "Removed targets and native configurations" up. Merge duplicate "New commands" sub-sections. Add "New options" sub-sections.
2017-05-30gdb.base/watch-cond-infcall.exp: Don't run if target doesn't support infcallsSimon Marchi2-0/+10
This test requires calling a function in the inferior, and therefore it doesn't make sense to run it if the target doesn't support calling functions from GDB. gdb/testsuite/ChangeLog: * gdb.base/watch-cond-infcall.exp: Don't run if target doesn't support function calls from GDB.
2017-05-30S/390: Fix instruction types of csdtr and csxtrAndreas Krebbel4-6/+10
opcodes/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.c: Add new instruction types RRF_0URF and RRF_0UREFE. * s390-opc.txt: Fix instruction typs of csdtr and csxtr. gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/s390/zarch-z9-ec.d: Adjust csdtr and csxtr. * testsuite/gas/s390/zarch-z9-ec.s: Likewise.
2017-05-30S/390: Add missing operand to tb instructionAndreas Krebbel3-3/+3
gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/s390/esa-g5.d: Add missing operand to tb instruction. * testsuite/gas/s390/esa-g5.s: Likewise. opcodes/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.txt: Add missing operand to tb instruction.
2017-05-30S/390: Add ipte/idte variants with optional operandsAndreas Krebbel6-10/+29
This patch adds missing variants of ipte and idte instructions added with later CPU generations. ipte got an optional operand with z196 and another one with zEC12. idte got an optional operand with zEC12 opcodes/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.c: Add new idte/ipte variants. * s390-opc.txt: Likewise. gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/s390/zarch-z196.d: Add new idte/ipte variants. * testsuite/gas/s390/zarch-z196.s: Likewise. * testsuite/gas/s390/zarch-zEC12.d: Likewise. * testsuite/gas/s390/zarch-zEC12.s: Likewise.
2017-05-30S/390: Improve error checking for optional operandsAndreas Krebbel4-8/+34
So far we only had an instruction flag which made an arbitrary number of operands optional. This limits error checking capabilities for instructions marked that way. With this patch the optparm flag only allows a single optional parameter and another one is added (optparm2) allowing 2 optional arguments. Hopefully we won't need more than that in the future. So far there will be only a single use of optparm2. gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (md_gather_operands): Support new optparm2 instruction flag. include/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h: Add new instruction flags optparm2. opcodes/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-dis.c (s390_print_insn_with_opcode): Support new optparm2 instruction flag. * s390-mkopc.c (main): Recognize the new instruction flag when parsing instruction list.
2017-05-30S/390: Remove optional operand flag.Andreas Krebbel2-29/+6
The per operand optional flag hasn't been used for quite some time. Cleanup some remains. include/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h: Remove S390_OPERAND_OPTIONAL. gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (md_gather_operands): Remove code dealing with S390_OPERAND_OPTIONAL.
2017-05-30Automatic date update in version.inGDB Administrator1-1/+1
2017-05-29Automatic date update in version.inGDB Administrator1-1/+1
2017-05-28Automatic date update in version.inGDB Administrator1-1/+1
2017-05-27Automatic date update in version.inGDB Administrator1-1/+1
2017-05-26Add regcache raw_supply_integer and raw_collect_integer.Alan Hayward7-69/+213
Use these to replace instances of MAX_REGISTER_SIZE. * defs.h (copy_integer_to_size): New declaration. * findvar.c (copy_integer_to_size): New function. (do_cint_test): New selftest function. (copy_integer_to_size_test): Likewise. (_initialize_findvar): Likewise. * mips-fbsd-tdep.c (mips_fbsd_supply_reg): Use raw_supply_integer. (mips_fbsd_collect_reg): Use raw_collect_integer. * mips-linux-tdep.c (supply_32bit_reg): Use raw_supply_integer. (mips64_fill_gregset): Use raw_collect_integer (mips64_fill_fpregset): Use raw_supply_integer. * regcache.c (regcache::raw_supply_integer): New function. (regcache::raw_collect_integer): Likewise. * regcache.h: (regcache::raw_supply_integer): New declaration. (regcache::raw_collect_integer): Likewise.
2017-05-26Automatic date update in version.inGDB Administrator1-1/+1
2017-05-25Automatic date update in version.inGDB Administrator1-1/+1
2017-05-24Add unit test to gdbarch methods register_to_value and value_to_registerYao Qi6-0/+205
This patch adds one unit test for gdbarch methods register_to_value and value_to_register. The test pass different combinations of {regnu, type} to gdbarch_register_to_value and gdbarch_value_to_register. In order to do the test, add a new function create_new_frame to create a fake frame. It can be improved after we converted frame_info to class. In order to isolate regcache (from target_ops operations on writing registers, like target_store_registers), the sub-class of regcache in the test override raw_write. Also, in order to get the right regcache from get_thread_arch_aspace_regcache, the sub-class of regcache inserts itself to current_regcache. Suppose I incorrectly modified the size of buffer as below, @@ -1228,7 +1228,7 @@ ia64_register_to_value (struct frame_info *frame, int regnum, int *optimizedp, int *unavailablep) { struct gdbarch *gdbarch = get_frame_arch (frame); - gdb_byte in[MAX_REGISTER_SIZE]; + gdb_byte in[1]; /* Convert to TYPE. */ if (!get_frame_register_bytes (frame, regnum, 0, build GDB with "-fsanitize=address" and run unittest.exp, asan can detect such error ==2302==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fff98193870 at pc 0xbd55ea bp 0x7fff981935a0 sp 0x7fff98193598 WRITE of size 16 at 0x7fff98193870 thread T0 #0 0xbd55e9 in frame_register_unwind(frame_info*, int, int*, int*, lval_type*, unsigned long*, int*, unsigned char*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1119 #1 0xbd58c8 in frame_register(frame_info*, int, int*, int*, lval_type*, unsigned long*, int*, unsigned char*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1147 #2 0xbd6e25 in get_frame_register_bytes(frame_info*, int, unsigned long, int, unsigned char*, int*, int*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1427 #3 0x70080a in ia64_register_to_value /home/yao/SourceCode/gnu/gdb/git/gdb/ia64-tdep.c:1236 #4 0xbf570e in gdbarch_register_to_value(gdbarch*, frame_info*, int, type*, unsigned char*, int*, int*) /home/yao/SourceCode/gnu/gdb/git/gdb/gdbarch.c:2619 #5 0xc05975 in register_to_value_test /home/yao/SourceCode/gnu/gdb/git/gdb/gdbarch-selftests.c:131 Or, even if GDB is not built with asan, GDB just crashes. *** stack smashing detected ***: ./gdb terminated Aborted (core dumped) gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * Makefile.in (SFILES): Add gdbarch-selftests.c. (COMMON_OBS): Add gdbarch-selftests.o. * frame.c [GDB_SELF_TESTS] (create_new_frame): New function. * frame.h [GDB_SELF_TESTS] (create_new_frame): Declare. * gdbarch-selftests.c: New file. * regcache.h (regcache) <~regcache>: Mark it virtual if GDB_SELF_TEST. <raw_write>: Likewise.
2017-05-24Move current_regcache to regcache::current_regcacheYao Qi3-24/+52
This patches moves global variable current_regcache to a class regcache static variable (protected) so that the unit test I add in the following patch can access it (by means of extending class regcache in unit test). gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * regcache.c (current_regcache): Change it to regcache::current_regcache. (regcache_observer_target_changed): Update. (regcache_thread_ptid_changed): Make it a regcache static method. (regcache_thread_ptid_changed): Update. (class regcache_access): New. (current_regcache_test): Update. (_initialize_regcache): Update. * regcache.h: Include forward_list. (regcache): Declare regcache_thread_ptid_changed and declare registers_changed_ptid as friend.
2017-05-24Get register contents by register_size instead of TYPE_LENGTHYao Qi3-2/+11
We should use register_size to get register contents instead of TYPE_LENGTH. gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * i387-tdep.c (i387_register_to_value): Use register_size instead of TYPE_LENGTH. * m68k-tdep.c (m68k_register_to_value): Likewise.
2017-05-24Restrict i387_convert_register_pYao Qi2-2/+8
gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * i387-tdep.c (i387_convert_register_p): Return false if type code isn't TYPE_CODE_FLT.
2017-05-24Restrict alpha_convert_register_pYao Qi2-18/+16
This patch restricts alpha_convert_register_p from "TYPE_LENGTH (type) != 8" to "TYPE_LENGTH (type) == 4", because, - we have check "TYPE_LENGTH (valtype) == 4" in alpha_register_to_value and alpha_value_to_register, - alpha lds and sts instruction access 4 bytes, - comments "It might need to convert the [float] register into the corresponding [integer] type (see Alpha)" and integer is 4-byte on alpha, I think it is the right restrict condition to "TYPE_LENGTH (valtype) == 4". gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-tdep.c (alpha_convert_register_p): Return true if type length is 4. (alpha_register_to_value): Remove type length check. (alpha_value_to_register): Likewise.
2017-05-24Restrict ia64_convert_register_pYao Qi2-0/+6
gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * ia64-tdep.c (ia64_convert_register_p): Check type's code is TYPE_CODE_FLT.
2017-05-24Restrict m68k_convert_register_pYao Qi2-12/+9
We need to convert register if the type is float. Suppose we get a value from float point register, but its type is integer, we don't have to convert. This case may not exist in real code, but exist in my unit test case. warning: Cannot convert floating-point register value to non-floating-point type. Self test failed: arch m68k: self-test failed at gdb/git/gdb/findvar.c:1072 ok = gdbarch_register_to_value (gdbarch, frame, regnum, type, buf.data (), &optim, &unavail); 1072: SELF_CHECK (ok); gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * m68k-tdep.c (m68k_convert_register_p): Check type's code is TYPE_CODE_FLT or not.
2017-05-24Use XCNEW gdbarch_tdepYao Qi17-16/+35
This patch uses XCNEW gdbarch_tdep instead of XNEW. gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-tdep.c (alpha_gdbarch_init): Use XCNEW instead of XNEW. * avr-tdep.c (avr_gdbarch_init): Likewise. * bfin-tdep.c (bfin_gdbarch_init): Likewise. * cris-tdep.c (cris_gdbarch_init): Likewise. * ft32-tdep.c (ft32_gdbarch_init): Likewise. * lm32-tdep.c (lm32_gdbarch_init): Likewise. * m32r-tdep.c (m32r_gdbarch_init): Likewise. * m68hc11-tdep.c (m68hc11_gdbarch_init): Likewise. * mep-tdep.c (mep_gdbarch_init): Likewise. * microblaze-tdep.c (microblaze_gdbarch_init): Likewise. * mips-tdep.c (mips_gdbarch_init): Likewise. * mn10300-tdep.c (mn10300_gdbarch_init): Likewise. * moxie-tdep.c (moxie_gdbarch_init): Likewise. * msp430-tdep.c (msp430_gdbarch_init): Likewise. * sh64-tdep.c (sh64_gdbarch_init): Likewise. * v850-tdep.c (v850_gdbarch_init): Likewise.
2017-05-24Clear GDB internal state after each unit testYao Qi3-0/+14
GDB has some global variables, like sentinel_frame, current_thread_arch, and etc, we need to reset them after each unit tests. gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * selftest-arch.c (tests_with_arch): Call registers_changed and reinit_frame_cache. * selftest.c (run_self_tests): Likewise.
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi72-146/+205
With the changes done in previous patches, print_insn_XXX functions don't have to be external visible out of opcodes, because both gdb and objdump select disassemblers through a single interface. This patch moves these print_insn_XXX declarations from include/dis-asm.h to opcodes/disassemble.h, which is a new header added by this patch. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h: Move some function declarations to opcodes/disassemble.h. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-dis.c: Include disassemble.h, don't include dis-asm.h. * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. * moxie-dis.c, msp430-dis.c, mt-dis.c: * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. * z80-dis.c, z8k-dis.c: Likewise. * disassemble.h: New file.
2017-05-24Use disassemble.c:disassembler select rs6000 disassemblerYao Qi2-14/+5
Nowadays, rs6000 disassembler is selected in different ways in opcodes and gdb, opcodes: case bfd_arch_rs6000: if (mach == bfd_mach_ppc_620) disassemble = print_insn_big_powerpc; else disassemble = print_insn_rs6000; break; gdb: if (arch == bfd_arch_rs6000) set_gdbarch_print_insn (gdbarch, print_insn_rs6000); else set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); I am not sure which one is the right one. However, such selection should be done in one place instead of two. gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * rs6000-tdep.c (gdb_print_insn_powerpc): Remove. (rs6000_gdbarch_init): Don't call set_gdbarch_print_insn.
2017-05-24Use disassemble.c:disassembler select rl78 disassemblerYao Qi4-4/+15
This patch changes rl78 to let disassble.c:disassembler select disassembler. rl78_get_disassembler doesn't handle the case that abfd is NULL, so this patch also fix it. gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * rl78-tdep.c (rl78_gdbarch_init): Don't call set_gdbarch_print_insn. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * rl78-dis.c (rl78_get_disassembler): If parameter abfd is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
2017-05-24Use disassemble.c:disassembler select h8300 disassemblerYao Qi2-4/+5
opcodes/disassble.c:disassembler select h8300 disassembler like this, if (mach == bfd_mach_h8300h || mach == bfd_mach_h8300hn) disassemble = print_insn_h8300h; else if (mach == bfd_mach_h8300s || mach == bfd_mach_h8300sn || mach == bfd_mach_h8300sx || mach == bfd_mach_h8300sxn) disassemble = print_insn_h8300s; else disassemble = print_insn_h8300; which is the same as what gdb/h8300-tdpe.c does, switch (info.bfd_arch_info->mach) { case bfd_mach_h8300: ... set_gdbarch_print_insn (gdbarch, print_insn_h8300); case bfd_mach_h8300h: case bfd_mach_h8300hn: ... set_gdbarch_print_insn (gdbarch, print_insn_h8300h); case bfd_mach_h8300s: case bfd_mach_h8300sn: ... set_gdbarch_print_insn (gdbarch, print_insn_h8300s); so we can leave disassble.c:disassembler doing the selection. gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * h8300-tdep.c (h8300_gdbarch_init): Don't call set_gdbarch_print_insn.
2017-05-24Delegate opcodes to select disassembler in GDBYao Qi39-124/+73
This patch changes GDB to use disassembler selected by opcodes in default, so that we don't have to duplicate the selection logic again in GDB side. For example, gdb/score-tdep.c has static int score_print_insn (bfd_vma memaddr, struct disassemble_info *info) { if (info->endian == BFD_ENDIAN_BIG) return print_insn_big_score (memaddr, info); else return print_insn_little_score (memaddr, info); } and opcodes/disassemble.c has the same logic, case bfd_arch_score: if (big) disassemble = print_insn_big_score; else disassemble = print_insn_little_score; This patch removes the logic in GDB and calls opcodes/disassemble.c:disassembler in default to select disassembler. gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-tdep.c (alpha_gdbarch_init): Don't call set_gdbarch_print_insn. * arc-tdep.c (arc_gdbarch_init): Likewise. * arch-utils.c: include dis-asm.h. (default_print_insn): New function. * arch-utils.h (default_print_insn): Declare. * avr-tdep.c (avr_gdbarch_init): Don't call set_gdbarch_print_insn. * bfin-tdep.c (bfin_gdbarch_init): Likewise. * cris-tdep.c (cris_delayed_get_disassembler): Remove. (cris_gdbarch_init): Don't call set_gdbarch_print_insn. * frv-tdep.c (frv_gdbarch_init): Likewise. * ft32-tdep.c (ft32_gdbarch_init): Likewise. * gdbarch.sh (print_insn): Use default_print_insn. * gdbarch.c: Regenerated. * hppa-tdep.c (hppa_gdbarch_init): Likewise. * iq2000-tdep.c (iq2000_gdbarch_init): Likewise. * lm32-tdep.c (lm32_gdbarch_init): Likewise. * m32c-tdep.c (m32c_gdbarch_init): Likewise. * m32r-tdep.c (m32r_gdbarch_init): Likewise. * m68hc11-tdep.c (gdb_print_insn_m68hc11): Remove. (m68hc11_gdbarch_init): Don't call set_gdbarch_print_insn. * m68k-tdep.c (m68k_gdbarch_init): Likewise. * m88k-tdep.c (m88k_gdbarch_init): Likewise. * microblaze-tdep.c (microblaze_gdbarch_init): Likewise. * mn10300-tdep.c (mn10300_gdbarch_init): Likewise. * moxie-tdep.c (moxie_gdbarch_init): Likewise. * msp430-tdep.c (msp430_gdbarch_init): Likewise. * mt-tdep.c (mt_gdbarch_init): Likewise. * nds32-tdep.c (nds32_gdbarch_init): Likewise. * nios2-tdep.c (nios2_print_insn): Remove. (nios2_gdbarch_init): Don't call set_gdbarch_print_insn. * rx-tdep.c (rx_gdbarch_init): Likewise. * s390-linux-tdep.c (s390_gdbarch_init): Likewise. * score-tdep.c (score_print_insn): Remove. (score_gdbarch_init): Don't call set_gdbarch_print_insn. * sh-tdep.c (sh_gdbarch_init): Likewise. * sh64-tdep.c (sh64_gdbarch_init): Likewise. * sparc-tdep.c (sparc32_gdbarch_init): Likewise. * tic6x-tdep.c (tic6x_print_insn): Remove. (tic6x_gdbarch_init): Don't call set_gdbarch_print_insn. * tilegx-tdep.c (tilegx_gdbarch_init): Likewise. * v850-tdep.c (v850_gdbarch_init): Likewise. * vax-tdep.c (vax_gdbarch_init): Likewise. * xstormy16-tdep.c (xstormy16_gdbarch_init): Likewise. * xtensa-tdep.c (xtensa_gdbarch_init): Likewise.
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