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2024-07-09include: sframe: update code comments around SFrame FRE stack offsetsIndu Bhagat1-10/+12
This also amends the incorrect comment: offset3 (intrepreted as FP = CFA + offset2) If RA tracking is enabled, the offset to recover FP is at the third index. The SFrame format (V2) has assumption that if FP is saved on stack, RA must have been saved as well. This is true for the currently supported arch Aarch64. For AMD64, RA tracking per SFrame FRE is not necessary. In future, when extending support for more architectures, this will likely need to be revisited. include/ * sframe.h: Make the comments clearer by enumerating what happens per-ABI.
2024-07-09doc: sframe: segregate the ABI/arch-specific componentsIndu Bhagat1-28/+110
The recipe to interpret the SFrame FRE stack offsets is ABI/arch-specific. Although, there is other information in the specification that is ABI-specific (like pauth_key usage in AArch64), those pieces of information are now assimmilated in the SFrame specification in a way that it is fairly difficult to carve then out into a ABI/arch-specific section without confusing the readers. For future though, the specification must strive to keep the generic parts and ABI/arch-specific parts clearly laid out in separate sections. libsframe/ * doc/sframe-spec.texi: Reorder and adapt the contents.
2024-07-09LTO: Properly check wrapper symbolH.J. Lu6-8/+50
Add wrapper_symbol to bfd_link_hash_entry and set it to true for wrapper symbol. Set wrap_status to wrapper if wrapper_symbol is true in LTO. Note: Calling unwrap_hash_lookup to check for the wrapper symbol works only when there is a definition for the wrapped symbol since references to the wrapped symbol have been redirected to the wrapper symbol. bfd/ PR ld/31956 * linker.c (bfd_wrapped_link_hash_lookup): Set wrapper_symbol for wrapper symbol. include/ PR ld/31956 * bfdlink.h (bfd_link_hash_entry): Add wrapper_symbol. ld/ PR ld/31956 * plugin.c (get_symbols): Set wrap_status to wrapper if wrapper_symbol is set. * testsuite/ld-plugin/lto.exp: Run PR ld/31956 tests. * testsuite/ld-plugin/pr31956a.c: New file. * testsuite/ld-plugin/pr31956b.c: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-07-09Automatic date update in version.inGDB Administrator1-1/+1
2024-07-08aarch64: Add support for sve2p1 pmov instruction.srinath13-224/+766
This patch adds support for followign SVE2p1 instruction, spec is available here [1]. 1. PMOV (to vector) 2. PMOV (to predicate) Both pmov (to vector) and pmov (to predicate) have destination scalable vector register and source scalable vector register respectively as an operand with no suffix and optional index. To handle this case we have added 8 new operands in this patch. AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */ AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */ AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */ AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */ AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */ AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */ AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */ AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */ Since the index of the <Zd> operand is optional, the index part is dropped in disassembly in both the cases of "no index" or "zero index". As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D PMOV <Pn>.D, <Zd>{[<imm>]} Example1: Assembly: pmov z5[0], p6.d Disassembly: pmov z5, p6.d Assembly: pmov z5, p6.d Disassembly: pmov z5, p6.d Example2: Assembly: pmov p4.b, z5[0] Disassembly: pmov p4.b, z5 Assembly: pmov p4.b, z5 Disassembly: pmov p4.b, z5 [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 tbxq instruction.Srinath Parvathaneni7-160/+207
This patch adds support for SVE2p1 "tbxq" instruction, spec is available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 zipq[1-2] instructions.Srinath Parvathaneni7-162/+256
This patch adds support for SVE2p1 "zipq1" and "zipq2" instructions, spec is available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 uzpq[1-2] instructions.Srinath Parvathaneni7-153/+247
This patch adds support for SVE2p1 "uzpq1" and "uzpq2" instructions, spec is available here [1] [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 tblq instruction.Srinath Parvathaneni7-175/+240
This patch adds support for SVE2p1 "tblq" instruction, spec is available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 orqv instruction.Srinath Parvathaneni7-152/+228
This patch adds support for SVE2p1 "orqv" instruction, spec available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08Automatic date update in version.inGDB Administrator1-1/+1
2024-07-07Automatic date update in version.inGDB Administrator1-1/+1
2024-07-06Re: LoongArch: Add DT_RELR supportAlan Modra1-2/+2
Fix commit d89ecf33ab testsuite breakage. * testsuite/lib/binutils-common.exp (supports_dt_relr): Correct.
2024-07-06objcopy bfd_map_over_sections and global statusAlan Modra2-144/+140
This patch started life as a relatively simple change to fix some unimportant objcopy memory leaks, but expanded into a larger patch when I was annoyed by the awkwardness of passing data when using bfd_map_over_sections. A simple loop over sections is much more convenient, and we really don't need the abstraction layer. Sections in a list isn't going to disappear any time soon. The patch also removes use of the global "status" variable by all but the top-level functions called from main. * objcopy.c (filter_symbols): Return success as a bool. Pass symcount as a pointer, updated on return. (merge_gnu_build_notes): Similarly return a bool and add newsize param with updated smaller section size. (setup_bfd_headers): Return bool success rather than setting "status" on failure. (setup_section): Likewise. (copy_relocations_in_section, copy_section): Likewise, and adjust params. (mark_symbols_used_in_relocations): Likewise, and free memory on failure path. Don't call bfd_fatal. (get_sections): Delete function. (copy_object): Don't use bfd_map_over_sections, instead use a loop allowing easy detection of failure status. Free memory on error paths. (copy_archive): Return bool success rather than setting "status" on failure. (copy_file): Set "status" here. * testsuite/binutils-all/strip-13.d: Adjust to suit.
2024-07-06Automatic date update in version.inGDB Administrator1-1/+1
2024-07-05aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)Matthieu Longo3-0/+11
This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
2024-07-05aarch64: add STEP2 feature and its associated registersMatthieu Longo5-0/+13
AArch64 defines new registers for the feature step2 (Enhanced Software Step Extension). step2 is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
2024-07-05aarch64: add SPMU2 feature and its associated registersMatthieu Longo5-0/+13
AArch64 defines new registers for the feature spmu2 (System Performance Monitors Extension version 2). spmu2 is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
2024-07-05aarch64: add E3DSE feature and its associated registersMatthieu Longo6-1/+39
AArch64 defines new registers for the feature e3dse (Delegated SError exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
2024-07-05x86-64: Fix support for APX NF TLS IE with 2 operandsLingling Kong1-3/+2
Added the restriction in assemble for APX TLS IE that the destination can only be a register. gas/ * config/tc-i386.c (md_assemble): Added stricter restrictions for APX TLS IE.
2024-07-05RISC-V: avoid use of match_opcode() in riscv_insn_types[]Jan Beulich1-102/+102
As of 27b33966b18e ("RISC-V: disallow x0 with certain macro-insns") the .match_func field may be NULL for entries used for assembly only, which is the case for the entire table. With .match and .mask both zero the function would only ever succeed anyway. Save almost a hundred base relocations in the final executable by using NULL instead.
2024-07-05aarch64: fix build with old glibcJan Beulich1-3/+3
As was pointed out several times before, old glibc declares index(), resulting in warnings from -Wshadow, in turn failing the build due to -Werror.
2024-07-05LoongArch: Add DT_RELR testsXi Ruoyao19-0/+485
Most tests are ported from AArch64. The relr-addend test is added to make sure the addend (link-time address) is correctly written into the relocated section. Doing so is not strictly needed for RELA, but strictly needed for RELR). Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05LoongArch: Add DT_RELR supportXi Ruoyao3-4/+486
The logic is same as a71d87680110 ("aarch64: Add DT_RELR support"). As LoongArch does not have -z dynamic-undefined-weak, we don't need to consider UNDEFWEAK_NO_DYNAMIC_RELOC. The linker relaxation adds another layer of complexity. When we delete bytes in a section during relaxation, we need to fix up the offset in the to-be-packed relative relocations against this section. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05LoongArch: Make protected function symbols local for -sharedXi Ruoyao5-21/+81
On LoongArch there is no reason to treat STV_PROTECTED STT_FUNC symbols as preemptible. See the comment above LARCH_REF_LOCAL for detailed explanation. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05LoongArch: Fix bad reloc with mixed visibility ifunc symbols in shared librariesXi Ruoyao4-12/+140
With a simple test case: .globl ifunc .globl ifunc_hidden .hidden ifunc_hidden .type ifunc, %gnu_indirect_function .type ifunc_hidden, %gnu_indirect_function .text .align 2 ifunc: ret ifunc_hidden: ret test: bl ifunc bl ifunc_hidden "ld -shared" produces a shared object with one R_LARCH_NONE (instead of R_LARCH_JUMP_SLOT as we expect) to relocate the GOT entry of "ifunc". It's because the indices in .plt and .rela.plt mismatches for STV_DEFAULT STT_IFUNC symbols when another PLT entry exists for a STV_HIDDEN STT_IFUNC symbol, and such a mismatch breaks the logic of loongarch_elf_finish_dynamic_symbol. Fix the issue by reordering .plt so the indices no longer mismatch. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05LoongArch: Reject R_LARCH_32 from becoming a runtime reloc in ELFCLASS64Xi Ruoyao4-2/+36
We were converting R_LARCH_32 to R_LARCH_RELATIVE for ELFCLASS64: $ cat t.s .data x: .4byte x .4byte 0xdeadbeef $ as/as-new t.s -o t.o $ ld/ld-new -shared t.o $ objdump -R a.out: file format elf64-loongarch DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE 00000000000001a8 R_LARCH_RELATIVE *ABS*+0x00000000000001a8 But this is just wrong: at runtime the dynamic linker will run *(uintptr *)&x += load_address, clobbering the next 4 bytes of data ("0xdeadbeef" in the example). If we keep the R_LARCH_32 reloc as-is in ELFCLASS64, it'll be rejected by the Glibc dynamic linker anyway. And it does not make too much sense to modify Glibc to support it. So we can just reject it like x86_64: relocation R_X86_64_32 against `.data' can not be used when making a shared object; recompile with -fPIC or RISC-V: relocation R_RISCV_32 against non-absolute symbol `a local symbol' can not be used in RV64 when making a shared object Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05x86: Correct position of ".s" for CCMPcc in disassemblerCui, Lili4-5/+24
Added new macro %SW to CCMPcc to print ".s" after the mnemonic. Before: ccmpbl {dfv=}.s %edx,%eax After: ccmpbl.s {dfv=} %edx,%eax gas/ChangeLog: * testsuite/gas/i386/x86-64-pseudos-apx.d: Add tests for CCMPcc. * testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Added %SW for CCMPcc swap operands. * i386-dis.c (struct dis386): Added %SW. (putop): Handle %SW.
2024-07-05x86: Add {load}/{store} tests for apx instructions.Cui, Lili3-0/+204
gas/ChangeLog: * testsuite/gas/i386/x86-64.exp: Add {load}/{store} tests for apx instructions. * testsuite/gas/i386/x86-64-pseudos-apx.d: New test. * testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto.
2024-07-05Automatic date update in version.inGDB Administrator1-1/+1
2024-07-04RISC-V: Fix BFD_RELOC_RISCV_PCREL_LO12_S patch issueSun Sunny4-40/+114
In commit dff565fcca8137954d6ad571ef39f6aec5c0429c, the fixups for PCREL_LO12_I and PCREL_LO12_S were mixed, so the "IMM" field were applied to incorrect position, this caused incorrect src registers to be encoded. gas/ * config/tc-riscv.c (md_apply_fix): Fix PCREL_LO12_S issue. * testsuite/gas/riscv/ixup-local.s: Updated for PCREL_LO12_S cases. * testsuite/gas/riscv/fixup-local-relax.d: Likewise. * testsuite/gas/riscv/fixup-local-norelax.d: Likewise. Signed-off-by: Jianwei Sun <sunny.sun@corelabtech.com>
2024-07-04RISC-V: hash with segment id and pcrel_hi address while recording pcrel_hiLifang Xia1-7/+17
When the same address across different segments (sections) needs to be recorded, it will overwrite the slot, leading to a memory leak. To ensure uniqueness, the segment (section) ID needs to be included in the hash key calculation. gas/ * config/tc-riscv.c (riscv_pcrel_hi_fixup): New "const asection *sec". (riscv_pcrel_fixup_hash): make sec->id and e->adrsess as the hash key. (riscv_pcrel_fixup_eq): Check sec->id at first. (riscv_record_pcrel_fixup): New member "sec". (md_apply_fix) <case BFD_RELOC_RISCV_PCREL_HI20>: Likewise. (md_apply_fix) <case BFD_RELOC_RISCV_PCREL_LO12_I>: Likewise.
2024-07-04mve: Fix encoding for vcvt[bt] single-half float conversion instructionsAndre Vieira2-72/+81
The encoding was previously not taking into account that the Quad vector registers were being encoded using their Q-register numbers rather than their D-register equivalent (multiply by 2). gas/ * config/tc-arm.c (do_neon_cvttb_1): Use Q-register vector number rather than their D-register equivalent. gas/testsuite/ * gas/arm/mve-vcvt-3.d: Correct expected values in test.
2024-07-04gas: Validate SFrame RA tracking and fixed RA offsetJens Remus1-5/+9
Verify all architectures participating in SFrame generation do define the mandatory SFrame return address (RA) tracking predicate function sframe_ra_tracking_p. Do so by explicitly not testing for the macro SFRAME_FRE_RA_TRACKING as otherwise required. Verify that architectures not using SFrame RA tracking specify a valid fixed RA offset. gas/ * gen-sframe.c (output_sframe_internal): Validate SFrame RA tracking and fixed RA offset. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Test predicate whether SFrame RA tracking is usedJens Remus1-2/+4
The existence of the macro SFRAME_FRE_RA_TRACKING only ensures the existence of the macro SFRAME_CFA_RA_REG and the predicate function sframe_ra_tracking_p. It does not indicate whether SFrame RA tracking is actually used. Test the return value of the SFrame RA tracking predicate function sframe_ra_tracking_p to determine whether RA tracking is used. This aligns the logic in functions get_fre_num_offsets and output_sframe_row_entry to the one used in all other places. gas/ * gen-sframe.c (get_fre_num_offsets, output_sframe_row_entry): Test predicate to determine whether SFrame RA tracking is used. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Don't skip SFrame FDE if .cfi_register specifies SP registerJens Remus1-3/+6
Neither ".cfi_offset SP, <offset>", ".cfi_register SP, <regno>", nor ".cfi_val_offset SP, <offset>" alter the tracking information to recover the stack pointer (SP). Doing so would need an explicit .cfi_def_cfa, which SFrame tracks. The stack pointer (SP) register contents on entry can be reconstructed from the SFrame CFA tracking information using information from the current and initial SFrame FREs of the SFrame FDE: 1. Compute CFA from the current CFA base register (SP or FP) and CFA offset from the SFrame CFA tracking information from the SFrame FRE for the current instruction address: CFA = <current_base_reg> + <current_cfa_offset> 2. Compute SP from the current CFA and the CFA offset from the SFrame CFA tracking information from the initial SFrame FRE of the FDE: SP = CFA - <initial_cfa_offset> While at it add comments to the processing of .cfi_offset and .cfi_val_offset that the SP can be reconstructed from the CFA tracking information. gas/ * gen-sframe.c (sframe_xlate_do_register): Do not skip SFrame FDE if .cfi_register specifies SP register. (sframe_xlate_do_offset,sframe_xlate_do_val_offset): Add comment that this is likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Don't skip SFrame FDE if .cfi_register specifies RA w/o trackingJens Remus1-1/+1
Do not skip SFrame FDE if .cfi_register specifies RA register without RA tracking being actually used. Without RA tracking the register contents can always be restored from the stack using the fixed RA offset from CFA. gas/ * gen-sframe.c (sframe_xlate_do_register): Do not skip SFrame FDE if .cfi_register specifies RA register without RA tracking being used. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Skip SFrame FDE if .cfi_window_saveJens Remus1-3/+22
CFI opcode DW_CFA_AARCH64_negate_ra_state is multiplexed with DW_CFA_GNU_window_save. Process DW_CFA_AARCH64_negate_ra_state on AArch64. Skip generation of SFrame FDE otherwise with the following warning message: skipping SFrame FDE; .cfi_window_save gas/ * gen-sframe.c: Skip SFrame FDE if .cfi_window_save. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Skip SFrame FDE if FP without RA on stackJens Remus1-2/+19
The SFrame format cannot represent the frame pointer (FP) being saved on the stack without the return address (RA) also being saved on the stack, if RA tracking is used. A SFrame FDE is followed by 1-3 offsets with the following information: Without RA tracking: 1. Offset from base pointer (SP or FP) to locate the CFA 2. Optional: Offset to CFA to restore the frame pointer (FP) With RA tracking: 1. Offset from base pointer (SP or FP) to locate the CFA 2. Optional: Offset to CFA to restore the return address (RA) 3. Optional: Offset to CFA to restore the frame pointer (FP) When RA tracking is used and a FDE is followed by two offsets the SFrame format does not provide any information to distinguish whether the second offset is the RA or FP offset. SFrame assumes the offset to be the RA offset, which may be wrong. Therefore skip generation of SFrame FDE information and print the following warning, if RA tracking is used and the FP is saved on the stack without the RA being saved as well: skipping SFrame FDE; FP without RA on stack gas/ * gen-sframe.c (sframe_do_fde): Skip SFrame FDE if FP without RA on stack, as the SFrame format cannot represent this case. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: User readable warnings if SFrame FDE is not generatedJens Remus5-28/+72
The following generic warning message, which is printed whenever the assembler skips generation of SFrame FDE, is not very helpful for the user: skipping SFrame FDE; CFI insn <name> (0x<hexval>) Whenever possible print meaningful warning messages, when the assembler skips generation of SFrame FDE: - skipping SFrame FDE; non-SP/FP register <regno> in .cfi_def_cfa - skipping SFrame FDE; non-SP/FP register <regno> in .cfi_def_cfa_register - skipping SFrame FDE; .cfi_def_cfa_offset without CFA base register in effect - skipping SFrame FDE; {FP|RA} register <regno> in .cfi_val_offset - skipping SFrame FDE; {SP|FP|RA} register <regno> in in .cfi_register - skipping SFrame FDE; .cfi_remember_state without prior SFrame FRE state - skipping SFrame FDE; non-default RA register <regno> gas/ * gen-sframe.h (SFRAME_FRE_BASE_REG_INVAL): New macro for invalid SFrame FRE CFA base register value of -1. * gen-sframe.c: User readable warnings if SFrame FDE is not generated. gas/testsuite/ * gas/cfi-sframe/common-empty-1.d: Update generic SFrame test case to updated warning message texts. * gas/cfi-sframe/common-empty-2.d: Likewise. * gas/cfi-sframe/common-empty-3.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Refactor SFrame CFI opcode DW_CFA_register processingJens Remus1-11/+26
Refactor SFrame processing of CFI opcode DW_CFA_register into a separate function. This harmonizes the CFI opcode processing. While at it reword the comment on CFI opcodes that are not processed. This is a purely mechanical change. gas/ * gen-sframe.c (sframe_do_cfi_insn, sframe_xlate_do_register): Refactor SFrame CFI opcode DW_CFA_register processing. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Warn if SFrame FDE is skipped due to non-default return columnJens Remus2-3/+8
Print a warning message if SFrame FDE is skipped due to a non-default DWARF return column (i.e. return address (RA) register number). This may be caused by the use of CFI directive .cfi_return_column with a non-default return address (RA) register number in the processed assembler source code. Warning: skipping SFrame FDE due to non-default DWARF return column gas/ * gen-sframe.c: Warn if SFrame FDE is skipped due to non-default DWARF return column. gas/testsuite/ * gas/cfi-sframe/common-empty-3.d: Update test case to expect for new warning message when SFrame FDE is skipped due to a non-default DWARF return column. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Skip SFrame FDE if CFI specifies non-FP/SP base registerJens Remus2-3/+11
Do not generate SFrame FDE if DWARF CFI directives .cfi_def_cfa or .cfi_def_cfa_register specify a CFA base register number other than the architecture-specific stack-pointer (SP) or frame-pointer (FP) register numbers. This also causes the assembler to print a warning message, so that skipping of the SFrame FDE does not occur silently. Update the generic ld SFrame test case to be architecture independent. Do not use CFI directive .cfi_def_cfa, as the specified CFA base register number is not a valid SP/FP register number on all architectures. An invalid SP/FP register number will now cause the assembler to print a warning message and skip SFrame FDE generation. Remove the offending CFI directive, that cannot be coded architecture- independent, as the test case requires SFrame information to be generated. This was reported by the Linaro-TCWG-CI for AArch64. gas/ * gen-sframe.c: Skip SFrame generation if CFI specifies non-FP/SP base register. ld/testsuite/ * ld-sframe/discard.s: Update generic SFrame test case to be architecture independent. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Print DWARF call frame insn name in SFrame warning messageJens Remus3-3/+50
SFrame generation prints the DWARF call frame instruction opcode in hexadecimal. Leverage get_DW_CFA_name to additionally print the DWARF call frame instruction name in human readable form, while also respecting fake CFI types. Use "(unknown)", if the DWARF call frame instruction name is not known. While at it use the terminology "instruction" for these DW_CFA_*, as suggested by Indu. This changes the following assembler SFrame generation warning message as follows: Old: Warning: skipping SFrame FDE due to DWARF CFI op 0x<hexval> New: Warning: skipping SFrame FDE; CFI insn <name> (0x<hexval>) gas/ * gen-sframe.c (sframe_get_cfi_name): New function to get the DWARF call frame instruction name for a DWARF call frame instruction opcode. (sframe_do_cfi_insn): Use sframe_get_cfi_name to print the DWARF call frame instruction name for the DWARF call frame instruction opcode in the warning message. gas/testsuite/ * gas/cfi-sframe/common-empty-1.d: Update expected SFrame warning message text for DWARF call frame insn name. * gas/cfi-sframe/common-empty-2.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04readelf/objdump: Display SFrame fixed RA offset as 'f' in dumpJens Remus11-38/+40
For the SFrame FRE frame-pointer (FP) offset from CFA a 'u' is displayed if it is unavailable. For the SFrame FRE return-address (RA) offset from CFA a 'u' was displayed if the ABI uses a fixed RA offset from CFA. By chance a 'u' was also displayed if the RA offset is unavailable, as the string buffer was not initialized after formatting the FP offset. Note that it could not occur that the FP offset was erroneously displayed as RA offset, as the SFrame format cannot have a FRE with FP offset without RA offset. For the FRE RA offset display 'f' if the ABI uses a fixed RA offset from CFA. Display a 'u' if it is unavailable. libsframe/ * sframe-dump.c: Display SFrame fixed RA offset as 'f' in dump. gas/testsuite/ * gas/cfi-sframe/cfi-sframe-common-4.d: Test for RA displayed either as 'u' (if RA tracking) or as 'f' (fixed RA offset if no RA tracking). * gas/cfi-sframe/cfi-sframe-common-5.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-6.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-7.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-8.d: Likewise. * gas/cfi-sframe/cfi-sframe-x86_64-1.d: Test for RA displayed as 'f' (fixed RA offset), as x86-64 does not use RA tracking. * gas/scfi/x86_64/scfi-cfi-sections-1.d: Likewise. * gas/scfi/x86_64/scfi-dyn-stack-1.d: Likewise. ld/testsuite/ * ld-x86-64/sframe-plt-1.d: Test for RA displayed as 'f' (fixed RA offset), as x86-64 does not use RA tracking. * ld-x86-64/sframe-simple-1.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04readelf/objdump: Dump SFrame CFA fixed FP and RA offsetsJens Remus17-0/+37
The SFrame format allows architectures to specify fixed offsets from the CFA, if any, from which the frame pointer (FP) and/or return address (RA) may be recovered. These offsets are stored in the SFrame header. For instance the SFrame generation in the assembler for x86 AMD64 specifies a fixed offset from the CFA, from which the return address (RA) may be recovered. When dumping the SFrame header, for instance in readelf/objdump with option --sframe, do also dump the specified fixed offsets from the CFA, if any, from which the frame pointer (FP) and return address (RA) may be recovered. Update the common SFrame test case verification patterns to allow for the optional dumping of the CFA fixed FP/RA offsets. Update the x86- specific SFrame and SCFI test case verification patterns to require a CFA fixed RA offset of -8. libsframe/ * sframe-dump.c: Dump CFA fixed FP and RA offsets. gas/testsuite/ * gas/cfi-sframe/cfi-sframe-common-1.d: Test for optional fixed FP and RA offsets. * gas/cfi-sframe/cfi-sframe-common-2.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-3.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-4.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-5.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-6.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-7.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-8.d: Likewise. * gas/cfi-sframe/cfi-sframe-x86_64-1.d: Test for fixed RA offset. * gas/cfi-sframe/common-empty-1.d: Test for optional fixed FP and RA offsets. * gas/cfi-sframe/common-empty-2.d: Likewise. * gas/cfi-sframe/common-empty-3.d: Likewise. * gas/scfi/x86_64/scfi-cfi-sections-1.d: Test for SFrame fixed RA offset. * gas/scfi/x86_64/scfi-dyn-stack-1.d: Likewise. ld/testsuite/ * ld-x86-64/sframe-plt-1.d: Test for SFrame fixed RA offset. * ld-x86-64/sframe-simple-1.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Enhance arch-specific SFrame configuration descriptionsJens Remus4-14/+19
Explicitly mention "SFrame" in the descriptions for the architecture- specific SFrame configuration macros, variables, and functions. Use the term "frame pointer" (FP) instead of "base pointer". This aligns with the terminology used in the SFrame specification. Additionally it helps not to confuse "base-pointer register" with the term "BASE_REG" used in the specification to denote either the SP or FP register. Specify what the SFRAME_CFA_*_REG register numbers are used for: - SP (stack pointer): CFA tracking - FP (frame pointer): CFA and FP tracking - RA (return address): RA tracking Align the descriptions for definitions in the source files to the declarations in the header files. gas/ * config/tc-aarch64.h: Enhance architecture-specific SFrame configuration descriptions. * config/tc-aarch64.c: Likewise. * config/tc-i386.h: Likewise. * config/tc-i386.c: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04x86: Remove unused SFrame CFI RA register variableJens Remus1-1/+0
gas/ * config/tc-i386.c (x86_sframe_cfa_ra_reg): Remove. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04Support APX CFCMOVCui, Lili13-2242/+3670
The CMOVcc instruction proposed by EVEX has four different forms, corresponding to the four possible combinations of EVEX.ND and EVEX.NF values. In the encoder part, when the CFCMOV template supports EVEX_NF, it means that it requires EVEX.NF to be 1. In the decoder part, CFCMOV_Fixup is used to reverse source and destination operands in the 2-operand case. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Set NF bit for cfcmov when the insn template supports EVEX_NF. * testsuite/gas/i386/x86-64-apx-inval.l: Add invalid tests for cfcmov. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add tests for cfcmov and cmov. * testsuite/gas/i386/x86-64-apx-cfcmov-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add cfcmov instructions. * i386-dis.c (CFCMOV_Fixup): Special handling of cfcmov. (putop): Print 'cf' for cfcmov instructions. * i386-opc.h (EVEX_NF): New. * i386-opc.tbl: Add cfcmov instructions. * i386-mnem.h: Regerated. * i386-tbl.h: Regerated.
2024-07-04Automatic date update in version.inGDB Administrator1-1/+1
generated by cgit v1.1 at 2025-09-27 05:53:17 +0000