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2024-03-09Reinstate bfd_print_error as an extern functionAlan Modra2-4/+32
* bfd.c (_bfd_print): Renamed from bfd_print_error. (bfd_print_error): Reinstate previous code but using the above. (error_handler_fprintf, error_handler_sprintf): Adjust. * bfd-in2.h: Regenerate.
2024-03-09Re: Move bfd_init to bfd.cAlan Modra1-1/+0
Commit b1c95bc4dd73 cleared some bfd static variables, with bad results since bfd_set_error_program_name is often called before bfd_init. * bfd.c (bfd_init): Don't clear _bfd_error_program_name.
2024-03-09print cached error messages using _bfd_error_handlerAlan Modra3-31/+3
* bfd.c (bfd_print_error): Make static. Don't print program name. (error_handler_fprintf): Print program name here. * format.c (print_warnmsg): Use _bfd_error_handler to print cached messages. * bfd-in2.h: Regenerate.
2024-03-08Avoid race when writing to index cacheTom Tromey3-20/+26
The background DWARF reader changes introduced a race when writing to the index cache. The problem here is that constructing the index_cache_store_context object should only happen on the main thread, to ensure that the various value captures do not race. This patch adds an assert to the construct to that effect, and then arranges for this object to be constructed by the cooked_index_worker constructor -- which is only invoked on the main thread. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31262
2024-03-08Move the 'store' method to index_cache_store_contextTom Tromey3-14/+12
I think it is cleaner for 'store' to be a method on index_cache_store_context rather than on the global index cache itself. This patch makes this change.
2024-03-08Capture the per-BFD object in index_cache_store_contextTom Tromey4-14/+14
This changes index_cache_store_context to also capture the per-BFD object when it is constructed. This is used when storing to the cache, and this approach makes the code a little simpler.
2024-03-08Capture directory in index_cache_store_contextTom Tromey2-4/+8
I noticed that index_cache_store_context captures the 'enabled' setting, but not the index cache directory. This patch makes this change, which avoids a possible race -- with background reading, the user could possibly change this directory at the exact moment the writer examines the variable.
2024-03-08Rename members of index_cache_store_contextTom Tromey2-7/+7
This renames the private members of index_cache_store_context to start with "m_".
2024-03-09Automatic date update in version.inGDB Administrator1-1/+1
2024-03-08Add return value to DAP scopeTom Tromey4-2/+158
A bug report in the DAP specification repository pointed out that it is typical for DAP implementations to put a function's return value into the outermost scope. This patch changes gdb to follow this convention. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31341 Reviewed-By: Kévin Le Gouguec <legouguec@adacore.com>
2024-03-08Export "finish" return value to PythonTom Tromey4-18/+47
This patch changes the Python "stop" event emission code to also add the function return value, if it is known. This happens when the stop comes from a "finish" command and when the value can be fetched. The test is in the next patch. Reviewed-By: Eli Zaretskii <eliz@gnu.org>
2024-03-08gas: Fix x86 build with GCC 6.4H.J. Lu1-1/+1
Add "()" to silence GCC 6.4: .../gas/config/tc-i386.c: In function ‘x86_ginsn_lea’: .../gas/config/tc-i386.c:5738:19: error: logical not is only applied to the left hand side of comparison [-Werror=logical-not-parentheses] if (!i.base_reg != (!i.index_reg || i.index_reg->reg_num == RegIZ)) ^~ cc1: all warnings being treated as errors PR gas/31464 * config/tc-i386.c (x86_ginsn_lea): Add "()" to silence GCC 6.4.
2024-03-08Avoid race when reading dwz fileTom Tromey2-20/+24
PR gdb/31260 points out a race introduced by the background reading changes. If a given objfile is re-opened when it is already being read, dwarf2_initialize_objfile will call dwarf2_read_dwz_file again, causing the 'dwz_file' to be reset. This patch fixes the problem by arranging to open the dwz just once: when the dwarf2_per_bfd object is created. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31260
2024-03-08bfd: Change the --with-mmap default to trueH.J. Lu2-2/+2
Change the configure default to using mmap. * configure.ac: Change the --with-mmap default to true. * configure: Regenerated.
2024-03-08bfd: Don't hard-code BFD_JUMP_TABLE_COPYH.J. Lu14-4/+20
In BFD_JUMP_TABLE_COPY, replace _bfd_generic_init_private_section_data with NAME##_init_private_section_data so that ELF targets can properly replace it with _bfd_elf_init_private_section_data. * aout-target.h (MY_init_private_section_data): New. * coff-rs6000.c (_bfd_xcoff_init_private_section_data): New. * coffcode.h (coff_init_private_section_data): New. * elfxx-target.h (bfd_elfNN_init_private_section_data): New. * libecoff.h (_bfd_ecoff_init_private_section_data): New. * mach-o-target.c (bfd_mach_o_init_private_section_data): New. * mmo.c (mmo_init_private_section_data): New. * plugin.c (bfd_plugin_init_private_section_data): New. * ppcboot.c (ppcboot_init_private_section_data): New. * som.c (som_init_private_section_data): New. * targets.c (BFD_JUMP_TABLE_COPY): Replace _bfd_generic_init_private_section_data with NAME##_init_private_section_data. * vms-alpha.c (vms_init_private_section_data): New. * elf-bfd.h (_bfd_generic_init_private_section_data): Removed. * bfd-in2.h: Regenerated.
2024-03-08RISC-V: Support Zabha extension.Jiawei7-0/+370
The Zabha extension[1] supports for byte and halfword atomic memory operations. This patch add all instructions include in Zabha. Further work is waiting Zacas[2] merge. [1] https://github.com/riscv/riscv-zabha/tags [2] https://sourceware.org/pipermail/binutils/2023-May/127700.html Version log: Add new imply relation that Zabha extension implies A extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): New imply. (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * testsuite/gas/riscv/zabha-32.d: New test. * testsuite/gas/riscv/zabha.d: New test. * testsuite/gas/riscv/zabha.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes. (MASK_AMOADD_B): Ditto. (MATCH_AMOXOR_B): Ditto. (MASK_AMOXOR_B): Ditto. (MATCH_AMOOR_B): Ditto. (MASK_AMOOR_B): Ditto. (MATCH_AMOAND_B): Ditto. (MASK_AMOAND_B): Ditto. (MATCH_AMOMIN_B): Ditto. (MASK_AMOMIN_B): Ditto. (MATCH_AMOMAX_B): Ditto. (MASK_AMOMAX_B): Ditto. (MATCH_AMOMINU_B): Ditto. (MASK_AMOMINU_B): Ditto. (MATCH_AMOMAXU_B): Ditto. (MASK_AMOMAXU_B): Ditto. (MATCH_AMOSWAP_B): Ditto. (MASK_AMOSWAP_B): Ditto. (MATCH_AMOADD_H): Ditto. (MASK_AMOADD_H): Ditto. (MATCH_AMOXOR_H): Ditto. (MASK_AMOXOR_H): Ditto. (MATCH_AMOOR_H): Ditto. (MASK_AMOOR_H): Ditto. (MATCH_AMOAND_H): Ditto. (MASK_AMOAND_H): Ditto. (MATCH_AMOMIN_H): Ditto. (MASK_AMOMIN_H): Ditto. (MATCH_AMOMAX_H): Ditto. (MASK_AMOMAX_H): Ditto. (MATCH_AMOMINU_H): Ditto. (MASK_AMOMINU_H): Ditto. (MATCH_AMOMAXU_H): Ditto. (MASK_AMOMAXU_H): Ditto. (MATCH_AMOSWAP_H): Ditto. (MASK_AMOSWAP_H): Ditto. (DECLARE_INSN): New declare. * opcode/riscv.h (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-opc.c: New instructions.
2024-03-08Automatic date update in version.inGDB Administrator1-1/+1
2024-03-07Automatic date update in version.inGDB Administrator1-1/+1
2024-03-06Add "-j1" to make command lines in the create-a-release README.Nick Clifton1-3/+3
2024-03-06LoongArch: Fix some test cases for TLS transition and relaxLulu Cai37-168/+333
2024-03-06LoongArch: Add dtpoff calculation functionLulu Cai1-1/+11
When tls_sec is NULL, we should not access the virtual address of tls_sec.
2024-03-06LoongArch: Delete extra instructions when TLS type transitionLulu Cai2-172/+279
This modification mainly changes the timing of type transition, adds relaxation to the old LE instruction sequence, and fixes bugs in extreme code models. We strictly distinguish between type transition and relaxation. Type transition is from one type to another, while relaxation is the removal of instructions under the same TLS type. Detailed instructions are as follows: 1. For type transition, only the normal code model of DESC/IE does type transition, and each relocation is accompanied by a RELAX relocation. Neither abs nor extreme will do type transition, and no RELAX relocation will be generated. The extra instructions when DESC transitions to other TLS types will be deleted during the type transition. 2. Implemented relaxation for the old LE instruction sequence. The first two instructions of LE's 32-bit and 64-bit models use the same relocations and cannot be distinguished based on relocations. Therefore, for LE's instruction sequence, any code model will try to relax. 3. Some function names have been adjusted to facilitate understanding, parameters have been adjusted, and unused macros have been deleted.
2024-03-06Don't use bfd_error_handler in bfd_abortAlan Modra1-9/+9
We don't want to lose an abort message when bfd_set_error_handler has been called to ignore or cache errors. PR ld/31444 * bfd.c (_bfd_abort): Don't use _bfd_error_handler.
2024-03-06Automatic date update in version.inGDB Administrator1-1/+1
2024-03-05gdb/testsuite: fix duplicate test names in gdb.trace/circ.expAndrew Burgess1-31/+45
This fixes some duplicate test names in gdb.trace/circ.exp when using native-gdbserver and native-extended-gdbserver boards. In this test we set the trace buffer size twice. The same test name was used each time the size was adjusted. I've fixed this issue by: 1. Creating a new proc, set_trace_buffer_size, which factors out the code to change the buffer size, and uses test names based on the size we're setting the buffer too, 2. Calling the new proc each time we want to adjust the buffer size. After this the duplicate test names are resolved. There should be no change in what is tested after this commit.
2024-03-05gdb/testsuite: fix some more duplicate test names in gdb.trace/Andrew Burgess2-55/+46
This commit fixes some duplicate test names in the gdb.trace/ directory when run with the native-gdbserver and native-extended-gdbserver boards. In this case the duplicates relate to the calls to gdb_compile_pthreads which emits a fixed PASS message, as there are two calls to gdb_compile_pthreads we get a duplicate PASS message. In both cases the problem is fixed by adding a with_test_prefix around one of the compilations, however, I've made additional changes to clean up the tests a little while I was working on them: 1. Switch to use prepare_for_testing instead of gdb_compile_pthreads. By passing the 'pthreads' option this does call gdb_compile_pthreads under the hood, but using the standard compile function is cleaner, 2. Using prepare_for_testing removes the need to call clean_restart immediately afterwards, so those calls are removed, 3. I removed the unneeded $executable and $expfile globals, where the $executable global was used I've replaced this with $binfile, 4. When we compile two executables I've now given these different names so that both exist at the end of the test run, 5. Removed a gdb_reinitialize_dir call, this is covered by clean_restart, 6. Use gdb_test_no_output where it makes sense. I now see no duplicate test names when running these test scripts. There should be no change in what is being tested after this commit.
2024-03-05LoongArch: Add gas testsuit for LA32 relocationsLulu Cai2-0/+136
Test the relocation of the LA32 instruction set.
2024-03-05LoongArch: Add gas testsuit for LA64 relocationsLulu Cai2-0/+253
Test the relocation of the LA64 instruction set.
2024-03-05LoongArch: Add gas testsuit for LA32 int/float instructionsLulu Cai4-0/+609
Test the int/float instructions of LA32.
2024-03-05LoongArch: Add gas testsuit for LA64 int/float instructionsLulu Cai4-0/+1192
Test the int/float instructions of LA64.
2024-03-05LoongArch: Add gas testsuit for lsx/lasx instructionsLulu Cai4-0/+2938
Test the LSX/LASX instructions. Only LA64 supports these instructions.
2024-03-05LoongArch: Add gas testsuit for lbt/lvz instructionsLulu Cai4-0/+382
Test the LBT/LVZ instructions. Only LA64 supports these instructions.
2024-03-05LoongArch: Add gas testsuit for alias instructionsLulu Cai4-0/+60
Test the alias instructions.
2024-03-05Automatic date update in version.inGDB Administrator1-1/+1
2024-03-04Automatic date update in version.inGDB Administrator1-1/+1
2024-03-03Automatic date update in version.inGDB Administrator1-1/+1
2024-03-02gdb: LoongArch: Change LOONGARCH_FIRST_FP_REGNUM to 35Hui Li1-1/+2
There is an assertion error "gdb_assert (n < tdesc->reg_defs.size ())" in find_register_by_number() when gdb connects to gdbserver, this is because the value of LOONGARCH_LINUX_NUM_GREGSET (45, which contains 10 reserved regs) is different with the number of regs (35, which not contains 10 reserved regs) in file gdb/features/loongarch/base64.xml. Add a new macro LOONGARCH_USED_NUM_GREGSET which is defined as 35 to keep consistent with the gdb/features/loongarch/base64.xml, and then define LOONGARCH_FIRST_FP_REGNUM as LOONGARCH_USED_NUM_GREGSET so that all the reg numbers in regcache are consistent with tdesc reg numbers. without this patch: Execute on the target machine: $ gdbserver 192.168.1.123:5678 ./test Execute on the host machine: $ gdb ./test (gdb) target remote 192.168.1.123:5678 Output on the target machine: Process ./test created; pid = 67683 Listening on port 5678 Remote debugging from host 192.168.1.136, port 6789 gdbserver/regcache.cc:205: A problem internal to GDBserver has been detected. find_register_by_number: Assertion 'n < tdesc->reg_defs.size ()' failed. Output on the host machine: Remote debugging using 192.168.1.123:5678 Remote connection closed Signed-off-by: Hui Li <lihui@loongson.cn> Approved-By: John Baldwin <jhb@FreeBSD.org> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
2024-03-01Fix TUI text centeringTom Tromey5-37/+26
In a couple of spots, the TUI tries to center some text in the window. Andrew noticed that the calculation is done strangely and the text ends up somewhat to the left of center. This patch fixes the problem. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31355
2024-03-02Automatic date update in version.inGDB Administrator1-1/+1
2024-03-01gdb/jit: Fix missing word in commentWill Hawkins1-2/+2
ChangeLog: * gdb/jit.c: Fix missing word in code comment. Signed-off-by: Will Hawkins <hawkinsw@obs.cr>
2024-03-01s390: Be more verbose about missing operand typeJens Remus3-18/+54
Provide expected operand type in s390-specific assembler operand parsing error message: "error: operand <operand-number>: missing <operand-type> operand" With <operand-type> being one of: - base register - displacement - [vector] index register - length - access register - control register - floating-point register - general-purpose register - vector register - [un]signed number gas/ * config/tc-s390.c: Provide missing operand type in error message. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case result validation patterns to operand number in operand syntax error messages. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Provide operand number in assembler warning and error messagesJens Remus6-165/+206
Prepend the operand number "operand %d:" to the s390-specific assembler operand parsing warning and error messages. While at it reword the custom operand out of range error message text to be closer to the one used by as_bad_value_out_of_range(). Additionally reword the invalid FPR pair warning message to make it nicer. gas/ * config/tc-s390.c: Print operand number in error messages. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case verification patterns to accept syntax error messages now containing the operand number. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. * testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise. * testsuite/gas/s390/zarch-z9-109-err.l: Likewise. * testsuite/gas/s390/zarch-z900-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Allow to explicitly omit base register operand in assemblyJens Remus10-165/+120
The base register operand B may be omitted in D(B) by coding D and in D(L,B) by coding D(L). The index register operand X may be omitted in D(X,B) by coding D(B) or explicitly omitted by coding D(,B). In both cases the omitted base register operand value defaults to zero. Allow to explicitly omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). Default the omitted base register operand value to zero. gas/ * config/tc-s390.c: Allow to explicitly omit the base register operand in assembly. * NEWS: Mention that the base register now may be omitted on s390. * gas/testsuite/gas/s390/zarch-base-index-0.s: Update test cases for change to allow to explicitly omit the base register operand in assembly. * gas/testsuite/gas/s390/zarch-base-index-0.d: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.s: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Print base register 0 as "0" in disassemblyJens Remus4-39/+50
Base and index register 0 have no effect in address computation: "A value of zero in the B [base] or X [index] field specifies that no base or index is to be applied, and, thus, general register 0 cannot be designated as containing a base address or index." IBM z/Architecture Principles of Operation [1], chapter "Organization", section "General Registers". Index register 0 is omitted in the s390 disassembly. Base register 0 is omitted in D(B), D(L,B) and D(X,B) - the latter only if the index register is zero. To make it more apparent print base register 0 as "0" instead of "%r0", whenever it would still be printed in the disassembly. [1]: IBM z/Architecture Principles of Operation, SA22-7832-13, https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf opcodes/ * s390-dis.c: Print base register 0 as "0" in disassembly. binutils/ * NEWS: Mention base register 0 now being printed as "0" in s390 disassembly. gas/ * testsuite/gas/s390/zarch-base-index-0.d: Update test case output verification patterns to accept "0" as base base register due to disassembler output format change. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Warn when register name type does not match operandJens Remus14-53/+238
Print a warning message when the register type of a specified register name does not match with the operand's register type: operand {#}: expected {access|control|floating-point|general|vector} register name [as {base|index} register] Introduce a s390-specific assembler option "warn-regtype-mismatch" with the values "strict", "relaxed", and "no" as well as an option "no-warn-regtype-mismatch" which control whether the assembler performs register name type checks and generates above warning messages. warn-regtype-mismatch=strict: Perform strict register name type checks. warn-regtype-mismatch=relaxed: Perform relaxed register name type checks, which allow floating-point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating-point register (FPR) operands. This is acceptable as the FPRs are embedded into the lower halves of the VRs. Make "relaxed" the default, as GCC generates assembler code using FPR and VR interchangeably, which would cause assembler warnings to be generated with "strict". warn-regtype-mismatch=no: no-warn-regtype-mismatch: Disable any register name type checks. Tag .insn pseudo mnemonics as such, to skip register name type checks on those. They need to be skipped, as there do not exist .insn pseudo mnemonics for every possible operand register type combination. Keep track of the currently parsed operand number to provide it as reference in warning messages. To verify that the introduction of this change does not unnecessarily affect the compilation of existing code the GNU Binutils, GNU C Library, and Linux Kernel have been build with the new assembler, verifying that the assembler did not generate any of the new warning messages. gas/ * config/tc-s390.c: Handle new assembler options "[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate parsed register expressions with register type. Keep track of operand number being parsed. Print warning message in case of register type mismatch between instruction operand and parsed register expression. * doc/as.texi: Document new s390-specific assembler options "[no-]warn-regtype-mismatch[=strict|relaxed|no]". * NEWS: Mention new s390-specific register name type checks and related assembler option "warn-regtype-mismatch=strict| relaxed|no". * testsuite/gas/s390/s390.exp: Add test cases for new assembler option "warn-regtype-mismatch={strict|relaxed}". * testsuite/gas/s390/esa-g5.s: Fix register types in tests for didbr, diebr, tbdr, and tbedr. * testsuite/gas/s390/zarch-z13.s: Fix register types in tests for vgef, vgeg, vscef, and vsceg. * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s: Tests for assembler option "warn-regtype-mismatch=strict". * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l: Likewise. * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s: Tests for assembler option "warn-regtype-mismatch=relaxed". * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update test cases for assembler option "warn-regtype-mismatch" defaulting to "relaxed". * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. include/ * opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add instruction flag to tag .insn pseudo-mnemonics. opcodes/ * s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as such. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Revise s390-specific assembler option descriptionsJens Remus1-10/+18
Reorder, reword, and complete the s390-specific option descriptions. Align the formatting of s390-specific assembler options to that of the general assembler options in "as --help". While at it change a warning message to use the term "z/Architecture" instead of the deprecated "esame" (ESA Modal Extensions or ESAME) one. gas/ * config/tc-s390.c: Revise s390-specific assembler option descriptions. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add test case for disassembler option warn-areg-zeroJens Remus3-0/+182
gas/ * testsuite/gas/s390/s390.exp: Add test cases for s390-specific assembler option "warn-areg-zero". * testsuite/gas/s390/zarch-warn-areg-zero.s: Likewise. * testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add test cases for base/index register 0Jens Remus6-2/+397
While at it add comments to logic to omit base and/or index register 0 in s390 disassembly. opcodes/ * s390-dis.c: Add comments related to omitting base and/or index register 0 in disassembly. gas/ * testsuite/gas/s390/s390.exp: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.s: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.d: Likewise. * testsuite/gas/s390/zarch-base-index-0-err.s: Add error test cases for base and/or index register 0. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add comments to assembler operand parsing logicJens Remus1-6/+25
gas/ * config/tc-s390.c: Add comments to assembler operand parsing logic. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Assemble processor specific test cases for their processorJens Remus1-2/+2
Assemble the esa-g5 test case with -march=g5. Assemble the zarch-z900 test case with -march=z900. gas/ * testsuite/gas/s390/s390.exp: Assemble processor specific test cases for their respective processor (-march=<processor>). Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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