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2021-10-28RISC-V/SiFive: Added SiFive custom cache control instructions.users/riscv/binutils-integration-branchNelson Chu12-5/+113
According to the chapter 10 of the following U74-MC manual, https://sifive.cdn.prismic.io/sifive/6d9a2510-2632-44f3-adb9-d0430f139372_sifive_coreip_U74MC_AXI4_rtl_v19_08p2p0_release_manual.pdf and the implementations of freedom-metal, https://github.com/sifive/freedom-metal/blob/v201908-branch/src/cache.c * Encodings, 31-25 24-20 19-15 14-12 11-7 6-0 FUNCT7 RS2 RS1 FUNCT3 RD OPCODE 1111110 00000 xxxxx 000 00000 1110011 CFLUSH.D.L1 1111110 00010 xxxxx 000 00000 1110011 CDISCARD.D.L1 1111110 00001 00000 000 00000 1110011 CFLUSH.I.L1 * Extension names, xsfcflushdlone: CFLUSH.D.L1. xsfcdiscarddlone: CDISCARD.D.L1. xsfcflushilone: CFLUSH.I.L1. * Vendor target triples, For assembler, the target vendor is defined as TARGET_VENDOR in the gas/config.h, but I don't see any related settings in bfd/config.h and opcode/config. Since we may have vendor relocations in the future, and these relocation numbers may repeat, I add a new RISCV_TARGET_VENDOR in the bfd/config.h for riscv. The vendor name will be stored in the bfd/cpu-riscv.c, so that all tools (gas, bfd, opcode, ...) can get the vendor name from the configure setting. If the --with-arch configure option, -march gas option and elf architecture attributes are not set, then we will generate the default ISA string according to the chosen target vendor. For example, if you build the binutils with the configure option, --target=riscv64-sifive-elf, then the assembler will find the whole supported extension tables in the bfd/elfxx-riscv.c, and generate the suitable ISA string. bfd/ * configure.ac (RISCV_TARGET_VENDOR): Defined to store target_vendor, only when the target is riscv*. * config.in: Regenerated. * configure: Regenerated. * cpu-riscv.c (riscv_vendor_name): Defined to RISCV_TARGET_VENDOR. * cpu-riscv.h (enum riscv_spec_class): Added VENDOR_SPEC_CLASS_SIFIVE. * elfxx-riscv. (EXT_SIFIVE): Defined to choose the default extensions for sifive. (riscv_supported_vendor_sifive_ext): Added extensions for sifive cache control instructions. (riscv_supported_std_ext, riscv_all_supported_ext): Updated. (riscv_get_default_ext_version): Updated. (riscv_set_default_arch): Updated. gas/ * config/tc-riscv.c (VENDOR_SIFIVE_EXT): Added. (riscv_extended_subset_supports): Handle INSN_CLASS_XSF*. (op_vendor_sifive_hash): Added to store sifive opcodes. (md_begin): Init the op_vendor_sifive_hash. (riscv_find_extended_opcode_hash): Find the opcodes from op_vendor_sifive_hash. * testsuite/gas/riscv/extended/sifive-insns.d: New testcase. * testsuite/gas/riscv/extended/sifive-insns.s: Likewise. include/ * opcode/riscv-opc-extended.h: Added opcodes for sifive cache instructions. * opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS_XSF*. opcodes/ * riscv-opc.c (riscv_vendor_sifive_opcodes): Added. (riscv_extended_opcodes): Updated.
2021-10-28RISC-V/rvv: Added zve* and zvl* extensions, and clarify the imply rules.Nelson Chu28-81/+777
* Recognized zve* and zvl* extensions. - zve*: zve64d, zve64f, zve64x, zve32f and zve32x. - zvl*: zvl32b, zvl64b, zvl128b, zvl256b, zvl512b, zvl1024b, zvl2048b, zvl4096b, zvl8192b, zvl16384b, zvl32768b and zvl65536b. * Spec said that v requires f and d, zve64d requires d, zve64f and zve32f require f. However, according to the issue 723, [https://github.com/riscv/riscv-v-spec/issues/723] The general rule is that extension names imply the things they require. Therefore, the current imply rules should be as follows, - v imply f and d. - zve64d imply d. - zve64f and zve32f imply f. - zvamo imply a. Besides, consider the implicit zve and zvl extensions, - v imply zve64d and zvl128b. - zve64* imply the corresponding zve32*. For example, zve64f imply zve32f, and zve64x imply zve32x. - zve*d imply zve*f and zve*x. For example, zve64d imply zve64f and zve64x. - zve*f imply zve*x. For example, zve64f imply zve64x. - zve64* imply zvl64b, and zve32* imply zvl32b. - The larger zvl* imply all smaller zvl*. For example, zvl128b imply zvl64b, and zvl32b. Therefore, "-march=rv64iv -misa-spec=20191213" will be "rv64i2p0_f2p0_d2p0_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0". Note: zicsr is the imply extension of f. * For zve32x, the (segmant) load/store instructions are illegal when EEW is 64. Besides, vsew cannot be set to 64 by vsetvli when zve32* is enabled. * For zvl*b extensions, we also need to enable either v or zve* extensions. Otherwise we should issue errors. bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules for v, zve* and zvl*b extensions. (riscv_supported_std_z_ext): Added zve* and zvl*b extensions. (riscv_parse_check_conflicts): The zvl*b extensions cannot be set without v and zve* extensions. gas/ * config/tc-riscv.c (riscv_extended_subset_supports): Handle zve*. (my_getVsetvliExpression): vsew cannot be set to 64 by vsetvli when zve32* is enabled. (riscv_ip): The (segmant) loads and stores with EEW 64 cannot be used when zve32x is enabled. * testsuite/gas/riscv/extended/march-imply-v.d: New testcase. * testsuite/gas/riscv/extended/march-imply-zve*.d: Likewise. * testsuite/gas/riscv/extended/march-imply-zvl*b.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvl.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvl.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Removed a-ext from -march since it will be added as implicit ext for zvamo. * testsuite/gas/riscv/extended/vector-insns.d: Likewise. include/ * opcode/riscv.h: Defined INSN_V_EEW64. opcodes/ * riscv-opc.c (riscv_draft_opcodes): Added INSN_V_EEW64 for vector loads and stores when the eew encodings are 64.
2021-10-28RISC-V/rvv: Separate zvamo from v, and removed the zvlsseg extension name.Nelson Chu6-325/+317
* Separate zvamo from v extension with v1.0, but keep the implementations. * Removed zvlsseg extension name as the vector segmant loads and stores are required (included) in v extension. * Updated the versions of v and zvamo from draft v0.10 to frozen v1.0. bfd/ * elfxx-riscv.c (riscv_supported_std_z_ext): Removed entry of zvlsseg. gas/ * config/tc-riscv.c (riscv_extended_subset_supports): Changed INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO, and removed INSN_CLASS_V_OR_ZVLSSEG. (riscv_extended_csr_class_check): Updated since the name zvlsseg is removed. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Changed -march from rv32iav to rv32ia_zvamo. * testsuite/gas/riscv/extended/vector-insns.d: Changed -march from rv32iafv to rv32iafv_zvamo. include/ * opcode/riscv.h (riscv_extended_insn_class): Changed INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO, and removed INSN_CLASS_V_OR_ZVLSSEG. opcodes/ * riscv-opc.c (riscv_draft_opcodes): Changed INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO since they are separated from v. Also changed INSN_CLASS_V_OR_ZVLSSEG to INSN_CLASS_V as they are included in v.
2021-10-28RISC-V/rvv: Update constraints for widening and narrowing instructions.Nelson Chu6-562/+139
* Since fractional LMUL is supported, we cannot just assume LMUL is 1. Otherwise, the old conflit checking rules may cause problems. * Removed the overlap constraints for narrowing instructions. gas/ * testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.d: Removed. * testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.l: Updated. * testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.s: Likewise. opcodes/ * riscv-opc.c (match_vd_neq_vs1_neq_vm): Added for vw*.wv instructions. (match_widen_vd_neq_vs1_neq_vs2_neq_vm): Replaced by match_vd_neq_vs1_neq_vs2_neq_vm. (match_widen_vd_neq_vs1_neq_vm): Replaced by match_vd_neq_vs1_neq_vm. (match_widen_vd_neq_vs2_neq_vm): Replaced by match_vd_neq_vs2_neq_vm. (match_widen_vd_neq_vm): Replaced by match_vd_neq_vm. (match_narrow_vd_neq_vs2_neq_vm): Same as match_widen_vd_neq_vs2_neq_vm.
2021-10-28RISC-V/rvv: Added assembly pseudo and changed assembler mnemonics.Nelson Chu7-49/+85
* Added pseudo instruction, - vfabs.v vd,vs = vfsgnjx.vv vd,vs,vs * Changed assembler mnemonics, and the older names kept as aliases, - Changed from vle1.v to vlm.v, and vse1.v to vsm.v. - Changed from vfredsum and vfwredsum to vfredusum and vfwredusum respectively. - Changed from vpopc.m to vcpop.m, to be consistent with scalar instruction. - Changed from vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm. gas/ * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l: Updated. * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/extended/vector-insns.d: Likewise. * testsuite/gas/riscv/extended/vector-insns.s: Likewise. include/ * opcode/riscv-opc-extended.h: Updated. opcodes/ * riscv-opc.c: Added pseudo vfabs.v, and changed assembler mnemonics.
2021-10-28RISC-V/t-head: Add CSRs and opcodes of the T-HEAD XUANTIE CPUsLifang Xia13-0/+1512
Add CSRs and opcodes of the XUANTIE CPUs, extensions named "theadc", "xtheade" and "xtheadse". New ARG format for operands: "Xgm@n": encode GPR with m bit at opcode[m+n-1:n]. "Xg5@0": encode GPR with 5 bit at opcode[4:0]. "Xg5@8": encode GPR with 5 bit at opcode[12:8]. "XIm@n": m bits unsigned immediate at opcode[m+n-1:n]. "XI5@0": 5 bits unsigned immediate at opcode[4:0]. "XI4@8": 4 bits unsigned immediate at opcode[11:8]. "XSm@n": m bits signed immediate at opcode[m+n-1:n]. "XS5@0": 5 bits signed immediate at opcode[4:0]. "XS4@8": 4 bits signed immediate at opcode[11:8]. "XFm@n": m bits FR at opcode[m+n-1:n]. "XF5@0": 5 bits FR at opcode[4:0]. "XF5@0": 5 bits FR at opcode[4:0]. bfd/ * cpu-riscv.h (enum riscv_spec_class) <VENDOR_SPEC_CLASS_THEAD>: New. * elfxx-riscv.c (riscv_supported_vendor_thead_ext): New. (riscv_all_supported_ext): Updated. (riscv_get_default_ext_version): Updated. gas/ * config/tc-riscv.c (VENDOR_THEAD_EXT): New. (enum riscv_extended_csr_class) <CSR_CLASS_VENDOR_THEAD>: New. (riscv_extended_subset_supports): Check subset: INSN_CLASS_THEAD* (op_vendor_thead_hash): New, the hash of T-HEAD Xuantie's opcodes. (riscv_csr_address): Skip check version for T-HEAD Xuantie CPUs. (validate_riscv_extended_insn): Parsing T-HEAD opargs. (md_begin): Init op_vendor_thead_hash. (riscv_find_extended_opcode_hash): Search op_vendor_thead_hash. (riscv_parse_extended_operands): Parsing T-HEAD opargs. * testsuite/gas/riscv/extended/thead*: New testcases. include/ * opcode/riscv-opc-extended.h: Add CSRs and opcode of the T-HEAD XUANTIE CPUs. * opcode/riscv.h (riscv_extended_insn_class) <INSN_CLASS_THEADC>: New. <INSN_CLASS_THEADC_OR_THEADE>: New. <INSN_CLASS_THEADC_OR_THEADE_OR_THEADSE>: New. <INSN_CLASS_THEADE>: New. <INSN_CLASS_THEADSE>: New. (*VENDOR_THEAD_*): T-HEAD IMM encoding. opcodes/ * riscv-dis.c (print_extended_insn_args): Parsing T-HEAD opargs. * riscv-opc.c (match_thead_rd1_rd2_neq_rs1): New. (riscv_vendor_thead_opcodes): New. (riscv_extended_opcodes): Add riscv_vendor_thead_opcodes.
2021-10-28RISC-V/extended: Improve the gas/testsuite/gas/riscv/extended/extended.exp.Nelson Chu1-18/+1
gas/ * testsuite/gas/riscv/extended/extended.exp: Updated.
2021-10-28RISC-V: Support svinval extensions.Nelson Chu8-0/+50
https://github.com/riscv/riscv-isa-manual/pull/668/files There are five new instructions for svinval extension. According to the above draft spec, two of them (HINVAL.VVMA and HINVAL.GVMA) need to enable the hypervisor extension. But there is no implementation of hypervisor extension in mainline, so let's consider the related issues later. 31..25 24..20 19..15 14..12 11...7 6..2 1..0 sinval.vma 0001011 rs2 rs1 000 00000 11100 11 sfence.w.inval 0001100 00000 00000 000 00000 11100 11 sfence.inval.ir 0001100 00001 00000 000 00000 11100 11 hinval.vvma 0011011 rs2 rs1 000 00000 11100 11 hinval.gvma 0111011 rs2 rs1 000 00000 11100 11 bfd/ * elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval. gas/ * config/tc-riscv.c (riscv_extended_subset_supports): Handle INSN_CLASS_SVINVAL. * testsuite/gas/riscv/extended/extended.exp: Updated. * testsuite/gas/riscv/extended/svinval.d: Mew testcases. * testsuite/gas/riscv/extended/svinval.s: Likewise. include/ * opcode/riscv-opc-extended.h: Added encodings for svinval. * opcode/riscv.h (riscv_extended_insn_class): Added INSN_CLASS_SVINVAL. opcodes/ * riscv-opc.c (riscv_draft_opcodes): Added svinval instructions.
2021-10-28RISC-V/zfh: Added big endian testcase for .float16 directive.Nelson Chu4-5/+16
gas/ * testsuite/gas/riscv/extended/extended.exp: Updated. * testsuite/gas/riscv/extended/float16.s: Minor fix for sNaNh. * testsuite/gas/riscv/extended/float16-le.d: Updated and renamed from float16.d. * testsuite/gas/riscv/extended/float16-be.d: New testcase.
2021-10-28RISC-V/zfh: Support .float16 directive for assembler.Nelson Chu4-1/+34
This probably need to be sent to mainline rather than here. gas/ * config/tc-riscv.c (FLT_CHARS): Added h and H. (riscv_pseudo_table): Added .float16. * read.c (hex_float): Handle case 'h' and 'H'. * testsuite/gas/riscv/extended/extended.exp: Updated. * testsuite/gas/riscv/extended/float16.d: New testcase. * testsuite/gas/riscv/extended/float16.s: Likewise.
2021-10-28RISC-V/zfh: Add half-precision floating-point v0.1 instructions.Nelson Chu8-0/+344
This patch is porting from the following riscv github, https://github.com/riscv/riscv-binutils-gdb/commits/rvv-1.0.x-zfh And here is the draft zfh spec, https://github.com/riscv/riscv-isa-manual/tree/zfh bfd/ * elfxx-riscv.c (riscv_supported_std_z_ext): Added zfh. (riscv_implicit_subset): Add implicit f and zicsr for zfh. gas/ * config/tc-riscv.c (riscv_extended_subset_supports): Handle INSN_CLASS*_ZFH. (extended_macro): Handle M_FLH and M_FSH. * testsuite/gas/riscv/extended/extended.exp: Updated. * testsuite/gas/riscv/extended/fp-zfh-insns.d: New testcase. * testsuite/gas/riscv/extended/fp-zfh-insns.s: Likewise. include/ * opcode/riscv-opc-extended.h: Added zfh encoding macros and DECLARE_INSN. * opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS*_ZFH. (enum M_FLH, M_FSH): Added. opcodes/ * riscv-opc.c (riscv_draft_opcodes): Added zfh instructions.
2021-10-28RISC-V/rvv: Add rvv v0.10 instructions.Nelson Chu42-41/+10151
2021-03-30 Jim Wilson <jimw@sifive.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> This patch is porting from the following riscv github, https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x And here is the vector draft spec, https://github.com/riscv/riscv-v-spec The match_func in opcodes/riscv-opc.c have many purposes. One of them is checking the instruction constraints. But we got the request before that the assembler constraint checkings break some hardware exception testcases, which are written by assmebly code. Therefore, we add new assembler options and .option directives to let users can disable/enable the rvv constraints. For now the constraints are disabled by default, but should we default enable them for safety? Besides, the match_func will return different error constriant messages, so that we can report the details to users. This should be more user-friendly. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Updated the draft version of v. (riscv_supported_std_z_ext): Added draft zvamo and zvlsseg. gas/ * config/tc-riscv.c (enum DRAFT_EXT): Added. (enum riscv_extended_csr_class): Added CSR_CLASS_V for rvv CSRs. (enum reg_extended_class): Added vector registers. (op_draft_hash): Added draft hash table for rvv. (md_begin): Init op_draft_hash and register hash for rvv. (riscv_extended_subset_supports): Handle INSN_CLASS_V*. (riscv_extended_csr_class_check): Handle CSR_CLASS_V. (validate_riscv_extended_insn): Check if the rvv instructions are valid. (riscv_find_extended_opcode_hash): Search instruction opcode from op_draft_hash. (vector_macro): Call macro_build to expand rvv macros into instructions. (extended_macro_build): Handle rvv operands for macro_build. (extended_macro): Handle M_VMSGE and M_VMSGEU. (my_getVsetvliExpression): Similar to my_getVsetvliExpression, but used for parsing vsetvli operands. (riscv_parse_extended_operands): Handle rvv operands. Pass &regno from riscv_ip, otherwise we will get fail when parsing Vf operand for AMO VS3. (riscv_ip): Add two new arguments to match_func, check_constraints and &error. We can disbale the match_func check by setting check_constraints to zero; The part of match_func will set different error messages to the &error, and them we can report more details to users. (riscv_set_options, riscv_opts, s_riscv_option): Add .option checkconstraints and nocheckconstraints, to enable/disable the match_func constraints checking. Disable it by default. (enum options, md_longopts, md_parse_option): Add assembler options m[no-]check-constraints. * testsuite/gas/riscv/extended/extended.exp: Updated. * testsuite/gas/riscv/extended/extended-csr.d: New testcase for rvv CSRs. * testsuite/gas/riscv/extended/extended-csr.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.d: New testcase for rvv constriants. * testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-int.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-int.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-int.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-load-store.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-load-store.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-load-store.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-mask.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-mask.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-mask.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-permutation.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-permutation.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-permutation.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-vmsgtvx.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-zero-imm.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-zero-imm.s: Likewise. * testsuite/gas/riscv/extended/vector-insns.d: Likewise. * testsuite/gas/riscv/extended/vector-insns.s: Likewise. include/ * opcode/riscv-opc-extended.h: Added rvv encoding macros and CSRs. * opcode/riscv.h: Added rvv immediate encodings and fields. (struct riscv_opcode): Updated match_func. (enum riscv_extended_insn_class): Added INSN_CLASS_V*. (enum M_VMSGE, M_VMSGEU): Added. opcodes/ * riscv-dis.c (print_extended_insn_args): Handle rvv operands. (riscv_disassemble_opcode): Updated match_func. * riscv-opc.c (match_*): Updated since two new parameters. (riscv_vecr_names_numeric): Added rvv register names. (riscv_vecm_names_numeric): Added rvv mask register name. (riscv_vsew, riscv_vlmul, riscv_vta, riscv_vma): Added for vsetvli. (MASK_VD, MASK_VS1, MASK_VS2, MASK_VMASK): Added for rvv match_func. (match_vs1_eq_vs2, match_vs1_eq_vs2_neq_vm, match_vd_eq_vs1_eq_vs2): Added to check special register usage, cannot be disabled. (match_widen_vd_neq_vs1_neq_vs2_neq_vm): The rvv constraint check, can be disabled/enabled by m[no-]check-constraints or .option [no]checkconstraints. (match_widen_vd_neq_vs1_neq_vm): Likewise. (match_widen_vd_neq_vs2_neq_vm): Likewise. (match_widen_vd_neq_vm): Likewise. (match_narrow_vd_neq_vs2_neq_vm): Likewise. (match_vd_neq_vs1_neq_vs2): Likewise. (match_vd_neq_vs1_neq_vs2_neq_vm): Likewise. (match_vd_neq_vs2_neq_vm): Likewise. (match_vd_neq_vm): Likewise. (match_vls_nf_rv): Likewise. (match_vmv_nf_rv): Likewise. (riscv_draft_opcodes): Added rvv v0.10 instructions. (riscv_extended_opcodes): Updated.
2021-10-28RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions.Nelson Chu6-355/+630
To keep the original functions clean, we try to provide assembler and dis-assembler hooks as enough as possible for extended extensions. We probably need to add more once they are not enough in the future. However, there are several changes that might need to be discussed as follows, * Change the type of enums to int directly, to extend them for extended extensions. Not sure if the change is good enough, but it should be the easiler way to extend enums. * The extended operands should be parsed in the extended hooks, validate_riscv_extended_insn and riscv_parse_extended_operands. Obviously, we may need to reparse the opernad string in the extended hooks, when the original functions cannot recognize them. But the original functions have already pointed the parsed poniter to the next characters. Therefore, we should use a new pointer, opargStart, to record the position before parsing, and then pass it to the hooks when we need to reparse the extended operands. * Part of the "internal: unknown" errors are reported in the extended hooks rather than the original functions. For example, we used to report the "internal: unreachable" in the riscv_multi_subset_supports, to tell developers that they forgot to handle the new defined INSN_CLASS_. And the function returns TRUE/FALSE if the instruction is allowed or not according to the architecture string. The riscv_extended_subset_supports is the extended hook of riscv_multi_subset_supports, so it also returns a bfd_boolean to check the same thing. But it is hard to know if the INSN_CLASS_* is unknown from the same returned bfd_boolean, unless we add another new flag, or we just move the error report to the hook directly. I choose the latter for now, but it may cause the code of mainline and integration branches are inconsistent, which may affect the difficulty of the regular merge between these two branches. The same inconsistent problem also happens in riscv_parse_extended_operands. The hook only parse an operand rather than all, so it just has a switch without a for loop. We used to set "continue" to skip the loop in the switch, but the extended hook doesn't need the "continue". Perhaps we should use a single while/for in the hooks to keep the code consistent, then the regular merge may be more easiler. * Rename the variables to the more meaningful names in the riscv_ip, validate_riscv_insn and print_insn_args. - oparg: Renamed from args, means the arguments in the opcode table. - opargStart: Added to record the start of the argument. - asarg: Renamed from s, means the arguments of assembly string. - asargStart: Renamed from argsStart. * Extract the part that parsing the instruction opcode from the riscv_disassemble_insn, since we will need to call it for many times to search multiple opcode tables. gas/ * config/tc-riscv.c (enum EXTENDED_EXT_NUM): Added to choose the right extended opcode hashes in the riscv_find_extended_opcode_hash. (enum riscv_csr_class): Added CSR_CLASS_EXTENDED. (enum reg_class): Added RCLASS_EXTENDED_NUM. (enum reg_extended_class): Added to define extended registers. (struct riscv_csr_extra): Changed enum riscv_csr_class to int, to increase the expandability of enum. (riscv_init_csr_hash): Likewise. (riscv_find_opcode_hash): Handle more than one opcode hashes. (md_begin): Included riscv-opc-extended.h to define extended CSR. (init_ext_version_hash): Updated. (riscv_get_default_ext_version): Likewise. (md_assemble): Likewise. (s_riscv_insn): Likewsie. (riscv_after_parse_args): Likewise. (riscv_find_extended_opcode_hash): Extended hook for riscv_find_opcode_hash. (riscv_extended_subset_supports): Extended hook for riscv_multi_subset_supports. (riscv_extended_csr_class_check): Extended hook for riscv_csr_address, to check the CSR ISA dependency. (extended_macro): Extended hook for macro. (validate_riscv_extended_insn): Extended hook for validate_riscv_insn. (extended_macro_build): Extended hook for macro_build. (riscv_parse_extended_operands): Extended hook for riscv_ip. (riscv_multi_subset_supports): Updated to call extended hook. (riscv_csr_address): Likewise (macro): Likewise. (validate_riscv_insn): Likewise. Also define new variables, xxx and xxxStart, in case single letters are not enough to represent all extended operands. (macro_build): Likewise. (riscv_ip): Likewise. The asarg means assembly operand string, and oparg means operand string defined in the opcode table. * testsuite/gas/riscv/extended/extended.exp: New file to run extended testcases. include/ * opcode/riscv-opc-extended.h: New file to define encoding macros and CSR for extended extensions. * opcode/riscv.h: Included riscv-opc-extended.h. (enum riscv_insn_class): Added INSN_CLASS_EXTENDED. (struct riscv_opcode): Same as struct riscv_csr_extra. (enum M_EXTENDED): Added to support extended pseudo macros. opcode/ * riscv-dis.c (print_extended_insn_args): Extended hook for print_insn_args. (print_insn_args): Updated to call extended hook, and same as what validate_riscv_insn does. Also include riscv-opc-extended.h to show extended CSR correctly. * riscv-opc.c (riscv_extended_opcodes): Added to store all supported extended instruction opcodes.
2021-10-27Automatic date update in version.inGDB Administrator1-1/+1
2021-10-26gold: Place .note.gnu.property section before other note sectionsH.J. Lu2-3/+9
Place the .note.gnu.property section before all other note sections to avoid being placed between other note sections with different alignments. PR gold/28494 * layout.cc (Layout::create_note): Set order to ORDER_PROPERTY_NOTE for the .note.gnu.property section. * layout.h (Output_section_order): Add ORDER_PROPERTY_NOTE.
2021-10-26[gdb/doc] Fix print inferior-events defaultTom de Vries1-1/+1
In the docs about print inferior-events we read: ... By default, these messages will not be printed. ... That used to be the case, but is no longer so since commit f67c0c91715 "Enable 'set print inferior-events' and improve detach/fork/kill/exit messages". Fix this by updating the docs.
2021-10-26Automatic date update in version.inGDB Administrator1-1/+1
2021-10-25gdb: change functions returning value contents to use gdb::array_viewSimon Marchi96-417/+453
The bug fixed by this [1] patch was caused by an out-of-bounds access to a value's content. The code gets the value's content (just a pointer) and then indexes it with a non-sensical index. This made me think of changing functions that return value contents to return array_views instead of a plain pointer. This has the advantage that when GDB is built with _GLIBCXX_DEBUG, accesses to the array_view are checked, making bugs more apparent / easier to find. This patch changes the return types of these functions, and updates callers to call .data() on the result, meaning it's not changing anything in practice. Additional work will be needed (which can be done little by little) to make callers propagate the use of array_view and reap the benefits. [1] https://sourceware.org/pipermail/gdb-patches/2021-September/182306.html Change-Id: I5151f888f169e1c36abe2cbc57620110673816f3
2021-10-25gdbsupport: add assertions in array_viewSimon Marchi1-4/+24
Add assertions to ensure we don't access an array_view out of bounds. Enable these assertions only when _GLIBCXX_DEBUG is set, as we did for gdb::optional. Change-Id: Iffaee38252405073735ed123c8e57fde6b2c6be3
2021-10-25gdbserver: make target_pid_to_str return std::stringSimon Marchi6-51/+50
I wanted to write a warning that included two target_pid_to_str calls, like this: warning (_("Blabla %s, blabla %s"), target_pid_to_str (ptid1), target_pid_to_str (ptid2)); This doesn't work, because target_pid_to_str stores its result in a static buffer, so my message would show twice the same ptid. Change target_pid_to_str to return an std::string to avoid this. I don't think we save much by using a static buffer, but it is more error-prone. Change-Id: Ie3f649627686b84930529cc5c7c691ccf5d36dc2
2021-10-25x86: Also handle stores for -muse-unaligned-vector-moveH.J. Lu4-15/+74
* config/tc-i386.c (encode_with_unaligned_vector_move): Also handle stores. * testsuite/gas/i386/unaligned-vector-move.s: Add stores. * testsuite/gas/i386/unaligned-vector-move.d: Updated. * testsuite/gas/i386/x86-64-unaligned-vector-move.d: Likewise.
2021-10-25[gdb/testsuite] Fix duplicate in gdb.mi/mi-var-cp.expTom de Vries1-1/+1
With test-case gdb.mi/mi-var-cp.exp I run into this duplicate: ... PASS: gdb.mi/mi-var-cp.exp: run to mi-var-cp.cc:104 (set breakpoint) PASS: gdb.mi/mi-var-cp.exp: create varobj for s PASS: gdb.mi/mi-var-cp.exp: create varobj for s DUPLICATE: gdb.mi/mi-var-cp.exp: create varobj for s ... This is due to a duplicate test name here: ... $ cat -n gdb/testsuite/gdb.mi/mi-var-cp.cc ... 100 int reference_to_struct () 101 { 102 /*: BEGIN: reference_to_struct :*/ 103 S s = {7, 8}; 104 S& r = s; 105 /*: 106 mi_create_varobj S s "create varobj for s" 107 mi_create_varobj R r "create varobj for s" ... Fix this by using "create varobj for r" instead. Tested on x86_64-linux.
2021-10-25libctf, ld: handle nonrepresentable types betterNick Alcock5-6/+53
ctf_type_visit (used, among other things, by the type dumping code) was aborting when it saw a nonrepresentable type anywhere: even a single structure member with a nonrepresentable type caused an abort with ECTF_NONREPRESENTABLE. This is not useful behaviour, given that the abort comes from a type-resolution we are only doing in order to determine whether the type is a structure or union. We know nonrepresentable types can't be either, so handle that case and pass the nonrepresentable type down. (The added test verifies that the dumper now handles this case and prints nonrepresentable structure members as it already does nonrepresentable top-level types, rather than skipping the whole structure -- or, without the previous commit, skipping the whole types section.) ld/ChangeLog 2021-10-25 Nick Alcock <nick.alcock@oracle.com> * testsuite/ld-ctf/nonrepresentable-member.*: New test. libctf/ChangeLog 2021-10-25 Nick Alcock <nick.alcock@oracle.com> * ctf-types.c (ctf_type_rvisit): Handle nonrepresentable types.
2021-10-25libctf: dump: do not stop dumping types on errorNick Alcock2-4/+14
If dumping of a single type fails, we obviously can't dump it; but just as obviously this doesn't make the other types in the types section invalid or undumpable. So we should not propagate errors seen when type-dumping, but rather ignore them and carry on, so we dump as many types as we can (leaving out the ones we can't grok). libctf/ChangeLog 2021-10-25 Nick Alcock <nick.alcock@oracle.com> * ctf-dump.c (ctf_dump_type): Do not abort on error.
2021-10-25binutils, ld: make objdump --ctf's parameter optionalNick Alcock35-35/+81
ld by default (and always, unless adjusted with a hand-rolled linker script) emits deduplicated CTF into the .ctf section. But viewing it needs you to explicitly tell objdump this: it doesn't default its argument, even though what you always end up typing is --ctf=.ctf. This is annoying, so make the argument optional. binutils/ChangeLog 2021-10-25 Nick Alcock <nick.alcock@oracle.com> * objdump.c (usage): --ctf now has an optional argument. (main): Adjust accordingly. (dump_ctf): Default it. * doc/ctf.options.texi: Adjust. ld/ChangeLog 2021-10-25 Nick Alcock <nick.alcock@oracle.com> * testsuite/ld-ctf/array.d: Change --ctf=.ctf to --ctf. * testsuite/ld-ctf/conflicting-cycle-1.B-1.d: Likewise. * testsuite/ld-ctf/conflicting-cycle-1.B-2.d: Likewise. * testsuite/ld-ctf/conflicting-cycle-1.parent.d: Likewise. * testsuite/ld-ctf/conflicting-cycle-2.A-1.d: Likewise. * testsuite/ld-ctf/conflicting-cycle-2.A-2.d: Likewise. * testsuite/ld-ctf/conflicting-cycle-2.parent.d: Likewise. * testsuite/ld-ctf/conflicting-cycle-3.C-1.d: Likewise. * testsuite/ld-ctf/conflicting-cycle-3.C-2.d: Likewise. * testsuite/ld-ctf/conflicting-cycle-3.parent.d: Likewise. * testsuite/ld-ctf/conflicting-enums.d: Likewise. * testsuite/ld-ctf/conflicting-typedefs.d: Likewise. * testsuite/ld-ctf/cross-tu-cyclic-conflicting.d: Likewise. * testsuite/ld-ctf/cross-tu-cyclic-nonconflicting.d: Likewise. * testsuite/ld-ctf/cross-tu-into-cycle.d: Likewise. * testsuite/ld-ctf/cross-tu-noncyclic.d: Likewise. * testsuite/ld-ctf/cycle-1.d: Likewise. * testsuite/ld-ctf/cycle-2.A.d: Likewise. * testsuite/ld-ctf/cycle-2.B.d: Likewise. * testsuite/ld-ctf/cycle-2.C.d: Likewise. * testsuite/ld-ctf/data-func-conflicted.d: Likewise. * testsuite/ld-ctf/diag-cttname-null.d: Likewise. * testsuite/ld-ctf/diag-cuname.d: Likewise. * testsuite/ld-ctf/diag-parlabel.d: Likewise. * testsuite/ld-ctf/enum-forward.d: Likewise. * testsuite/ld-ctf/enums.d: Likewise. * testsuite/ld-ctf/forward.d: Likewise. * testsuite/ld-ctf/function.d: Likewise. * testsuite/ld-ctf/nonrepresentable.d: Likewise. * testsuite/ld-ctf/slice.d: Likewise. * testsuite/ld-ctf/super-sub-cycles.d: Likewise.
2021-10-25binutils: make objdump/readelf --ctf-parent actually usefulNick Alcock4-121/+86
This option has been present since the very early days of the development of libctf as part of binutils, and it shows. Back in the earliest days, I thought we might handle ambiguous types by introducing new ELF sections on the fly named things like .ctf.foo.c for ambiguous types found only in foo.c, etc. This turned out to be a terrible idea, so we moved to using a CTF archive in the .ctf section which contained all the CTF dictionaries -- but the --ctf-parent option in objdump and readelf was never adjusted, and lingered as a mechanism to specify CTF parent dictionaries in sections other than .ctf, even though the linker has no way to produce parent dictionaries in different sections from their children, libctf's ctf_open can't handle such split-up parent/child dicts, and they are never found in the wild, emitted by GNU ld or by any known third-party linking tool. Meanwhile, the actually-useful ctf_link feature (albeit not used by ld) which lets you remap the names of CTF archive members (so you can end up with a parent archive member named something other than ".ctf", still contained with all its children in a single .ctf section) had no support in objdump or readelf: there was no way to tell them that these members were parents, so all the types in the associated child dicts always appeared corrupted, referencing nonexistent types from a parent objdump couldn't find. So adjust --ctf-parent so that rather than taking a section name it takes a member name instead (if not specified, the name is ".ctf", which is what GNU ld emits). Because the option was always useless before now, this is expected to have no backward-compatibility implications. As part of this, we have to slightly adjust the code which skips the archive member name if redundant: right now it skips it if it's ".ctf", on the assumption that this name will almost always be at the start of the objdump output and thus we'll end up with a shared dump and then smaller, headed dumps for the per-TU child dicts; but if the parent name has been changed, that won't be true any more. So change the rules to "members named .ctf which appear first in the first have their member name skipped". Since we now need to count members, move from ctf_archive_iter (for which passing in extra parameters requires defining a new struct and is clumsy) to ctf_archive_next, allowing us to just *call* dump_ctf_archive_member and maintain a member count in the obvious way. In the process we fix a tiny difference between readelf and objdump: if a ctf_dump ever failed, readelf skipped every later member, while objdump tried to keep going as much as it could. For a dumping tool the former is clearly preferable. binutils/ChangeLog 2021-10-25 Nick Alcock <nick.alcock@oracle.com> * objdump.c (usage): --ctf-parent now takes a name, not a section. (dump_ctf): Don't open a separate section; use the parent_name in ctf_dict_open instead. Use ctf_archive_next, not ctf_archive_iter, so we can pass down a member count. (dump_ctf_archive_member): Add the member count; don't return anything. Import parents into children no matter what the parent's name, while still avoiding displaying the header for the common parent name of ".ctf". * readelf.c (usage): Adjust similarly. (dump_section_as_ctf): Likewise. (dump_ctf_archive_member): Likewise. Never stop iterating over archive members, even if ctf_dump of one member fails. * doc/ctf.options.texi: Adjust.
2021-10-25objdump doesn't accept -L optionAlan Modra1-1/+1
A followup to commit ca0e11aa4b. * objdump.c (main): Add 'L' to short options and sort them.
2021-10-25bfd_nonfatal_message, localise va_startAlan Modra1-3/+3
Nothing to see here, just a little tidier. * bucomm.c (bfd_nonfatal_message): Localise va_list args.
2021-10-25ubsan: _bfd_xcoff64_swap_aux_in left shift of negative valueAlan Modra1-5/+2
* coff64-rs6000.c (_bfd_xcoff64_swap_aux_in): Use bfd_vma for h.
2021-10-25asan: evax_bfd_print_image buffer overflowAlan Modra1-42/+51
* vms-alpha.c (evax_bfd_print_image): Sanity check printing of "image activator fixup" section. (evax_bfd_print_relocation_records): Sanity check buffer offsets. (evax_bfd_print_address_fixups): Likewise. (evax_bfd_print_reference_fixups): Likewise.
2021-10-25Automatic date update in version.inGDB Administrator1-1/+1
2021-10-24asan: c4x, c54x coff_canonicalize_reloc buffer overflowAlan Modra6-17/+44
Sometimes the investigation of a fuzzing bug report leads into areas you'd rather not go. In this instance by the time I'd figured out the real cause was a target variant that had never been properly supported in binutils, the time needed to fix it was less than the time needed to rip it out. * coffcode.h (coff_set_alignment_hook): Call bfd_coff_swap_reloc_in not coff_swap_reloc_in. (coff_slurp_reloc_table): Likewise. Don't use RELOC type. (ticoff0_swap_table): Use coff_swap_reloc_v0_out and coff_swap_reloc_v0_in. * coffswap.h (coff_swap_reloc_v0_in, coff_swap_reloc_v0_out): New. * coff-tic54x.c (tic54x_lookup_howto): Don't abort. * coffgen.c (coff_get_normalized_symtab): Use PTR_ADD. * bfd-in.h (PTR_ADD, NPTR_ADD): Avoid warnings when passing an expression. * bfd-in2.h: Regenerate.
2021-10-24asan: arm-darwin: buffer overflowAlan Modra1-18/+21
PR 21813 * mach-o-arm.c (bfd_mach_o_arm_canonicalize_one_reloc): Sanity check PAIR reloc in other branch of condition as was done for PR21813. Formatting. Delete debug printf.
2021-10-24asan: aout: heap buffer overflowAlan Modra2-6/+4
* aoutx.h (aout_get_external_symbols): Sanity check before writing zero index entry. Remove outdated comment. * pdp11.c (aout_get_external_symbols): Likewise.
2021-10-24LoongArch ld supportliuzhensong22-1/+1146
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> Xiaolin Tang <tangxiaolin@loongson.cn> ld/ * Makefile.am: Add LoongArch. * NEWS: Mention LoongArch support. * configure.tgt: Add LoongArch. * emulparams/elf32loongarch-defs.sh: New. * emulparams/elf32loongarch.sh: Likewise. * emulparams/elf64loongarch-defs.sh: Likewise. * emulparams/elf64loongarch.sh: Likewise. * emultempl/loongarchelf.em: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. ld/testsuite/ * ld-loongarch-elf/disas-jirl.d: New. * ld-loongarch-elf/disas-jirl.s: Likewise. * ld-loongarch-elf/jmp_op.d: Likewise. * ld-loongarch-elf/jmp_op.s: Likewise. * ld-loongarch-elf/ld-loongarch-elf.exp: Likewise. * ld-loongarch-elf/macro_op.d: Likewise. * ld-loongarch-elf/macro_op.s: Likewise. * ld-loongarch-elf/syscall-0.s: Likewise. * ld-loongarch-elf/syscall-1.s: Likewise. * ld-loongarch-elf/syscall.d: Likewise. * ld-srec/srec.exp: Add LoongArch. * ld-unique/pr21529.d: Likewise.
2021-10-24LoongArch gas supportliuzhensong39-5/+4152
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> Xiaolin Tang <tangxiaolin@loongson.cn> gas/ * Makefile.am: Add LoongArch. * NEWS: Mention LoongArch support. * config/loongarch-lex-wrapper.c: New. * config/loongarch-lex.h: New. * config/loongarch-lex.l: New. * config/loongarch-parse.y: New. * config/tc-loongarch.c: New. * config/tc-loongarch.h: New. * configure.ac: Add LoongArch. * configure.tgt: Likewise. * doc/as.texi: Likewise. * doc/c-loongarch.texi: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/all/gas.exp: Add LoongArch. * gas/elf/elf.exp: Likewise. * gas/loongarch/4opt_op.d: New. * gas/loongarch/4opt_op.s: Likewise. * gas/loongarch/fix_op.d: Likewise. * gas/loongarch/fix_op.s: Likewise. * gas/loongarch/float_op.d: Likewise. * gas/loongarch/float_op.s: Likewise. * gas/loongarch/imm_op.d: Likewise. * gas/loongarch/imm_op.s: Likewise. * gas/loongarch/jmp_op.d: Likewise. * gas/loongarch/jmp_op.s: Likewise. * gas/loongarch/load_store_op.d: Likewise. * gas/loongarch/load_store_op.s: Likewise. * gas/loongarch/loongarch.exp: Likewise. * gas/loongarch/macro_op.d: Likewise. * gas/loongarch/macro_op.s: Likewise. * gas/loongarch/nop.d: Likewise. * gas/loongarch/nop.s: Likewise. * gas/loongarch/privilege_op.d: Likewise. * gas/loongarch/privilege_op.s: Likewise. * gas/loongarch/syscall.d: Likewise. * gas/loongarch/syscall.s: Likewise. * lib/gas-defs.exp: Add LoongArch.
2021-10-24LoongArch binutils supportliuzhensong3-0/+27
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> binutils/ * NEWS: Mention LoongArch support. * readelf.c: Add LoongArch. * testsuite/binutils-all/objdump.exp: Add LoongArch.
2021-10-24LoongArch opcodes supportliuzhensong12-0/+1877
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> include/ * opcode/loongarch.h: New. * dis-asm.h: Declare print_loongarch_disassembler_options. opcodes/ * Makefile.am: Add LoongArch. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Declare print_insn_loongarch. * loongarch-coder.c: New. * loongarch-dis.c: New. * loongarch-opc.c: New. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2021-10-24LoongArch bfd supportliuzhensong20-3/+4519
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> bfd/ * Makefile.am: Add LoongArch. * archures.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * cpu-loongarch.c: New. * elf-bfd.h: Add LoongArch. * elf.c: Add LoongArch elfcore_grok_xxx. * elfnn-loongarch.c: New. * elfxx-loongarch.c: New. * elfxx-loongarch.h: New. * reloc.c: Add LoongArch BFD RELOC ENUM. * targets.c: Add LoongArch target. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * po/BLD-POTFILES.in: Regenerate. * po/SRC-POTFILES.in: Regenerate. include/ * elf/common.h: Add NT_LARCH_{CPUCFG,CSR,LSX,LASX}. * elf/loongarch.h: New.
2021-10-24Automatic date update in version.inGDB Administrator1-1/+1
2021-10-23Automatic date update in version.inGDB Administrator1-1/+1
2021-10-22x86: Add -muse-unaligned-vector-move to assemblerH.J. Lu7-0/+110
Unaligned load/store instructions on aligned memory or register are as fast as aligned load/store instructions on modern Intel processors. Add a command-line option, -muse-unaligned-vector-move, to x86 assembler to encode encode aligned vector load/store instructions as unaligned vector load/store instructions. * NEWS: Mention -muse-unaligned-vector-move. * config/tc-i386.c (use_unaligned_vector_move): New. (encode_with_unaligned_vector_move): Likewise. (md_assemble): Call encode_with_unaligned_vector_move for -muse-unaligned-vector-move. (OPTION_MUSE_UNALIGNED_VECTOR_MOVE): New. (md_longopts): Add -muse-unaligned-vector-move. (md_parse_option): Handle -muse-unaligned-vector-move. (md_show_usage): Add -muse-unaligned-vector-move. * doc/c-i386.texi: Document -muse-unaligned-vector-move. * testsuite/gas/i386/i386.exp: Run unaligned-vector-move and x86-64-unaligned-vector-move. * testsuite/gas/i386/unaligned-vector-move.d: New file. * testsuite/gas/i386/unaligned-vector-move.s: Likewise. * testsuite/gas/i386/x86-64-unaligned-vector-move.d: Likewise.
2021-10-22Fix 'uninstall' targetTom Tromey2-3/+14
This adds some missing code to the 'uninstall' targets in gdb and gdbserver. It also changes gdb's uninstall target so that it no longer tries to remove any man page -- this is already done (and more correctly) by doc/Makefile.in. I tested this with 'make install' followed by 'make uninstall', then examining the install tree for regular files. Only the 'dir' file remains, but this appears to just be how 'install-info' is intended to work.
2021-10-22Remove unused variables from gdbserver's MakefileTom Tromey1-26/+1
This removes a number of unused variables from gdbserver's Makefile. I found these while working on the subsequent patches, and figured it would be cleaner to have a separate patch for the deletions.
2021-10-22[gdb/testsuite] Fix gdb.threads/linux-dp.expTom de Vries1-1/+1
On openSUSE Tumbleweed with glibc-debuginfo installed I get: ... (gdb) PASS: gdb.threads/linux-dp.exp: continue to breakpoint: thread 5's print where^M #0 print_philosopher (n=3, left=33 '!', right=33 '!') at linux-dp.c:105^M #1 0x0000000000401628 in philosopher (data=0x40537c) at linux-dp.c:148^M #2 0x00007ffff7d56b37 in start_thread (arg=<optimized out>) \ at pthread_create.c:435^M #3 0x00007ffff7ddb640 in clone3 () \ at ../sysdeps/unix/sysv/linux/x86_64/clone3.S:81^M (gdb) PASS: gdb.threads/linux-dp.exp: first thread-specific breakpoint hit ... while without debuginfo installed I get instead: ... (gdb) PASS: gdb.threads/linux-dp.exp: continue to breakpoint: thread 5's print where^M #0 print_philosopher (n=3, left=33 '!', right=33 '!') at linux-dp.c:105^M #1 0x0000000000401628 in philosopher (data=0x40537c) at linux-dp.c:148^M #2 0x00007ffff7d56b37 in start_thread () from /lib64/libc.so.6^M #3 0x00007ffff7ddb640 in clone3 () from /lib64/libc.so.6^M (gdb) FAIL: gdb.threads/linux-dp.exp: first thread-specific breakpoint hit ... The problem is that the regexp used: ... "\(from .*libpthread\|at pthread_create\|in pthread_create\)" ... expects the 'from' part to match libpthread, but in glibc 2.34 libpthread has been merged into libc. Fix this by updating the regexp. Tested on x86_64-linux.
2021-10-22[gdb/testsuite] Fix FAILs in gdb.mi/mi-breakpoint-changed.expTom de Vries1-2/+2
Since commit e36788d1354 "[gdb/testsuite] Fix handling of nr_args < 3 in mi_gdb_test" we run into: ... PASS: gdb.mi/mi-breakpoint-changed.exp: test_auto_disable: mi runto main Expecting: ^(-break-insert -f pendfunc1[^M ]+)?((&.*)*.*~"Breakpoint 2 at.*\\n".*=breakpoint-created,\ bkpt=\{number="2",type="breakpoint".*\}.*\n\^done[^M ]+[(]gdb[)] ^M [ ]*) -break-insert -f pendfunc1^M ^done,bkpt={number="2",type="breakpoint",disp="keep",enabled="y",\ addr="0x00007ffff7bd559e",func="pendfunc1",\ file="gdb/testsuite/gdb.mi/pendshr1.c",\ fullname="gdb/testsuite/gdb.mi/pendshr1.c",line="21",thread-groups=["i1"],\ times="0",original-location="pendfunc1"}^M (gdb) ^M FAIL: gdb.mi/mi-breakpoint-changed.exp: test_auto_disable: \ -break-insert -f pendfunc1 (unexpected output) ... The regexp expects a breakpoint-created event, but that's actually suppressed by the command: ... DEF_MI_CMD_MI_1 ("break-insert", mi_cmd_break_insert, &mi_suppress_notification.breakpoint), ... Fix this by updating the regexp. Likewise for the following: ... PASS: gdb.mi/mi-breakpoint-changed.exp: test_auto_disable: \ -break-insert -f pendfunc1 Expecting: ^(-break-enable count 1 2[^M ]+)?(=breakpoint-modified,\ bkpt=\{number="2",type="breakpoint",disp="dis",enabled="y".*\}.*\n\^done[^M ]+[(]gdb[)] ^M [ ]*) -break-enable count 1 2^M ^done^M (gdb) ^M FAIL: gdb.mi/mi-breakpoint-changed.exp: test_auto_disable: \ -break-enable count 1 2 (unexpected out\ put) ... Tested on x86_64-linux.
2021-10-22gdb/python: move gdb.Membuf support into a new fileAndrew Burgess5-179/+236
In a future commit I'm going to be creating gdb.Membuf objects from a new file within gdb/python/py*.c. Currently all gdb.Membuf objects are created directly within infpy_read_memory (as a result of calling gdb.Inferior.read_memory()). Initially I split out the Membuf creation code into a new function, and left the new function in gdb/python/py-inferior.c, however, it felt a little random that the Membuf creation code should live with the inferior handling code. So, then I moved all of the Membuf related code out into a new file, gdb/python/py-membuf.c, the interface is gdbpy_buffer_to_membuf, which wraps an array of bytes into a gdb.Membuf object. Most of the code is moved directly from py-inferior.c with only minor tweaks to layout and replacing NULL with nullptr, hence, I've left the copyright date on py-membuf.c as 2009-2021 to match py-inferior.c. Currently, the only user of this code is still py-inferior.c, but in later commits this will change. There should be no user visible changes after this commit.
2021-10-22gdb/python: new gdb.architecture_names functionAndrew Burgess6-0/+92
Add a new function to the Python API, gdb.architecture_names(). This function returns a list containing all of the supported architecture names within the current build of GDB. The values returned in this list are all of the possible values that can be returned from gdb.Architecture.name().
2021-10-22gdb: make disassembler fprintf callback a static member functionAndrew Burgess2-16/+18
The disassemble_info structure has four callbacks, we have three of them as static member functions within gdb_disassembler, the fourth is just a global static function. However, this fourth callback, is still only used from the disassemble_info struct, so there's no real reason for its special handling. This commit makes fprintf_disasm a static method within gdb_disassembler. There should be no user visible changes after this commit.
2021-10-22RISC-V: Added ld testcase for pcgp relaxation.Lewis Revill5-2/+36
Consider the the pcgp-relax-02 testcase, .text .globl _start _start: .L1: auipc a0, %pcrel_hi(data_a) .L2: auipc a1, %pcrel_hi(data_b) addi a0, a0, %pcrel_lo(.L1) addi a1, a1, %pcrel_lo(.L2) .data .word 0x0 .globl data_a data_a: .word 0x1 .section .rodata .globl data_b data_b: .word 0x2 If the first auipc is deleted, but we are still building the pcgp table (connect the high and low pcrel relocations), then there is an aliasing issue that we need some way to disambiguate which of the two symbols we are targeting. Therefore, Palmer thought of a way to use R_RISCV_DELETE to split this into two phases, so we could resolve the addresses before creating the ambiguities. This patch just add the ld testcase for the above case, in case we have changed something but break this. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Renamed pcgp-relax to pcgp-relax-01, and added pcgp-relax-02. * testsuite/ld-riscv-elf/pcgp-relax-01.d: Renmaed from pcgp-relax. * testsuite/ld-riscv-elf/pcgp-relax-01.s: Likewise. * testsuite/ld-riscv-elf/pcgp-relax-02.d: New testcase. * testsuite/ld-riscv-elf/pcgp-relax-02.s: Likewise.
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