Age | Commit message (Collapse) | Author | Files | Lines |
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Remove FUNCTION pointer in struct btrace_insn_iterator and use an index into
the list of function segments instead.
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Remove FUNCTION pointer in struct btrace_call_iterator and use an index into
the list of function segments instead.
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This will serve as the access path to the vector of function segments once
the FUNCTION pointer in struct btrace_insn_iterator is removed.
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Directly insert new btrace_function pointers into the vector and have the
vector own these pointers. This allows us to later retrieve these objects by
their number directly after creation whereas at the moment we have to wait
until the vector is fully populated.
This requires to pull btrace_thread_info through different functions but
cleans up the code for freeing the trace.
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gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Fix indentation.
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Change the GDB 8.0 section of the NEWS file to try to follow this order:
* Functional changes
* Added and removed configurations and targets
* New commands
* New options
* MI changes
In particular, there were two "New commands" sections.
gdb/ChangeLog:
* NEWS (Changes in GDB 8.0): Remove extra empty line. Move
"Removed targets and native configurations" up. Merge duplicate
"New commands" sub-sections. Add "New options" sub-sections.
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This test requires calling a function in the inferior, and therefore it
doesn't make sense to run it if the target doesn't support calling
functions from GDB.
gdb/testsuite/ChangeLog:
* gdb.base/watch-cond-infcall.exp: Don't run if target doesn't
support function calls from GDB.
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opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Add new instruction types RRF_0URF and RRF_0UREFE.
* s390-opc.txt: Fix instruction typs of csdtr and csxtr.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-z9-ec.d: Adjust csdtr and csxtr.
* testsuite/gas/s390/zarch-z9-ec.s: Likewise.
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gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/esa-g5.d: Add missing operand to tb
instruction.
* testsuite/gas/s390/esa-g5.s: Likewise.
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.txt: Add missing operand to tb instruction.
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This patch adds missing variants of ipte and idte instructions added with later CPU
generations.
ipte got an optional operand with z196 and another one with zEC12.
idte got an optional operand with zEC12
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Add new idte/ipte variants.
* s390-opc.txt: Likewise.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-z196.d: Add new idte/ipte variants.
* testsuite/gas/s390/zarch-z196.s: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Likewise.
* testsuite/gas/s390/zarch-zEC12.s: Likewise.
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So far we only had an instruction flag which made an arbitrary number
of operands optional. This limits error checking capabilities for
instructions marked that way. With this patch the optparm flag only
allows a single optional parameter and another one is added (optparm2)
allowing 2 optional arguments. Hopefully we won't need more than that
in the future. So far there will be only a single use of optparm2.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Support new optparm2
instruction flag.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Add new instruction flags optparm2.
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-dis.c (s390_print_insn_with_opcode): Support new optparm2
instruction flag.
* s390-mkopc.c (main): Recognize the new instruction flag when
parsing instruction list.
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The per operand optional flag hasn't been used for quite some time.
Cleanup some remains.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Remove S390_OPERAND_OPTIONAL.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Remove code dealing with
S390_OPERAND_OPTIONAL.
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Use these to replace instances of MAX_REGISTER_SIZE.
* defs.h (copy_integer_to_size): New declaration.
* findvar.c (copy_integer_to_size): New function.
(do_cint_test): New selftest function.
(copy_integer_to_size_test): Likewise.
(_initialize_findvar): Likewise.
* mips-fbsd-tdep.c (mips_fbsd_supply_reg): Use raw_supply_integer.
(mips_fbsd_collect_reg): Use raw_collect_integer.
* mips-linux-tdep.c (supply_32bit_reg): Use raw_supply_integer.
(mips64_fill_gregset): Use raw_collect_integer
(mips64_fill_fpregset): Use raw_supply_integer.
* regcache.c (regcache::raw_supply_integer): New function.
(regcache::raw_collect_integer): Likewise.
* regcache.h: (regcache::raw_supply_integer): New declaration.
(regcache::raw_collect_integer): Likewise.
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This patch adds one unit test for gdbarch methods register_to_value and
value_to_register. The test pass different combinations of {regnu, type}
to gdbarch_register_to_value and gdbarch_value_to_register. In order
to do the test, add a new function create_new_frame to create a fake
frame. It can be improved after we converted frame_info to class.
In order to isolate regcache (from target_ops operations on writing
registers, like target_store_registers), the sub-class of regcache in the
test override raw_write. Also, in order to get the right regcache from
get_thread_arch_aspace_regcache, the sub-class of regcache inserts itself
to current_regcache.
Suppose I incorrectly modified the size of buffer as below,
@@ -1228,7 +1228,7 @@ ia64_register_to_value (struct frame_info *frame, int regnum,
int *optimizedp, int *unavailablep)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
- gdb_byte in[MAX_REGISTER_SIZE];
+ gdb_byte in[1];
/* Convert to TYPE. */
if (!get_frame_register_bytes (frame, regnum, 0,
build GDB with "-fsanitize=address" and run unittest.exp, asan can detect
such error
==2302==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fff98193870 at pc 0xbd55ea bp 0x7fff981935a0 sp 0x7fff98193598
WRITE of size 16 at 0x7fff98193870 thread T0
#0 0xbd55e9 in frame_register_unwind(frame_info*, int, int*, int*, lval_type*, unsigned long*, int*, unsigned char*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1119
#1 0xbd58c8 in frame_register(frame_info*, int, int*, int*, lval_type*, unsigned long*, int*, unsigned char*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1147
#2 0xbd6e25 in get_frame_register_bytes(frame_info*, int, unsigned long, int, unsigned char*, int*, int*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1427
#3 0x70080a in ia64_register_to_value /home/yao/SourceCode/gnu/gdb/git/gdb/ia64-tdep.c:1236
#4 0xbf570e in gdbarch_register_to_value(gdbarch*, frame_info*, int, type*, unsigned char*, int*, int*) /home/yao/SourceCode/gnu/gdb/git/gdb/gdbarch.c:2619
#5 0xc05975 in register_to_value_test /home/yao/SourceCode/gnu/gdb/git/gdb/gdbarch-selftests.c:131
Or, even if GDB is not built with asan, GDB just crashes.
*** stack smashing detected ***: ./gdb terminated
Aborted (core dumped)
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* Makefile.in (SFILES): Add gdbarch-selftests.c.
(COMMON_OBS): Add gdbarch-selftests.o.
* frame.c [GDB_SELF_TESTS] (create_new_frame): New function.
* frame.h [GDB_SELF_TESTS] (create_new_frame): Declare.
* gdbarch-selftests.c: New file.
* regcache.h (regcache) <~regcache>: Mark it virtual if
GDB_SELF_TEST.
<raw_write>: Likewise.
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This patches moves global variable current_regcache to a class regcache
static variable (protected) so that the unit test I add in the following
patch can access it (by means of extending class regcache in unit test).
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* regcache.c (current_regcache): Change it to
regcache::current_regcache.
(regcache_observer_target_changed): Update.
(regcache_thread_ptid_changed): Make it a regcache static
method.
(regcache_thread_ptid_changed): Update.
(class regcache_access): New.
(current_regcache_test): Update.
(_initialize_regcache): Update.
* regcache.h: Include forward_list.
(regcache): Declare regcache_thread_ptid_changed and declare
registers_changed_ptid as friend.
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We should use register_size to get register contents instead of
TYPE_LENGTH.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* i387-tdep.c (i387_register_to_value): Use register_size
instead of TYPE_LENGTH.
* m68k-tdep.c (m68k_register_to_value): Likewise.
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gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* i387-tdep.c (i387_convert_register_p): Return false if type
code isn't TYPE_CODE_FLT.
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This patch restricts alpha_convert_register_p from
"TYPE_LENGTH (type) != 8" to "TYPE_LENGTH (type) == 4", because,
- we have check "TYPE_LENGTH (valtype) == 4" in alpha_register_to_value
and alpha_value_to_register,
- alpha lds and sts instruction access 4 bytes,
- comments "It might need to convert the [float] register into the
corresponding [integer] type (see Alpha)" and integer is 4-byte on
alpha,
I think it is the right restrict condition to "TYPE_LENGTH (valtype) == 4".
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* alpha-tdep.c (alpha_convert_register_p): Return true if type
length is 4.
(alpha_register_to_value): Remove type length check.
(alpha_value_to_register): Likewise.
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gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* ia64-tdep.c (ia64_convert_register_p): Check type's code is
TYPE_CODE_FLT.
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We need to convert register if the type is float. Suppose we get a value
from float point register, but its type is integer, we don't have to convert.
This case may not exist in real code, but exist in my unit test case.
warning: Cannot convert floating-point register value to non-floating-point type.
Self test failed: arch m68k: self-test failed at gdb/git/gdb/findvar.c:1072
ok = gdbarch_register_to_value (gdbarch, frame, regnum, type,
buf.data (), &optim, &unavail);
1072: SELF_CHECK (ok);
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* m68k-tdep.c (m68k_convert_register_p): Check type's code is
TYPE_CODE_FLT or not.
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This patch uses XCNEW gdbarch_tdep instead of XNEW.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* alpha-tdep.c (alpha_gdbarch_init): Use XCNEW instead of XNEW.
* avr-tdep.c (avr_gdbarch_init): Likewise.
* bfin-tdep.c (bfin_gdbarch_init): Likewise.
* cris-tdep.c (cris_gdbarch_init): Likewise.
* ft32-tdep.c (ft32_gdbarch_init): Likewise.
* lm32-tdep.c (lm32_gdbarch_init): Likewise.
* m32r-tdep.c (m32r_gdbarch_init): Likewise.
* m68hc11-tdep.c (m68hc11_gdbarch_init): Likewise.
* mep-tdep.c (mep_gdbarch_init): Likewise.
* microblaze-tdep.c (microblaze_gdbarch_init): Likewise.
* mips-tdep.c (mips_gdbarch_init): Likewise.
* mn10300-tdep.c (mn10300_gdbarch_init): Likewise.
* moxie-tdep.c (moxie_gdbarch_init): Likewise.
* msp430-tdep.c (msp430_gdbarch_init): Likewise.
* sh64-tdep.c (sh64_gdbarch_init): Likewise.
* v850-tdep.c (v850_gdbarch_init): Likewise.
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GDB has some global variables, like sentinel_frame,
current_thread_arch, and etc, we need to reset them after each unit
tests.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* selftest-arch.c (tests_with_arch): Call registers_changed
and reinit_frame_cache.
* selftest.c (run_self_tests): Likewise.
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With the changes done in previous patches, print_insn_XXX functions
don't have to be external visible out of opcodes, because both gdb
and objdump select disassemblers through a single interface.
This patch moves these print_insn_XXX declarations from
include/dis-asm.h to opcodes/disassemble.h, which is a new header
added by this patch.
include:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* dis-asm.h: Move some function declarations to
opcodes/disassemble.h.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* alpha-dis.c: Include disassemble.h, don't include
dis-asm.h.
* avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
* crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
* disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
* fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
* hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
* i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
* iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
* m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
* m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
* metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
* moxie-dis.c, msp430-dis.c, mt-dis.c:
* nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
* or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
* ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
* rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
* sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
* tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
* tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
* v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
* w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
* xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
* z80-dis.c, z8k-dis.c: Likewise.
* disassemble.h: New file.
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Nowadays, rs6000 disassembler is selected in different ways in
opcodes and gdb,
opcodes:
case bfd_arch_rs6000:
if (mach == bfd_mach_ppc_620)
disassemble = print_insn_big_powerpc;
else
disassemble = print_insn_rs6000;
break;
gdb:
if (arch == bfd_arch_rs6000)
set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
else
set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
I am not sure which one is the right one. However, such selection
should be done in one place instead of two.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* rs6000-tdep.c (gdb_print_insn_powerpc): Remove.
(rs6000_gdbarch_init): Don't call set_gdbarch_print_insn.
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This patch changes rl78 to let disassble.c:disassembler select
disassembler. rl78_get_disassembler doesn't handle the case
that abfd is NULL, so this patch also fix it.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* rl78-tdep.c (rl78_gdbarch_init): Don't call
set_gdbarch_print_insn.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* rl78-dis.c (rl78_get_disassembler): If parameter abfd
is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
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opcodes/disassble.c:disassembler select h8300 disassembler like this,
if (mach == bfd_mach_h8300h || mach == bfd_mach_h8300hn)
disassemble = print_insn_h8300h;
else if (mach == bfd_mach_h8300s
|| mach == bfd_mach_h8300sn
|| mach == bfd_mach_h8300sx
|| mach == bfd_mach_h8300sxn)
disassemble = print_insn_h8300s;
else
disassemble = print_insn_h8300;
which is the same as what gdb/h8300-tdpe.c does,
switch (info.bfd_arch_info->mach)
{
case bfd_mach_h8300:
...
set_gdbarch_print_insn (gdbarch, print_insn_h8300);
case bfd_mach_h8300h:
case bfd_mach_h8300hn:
...
set_gdbarch_print_insn (gdbarch, print_insn_h8300h);
case bfd_mach_h8300s:
case bfd_mach_h8300sn:
...
set_gdbarch_print_insn (gdbarch, print_insn_h8300s);
so we can leave disassble.c:disassembler doing the selection.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* h8300-tdep.c (h8300_gdbarch_init): Don't call
set_gdbarch_print_insn.
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This patch changes GDB to use disassembler selected by opcodes in
default, so that we don't have to duplicate the selection logic again
in GDB side. For example, gdb/score-tdep.c has
static int
score_print_insn (bfd_vma memaddr, struct disassemble_info *info)
{
if (info->endian == BFD_ENDIAN_BIG)
return print_insn_big_score (memaddr, info);
else
return print_insn_little_score (memaddr, info);
}
and opcodes/disassemble.c has the same logic,
case bfd_arch_score:
if (big)
disassemble = print_insn_big_score;
else
disassemble = print_insn_little_score;
This patch removes the logic in GDB and calls
opcodes/disassemble.c:disassembler in default to select disassembler.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* alpha-tdep.c (alpha_gdbarch_init): Don't call
set_gdbarch_print_insn.
* arc-tdep.c (arc_gdbarch_init): Likewise.
* arch-utils.c: include dis-asm.h.
(default_print_insn): New function.
* arch-utils.h (default_print_insn): Declare.
* avr-tdep.c (avr_gdbarch_init): Don't call set_gdbarch_print_insn.
* bfin-tdep.c (bfin_gdbarch_init): Likewise.
* cris-tdep.c (cris_delayed_get_disassembler): Remove.
(cris_gdbarch_init): Don't call set_gdbarch_print_insn.
* frv-tdep.c (frv_gdbarch_init): Likewise.
* ft32-tdep.c (ft32_gdbarch_init): Likewise.
* gdbarch.sh (print_insn): Use default_print_insn.
* gdbarch.c: Regenerated.
* hppa-tdep.c (hppa_gdbarch_init): Likewise.
* iq2000-tdep.c (iq2000_gdbarch_init): Likewise.
* lm32-tdep.c (lm32_gdbarch_init): Likewise.
* m32c-tdep.c (m32c_gdbarch_init): Likewise.
* m32r-tdep.c (m32r_gdbarch_init): Likewise.
* m68hc11-tdep.c (gdb_print_insn_m68hc11): Remove.
(m68hc11_gdbarch_init): Don't call set_gdbarch_print_insn.
* m68k-tdep.c (m68k_gdbarch_init): Likewise.
* m88k-tdep.c (m88k_gdbarch_init): Likewise.
* microblaze-tdep.c (microblaze_gdbarch_init): Likewise.
* mn10300-tdep.c (mn10300_gdbarch_init): Likewise.
* moxie-tdep.c (moxie_gdbarch_init): Likewise.
* msp430-tdep.c (msp430_gdbarch_init): Likewise.
* mt-tdep.c (mt_gdbarch_init): Likewise.
* nds32-tdep.c (nds32_gdbarch_init): Likewise.
* nios2-tdep.c (nios2_print_insn): Remove.
(nios2_gdbarch_init): Don't call set_gdbarch_print_insn.
* rx-tdep.c (rx_gdbarch_init): Likewise.
* s390-linux-tdep.c (s390_gdbarch_init): Likewise.
* score-tdep.c (score_print_insn): Remove.
(score_gdbarch_init): Don't call set_gdbarch_print_insn.
* sh-tdep.c (sh_gdbarch_init): Likewise.
* sh64-tdep.c (sh64_gdbarch_init): Likewise.
* sparc-tdep.c (sparc32_gdbarch_init): Likewise.
* tic6x-tdep.c (tic6x_print_insn): Remove.
(tic6x_gdbarch_init): Don't call set_gdbarch_print_insn.
* tilegx-tdep.c (tilegx_gdbarch_init): Likewise.
* v850-tdep.c (v850_gdbarch_init): Likewise.
* vax-tdep.c (vax_gdbarch_init): Likewise.
* xstormy16-tdep.c (xstormy16_gdbarch_init): Likewise.
* xtensa-tdep.c (xtensa_gdbarch_init): Likewise.
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Nowadays, opcodes/disassemble.c:disassembler selects the proper
disassembler according to ABFD only. However, it actually
selects disassemblers according to arch, mach, endianess, and
abfd. This patch adds them to the parameters of disassembler,
so that its caller can still select disassemblers in case that
abfd is NULL (a typical case in GDB).
There isn't any functionality change.
binutils:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* objdump.c (disassemble_data): Caller update.
include:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (disassembler): Update declaration.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* disassemble.c (disassembler): Add arguments a, big and mach.
Use them.
sim/common:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* sim-trace.c (trace_disasm): Caller update.
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gdb/ChangeLog:
* mips-fbsd-tdep.c (MIPS_PC_REGNUM): Remove.
(MIPS_FP0_REGNUM): Remove.
(MIPS_FSR_REGNUM): Remove.
(mips_fbsd_supply_fpregs): Use mips_regnum.
(mips_fbsd_supply_gregs): Likewise.
(mips_fbsd_collect_fpregs): Likewise.
(mips_fbsd_collect_gregs): Likewise.
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Compare against the "raw" PC register number instead of the cooked
register number when determining if a register was handled by
PT_GETREGS. Previously the register fetch/store operations only tried
PT_GETREGS to fetch any individual register. The result was that
fetching or storing an individual register not covered by PT_GETREGS
(such as floating point registers) did not work.
While here, remove an early exit to simplify the code flow from the
PT_GETREGS / PT_SETREGS case, and add a getfpregs_supplies similar to
getregs_supplies to describe the registers supplied by PT_GETFPREGS
and PT_SETFPREGS.
gdb/ChangeLog:
* mips-fbsd-nat.c (getregs_supplies): Fix upper bound comparison.
(getpfpregs_supplies): New function.
(mips_fbsd_fetch_inferior_registers): Remove early exit and use
getfpregs_supplies.
(mips_fbsd_store_inferior_registers): Likewise.
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* gas/testsuite/gas/i386/notrackbad.l: Updated for non-ELF
targets.
* gas/testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
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PR 21503
* options.h: Add --emit-stub-syms option.
* powerpc.cc (object_id): New.
(Powerpc_relobj): Add uniq_ and accessor. Sort variables for
better packing.
(Powerpc_dynobj): Sort variables for better packing.
(Target_powerpc::define_local): New function.
(Target_powerpc::group_sections): Pass stub table size to
Stub_table constructor.
(Target_powerpc::do_relax): Define stub and glink symbols.
(Stub_table): Add uniq_ variable, and id param to constructor.
(Stub_table::Plt_stub_ent): Add indx_ variable.
(Stub_table::Branch_stub_entries): Move typedef earlier.
(Stub_table::branch_stub_size): Replace "to" parameter with a
Branch_stub_entries iterator.
(Stub_table::add_long_branch_entry): Adjust to suit.
(Stub_table::add_plt_call_entry): Set indx_.
(Stub_table::define_stub_syms): New function.
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gas/
2017-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (md_apply_fix): Use as_bad_where.
(assemble_insn): Use as_bad.
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bfd/
2017-05-23 Dilian Palauzov <git-dpa@aegee.org>
* elf32-arc.c (arc_elf_merge_attributes): Add fall through
comments.
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It is required to parse instructions like ldb.x.a.di.
include/
2017-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (MAX_INSN_FLGS): Update to 4.
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Add mention of the vMustReplyEmpty to the remote serial protocol
documentation. It is important that this packet be treated in the same
fashion as any other unknown 'v' packet, and I have tried to reflect
this in the description of the packet, it is not simply the case that we
_must_ return the empty string for this packet.
As the intention is that we should treat this packet as unknown then an
argument could be made that we should not document it, however, for
someone implementing a gdbserver from scratch, seeing an undocumented
packet arrive from gdb is confusing, and will probably cause them to
have to read the code in order to check how this packet should be
handled, which is not ideal.
gdb/doc/ChangeLog:
* gdb.texinfo (Packets): Document vMustReplyEmpty packet.
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For register indirect branches, NOTRACK prefix (0x3e), which is also
the DS segment register prefix, can be used to ignore the CET indirect
branch track.
gas/
* config/tc-i386.c (REX_PREFIX): Changed to 7.
(NOTRACK_PREFIX): New.
(MAX_PREFIXES): Changed to 8.
(_i386_insn): Add notrack_prefix.
(PREFIX_GROUP): Add PREFIX_DS.
(add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE.
(md_assemble): Check if NOTRACK prefix is supported.
(parse_insn): Set notrack_prefix and issue an error for
other prefixes after NOTRACK prefix.
* testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix.
* testsuite/gas/i386/notrack-intel.d: New file.
* testsuite/gas/i386/notrack.d: Likewise.
* testsuite/gas/i386/notrack.s: Likewise.
* testsuite/gas/i386/notrackbad.l: Likewise.
* testsuite/gas/i386/notrackbad.s: Likewise.
* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.s: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
include/
* include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New.
opcodes/
* i386-dis.c (NOTRACK_Fixup): New.
(NOTRACK): Likewise.
(NOTRACK_PREFIX): Likewise.
(last_active_prefix): Likewise.
(reg_table): Use NOTRACK on indirect call and jmp.
(ckprefix): Set last_active_prefix.
(prefix_name): Return "notrack" for NOTRACK_PREFIX.
* i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
* i386-opc.h (NoTrackPrefixOk): New.
(i386_opcode_modifier): Add notrackprefixok.
* i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
Add notrack.
* i386-tbl.h: Regenerated.
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* elf64-x86-64.c (elf_x86_64_link_setup_gnu_properties): Use
dynobj instead of htab->elf.dynobj.
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This patch allows AArch64 LD defaulting to ILP32 if it is configured with
aarch64*-linux-gnu_ilp32.
ld/
* configure.tgt: Set "targ_emul" to "aarch64linux32b" for
aarch64_be-*-linux-gnu_ilp32. Set "targ_emul" to "aarch64linux32" for
aarch64-*-linux-gnu_ilp32.
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This patch allows AArch64 GAS defaulting to ILP32 if it is configured with
aarch64*-linux-gnu_ilp32.
"md_after_parse_args" is implemented to update ABI into ILP32 if DEFAULT_ARCH is
"aarch64:32".
gas/
* configure.tgt: Set "arch" to "aarch64" if ${cpu} equals "aarch64".
Recognize the new triplet name aarch64*-linux-gnu_ilp32.
* configure.ac: Output DEFAULT_ARCH macro for AArch64.
* configure: Regenerate.
* config/tc-aarch64.h (aarch64_after_parse_args): New declaration.
(md_after_parse_args): New define.
* config/tc-aarch64.c (aarch64_abi_type): New enumeration
AARCH64_ABI_NONE.
(DEFAULT_ARCH): New define.
(aarch64_abi): Set default value to AARCH64_ABI_NONE.
(aarch64_after_parse_args): New function.
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