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2024-07-10x86-64: Skip -z mark-plt tests on MUSLH.J. Lu1-0/+7
Skip -z mark-plt tests, which are specific to glibc, on MUSL. PR ld/31970 * ld/testsuite/ld-x86-64/x86-64.exp: Skip -z mark-plt tests on MUSL. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-07-10RISC-V:[gprofng] Minimal support gprofng for riscv.Yixuan Chen19-8/+99
ChangeLog: Add target riscv to --enable-gprofng. 2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn> * configure: Add riscv. * configure.ac: Add riscv. gprofng/ChangeLog: Minimal support gprofng for riscv. 2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn> * gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon. (defined): Add riscv. * gprofng/common/cpuid.c (defined): Add risc-v hwprobe. * gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv. (defined): Add riscv. (ARCH_RISCV): Add riscv. * gprofng/common/hwc_cpus.h: Add RISC-V vendor. * gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination. * gprofng/configure: Add riscv. * gprofng/configure.ac: Add riscv. * gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register. (CONTEXT_PC): Add RISC-V register. (CONTEXT_FP): Add RISC-V register. (CONTEXT_SP): Add RISC-V register. (SETFUNCTIONCONTEXT): * gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition. * gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V. * gprofng/libcollector/unwind.c (ARCH): Add RISC-V register. (GET_PC): Add RISC-V register. (GET_SP): Add RISC-V register. (GET_FP): Add RISC-V register. (FILL_CONTEXT): * gprofng/src/DbeSession.cc (ARCH): Add RISC-V. * gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V. * gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V. * gprofng/src/checks.cc (ARCH): Add RISC-V. * gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency. (read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content. * gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.
2024-07-10Add support for a .base64 pseudo-op to gasNick Clifton10-0/+398
PR 31964
2024-07-10libsframe: remove runstatedir in Makefile.inClément Chigot1-1/+0
The regeneration was made with Ubuntu automake which has this runstatedir additional variable, compared to the usual automake.
2024-07-10libsframe: accept --target configure optionClément Chigot3-81/+138
Libsframe was missing AC_CANONICAL_TARGET, meaning that --target was ignored. This could prevent libsframe.a to be installed in some cases, the host fetching its canonical value while the target isn't. Both having a different value, INSTALL_LIBBFD would be false.
2024-07-10Automatic date update in version.inGDB Administrator1-1/+1
2024-07-09elf: Add glibc version dependency only if neededH.J. Lu1-9/+23
There is no need to add a needed glibc version if the glibc base version includes the needed glibc version. PR ld/31966 * elflink.c (elf_link_add_glibc_verneed): Add glibc_minor_base. Skip if the glibc base version includes the needed glibc version. (_bfd_elf_link_add_glibc_version_dependency): Initialize glibc_minor_base to INT_MAX and pass it to elf_link_add_glibc_verneed. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-07-09gprofng: add hardware counters for Intel Ice Lake processorVladimir Mezentsev8-19/+1210
gprofng/ChangeLog 2024-07-07 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>. * common/hwc_cpus.h: New constant for Intel Ice Lake processor. * common/hwcdrv.c: Add a new argument to hwcfuncs_get_x86_eventsel. Set config1 in perf_event_attr. Remove the use of memset. * common/core_pcbe.c (core_pcbe_get_eventnum): Return 0. * common/hwcentry.h: Add config1. * src/collctrl.cc (Coll_Ctrl::build_data_desc):Set config1. * common/hwcfuncs.c (process_data_descriptor): Set config1. * common/hwctable.c: Add the hwc table for Intel Ice Lake processor. * src/hwc_intel_icelake.h: New file.
2024-07-09doc: sframe: add appendix for generating stack tracesIndu Bhagat1-0/+84
Add an appendix to provide a rough outline to show how to generate stack traces using the SFrame format. Such content should hopefully aid the reader assimmilate the information in the specification. libsframe/ * doc/sframe-spec.texi: Add new appendix.
2024-07-09include: sframe: update code comments around SFrame FRE stack offsetsIndu Bhagat1-10/+12
This also amends the incorrect comment: offset3 (intrepreted as FP = CFA + offset2) If RA tracking is enabled, the offset to recover FP is at the third index. The SFrame format (V2) has assumption that if FP is saved on stack, RA must have been saved as well. This is true for the currently supported arch Aarch64. For AMD64, RA tracking per SFrame FRE is not necessary. In future, when extending support for more architectures, this will likely need to be revisited. include/ * sframe.h: Make the comments clearer by enumerating what happens per-ABI.
2024-07-09doc: sframe: segregate the ABI/arch-specific componentsIndu Bhagat1-28/+110
The recipe to interpret the SFrame FRE stack offsets is ABI/arch-specific. Although, there is other information in the specification that is ABI-specific (like pauth_key usage in AArch64), those pieces of information are now assimmilated in the SFrame specification in a way that it is fairly difficult to carve then out into a ABI/arch-specific section without confusing the readers. For future though, the specification must strive to keep the generic parts and ABI/arch-specific parts clearly laid out in separate sections. libsframe/ * doc/sframe-spec.texi: Reorder and adapt the contents.
2024-07-09LTO: Properly check wrapper symbolH.J. Lu6-8/+50
Add wrapper_symbol to bfd_link_hash_entry and set it to true for wrapper symbol. Set wrap_status to wrapper if wrapper_symbol is true in LTO. Note: Calling unwrap_hash_lookup to check for the wrapper symbol works only when there is a definition for the wrapped symbol since references to the wrapped symbol have been redirected to the wrapper symbol. bfd/ PR ld/31956 * linker.c (bfd_wrapped_link_hash_lookup): Set wrapper_symbol for wrapper symbol. include/ PR ld/31956 * bfdlink.h (bfd_link_hash_entry): Add wrapper_symbol. ld/ PR ld/31956 * plugin.c (get_symbols): Set wrap_status to wrapper if wrapper_symbol is set. * testsuite/ld-plugin/lto.exp: Run PR ld/31956 tests. * testsuite/ld-plugin/pr31956a.c: New file. * testsuite/ld-plugin/pr31956b.c: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-07-09Automatic date update in version.inGDB Administrator1-1/+1
2024-07-08aarch64: Add support for sve2p1 pmov instruction.srinath13-224/+766
This patch adds support for followign SVE2p1 instruction, spec is available here [1]. 1. PMOV (to vector) 2. PMOV (to predicate) Both pmov (to vector) and pmov (to predicate) have destination scalable vector register and source scalable vector register respectively as an operand with no suffix and optional index. To handle this case we have added 8 new operands in this patch. AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */ AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */ AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */ AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */ AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */ AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */ AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */ AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */ Since the index of the <Zd> operand is optional, the index part is dropped in disassembly in both the cases of "no index" or "zero index". As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D PMOV <Pn>.D, <Zd>{[<imm>]} Example1: Assembly: pmov z5[0], p6.d Disassembly: pmov z5, p6.d Assembly: pmov z5, p6.d Disassembly: pmov z5, p6.d Example2: Assembly: pmov p4.b, z5[0] Disassembly: pmov p4.b, z5 Assembly: pmov p4.b, z5 Disassembly: pmov p4.b, z5 [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 tbxq instruction.Srinath Parvathaneni7-160/+207
This patch adds support for SVE2p1 "tbxq" instruction, spec is available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 zipq[1-2] instructions.Srinath Parvathaneni7-162/+256
This patch adds support for SVE2p1 "zipq1" and "zipq2" instructions, spec is available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 uzpq[1-2] instructions.Srinath Parvathaneni7-153/+247
This patch adds support for SVE2p1 "uzpq1" and "uzpq2" instructions, spec is available here [1] [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 tblq instruction.Srinath Parvathaneni7-175/+240
This patch adds support for SVE2p1 "tblq" instruction, spec is available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08aarch64: Add support for sve2p1 orqv instruction.Srinath Parvathaneni7-152/+228
This patch adds support for SVE2p1 "orqv" instruction, spec available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08Automatic date update in version.inGDB Administrator1-1/+1
2024-07-07Automatic date update in version.inGDB Administrator1-1/+1
2024-07-06Re: LoongArch: Add DT_RELR supportAlan Modra1-2/+2
Fix commit d89ecf33ab testsuite breakage. * testsuite/lib/binutils-common.exp (supports_dt_relr): Correct.
2024-07-06objcopy bfd_map_over_sections and global statusAlan Modra2-144/+140
This patch started life as a relatively simple change to fix some unimportant objcopy memory leaks, but expanded into a larger patch when I was annoyed by the awkwardness of passing data when using bfd_map_over_sections. A simple loop over sections is much more convenient, and we really don't need the abstraction layer. Sections in a list isn't going to disappear any time soon. The patch also removes use of the global "status" variable by all but the top-level functions called from main. * objcopy.c (filter_symbols): Return success as a bool. Pass symcount as a pointer, updated on return. (merge_gnu_build_notes): Similarly return a bool and add newsize param with updated smaller section size. (setup_bfd_headers): Return bool success rather than setting "status" on failure. (setup_section): Likewise. (copy_relocations_in_section, copy_section): Likewise, and adjust params. (mark_symbols_used_in_relocations): Likewise, and free memory on failure path. Don't call bfd_fatal. (get_sections): Delete function. (copy_object): Don't use bfd_map_over_sections, instead use a loop allowing easy detection of failure status. Free memory on error paths. (copy_archive): Return bool success rather than setting "status" on failure. (copy_file): Set "status" here. * testsuite/binutils-all/strip-13.d: Adjust to suit.
2024-07-06Automatic date update in version.inGDB Administrator1-1/+1
2024-07-05aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)Matthieu Longo3-0/+11
This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
2024-07-05aarch64: add STEP2 feature and its associated registersMatthieu Longo5-0/+13
AArch64 defines new registers for the feature step2 (Enhanced Software Step Extension). step2 is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
2024-07-05aarch64: add SPMU2 feature and its associated registersMatthieu Longo5-0/+13
AArch64 defines new registers for the feature spmu2 (System Performance Monitors Extension version 2). spmu2 is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
2024-07-05aarch64: add E3DSE feature and its associated registersMatthieu Longo6-1/+39
AArch64 defines new registers for the feature e3dse (Delegated SError exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
2024-07-05x86-64: Fix support for APX NF TLS IE with 2 operandsLingling Kong1-3/+2
Added the restriction in assemble for APX TLS IE that the destination can only be a register. gas/ * config/tc-i386.c (md_assemble): Added stricter restrictions for APX TLS IE.
2024-07-05RISC-V: avoid use of match_opcode() in riscv_insn_types[]Jan Beulich1-102/+102
As of 27b33966b18e ("RISC-V: disallow x0 with certain macro-insns") the .match_func field may be NULL for entries used for assembly only, which is the case for the entire table. With .match and .mask both zero the function would only ever succeed anyway. Save almost a hundred base relocations in the final executable by using NULL instead.
2024-07-05aarch64: fix build with old glibcJan Beulich1-3/+3
As was pointed out several times before, old glibc declares index(), resulting in warnings from -Wshadow, in turn failing the build due to -Werror.
2024-07-05LoongArch: Add DT_RELR testsXi Ruoyao19-0/+485
Most tests are ported from AArch64. The relr-addend test is added to make sure the addend (link-time address) is correctly written into the relocated section. Doing so is not strictly needed for RELA, but strictly needed for RELR). Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05LoongArch: Add DT_RELR supportXi Ruoyao3-4/+486
The logic is same as a71d87680110 ("aarch64: Add DT_RELR support"). As LoongArch does not have -z dynamic-undefined-weak, we don't need to consider UNDEFWEAK_NO_DYNAMIC_RELOC. The linker relaxation adds another layer of complexity. When we delete bytes in a section during relaxation, we need to fix up the offset in the to-be-packed relative relocations against this section. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05LoongArch: Make protected function symbols local for -sharedXi Ruoyao5-21/+81
On LoongArch there is no reason to treat STV_PROTECTED STT_FUNC symbols as preemptible. See the comment above LARCH_REF_LOCAL for detailed explanation. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05LoongArch: Fix bad reloc with mixed visibility ifunc symbols in shared librariesXi Ruoyao4-12/+140
With a simple test case: .globl ifunc .globl ifunc_hidden .hidden ifunc_hidden .type ifunc, %gnu_indirect_function .type ifunc_hidden, %gnu_indirect_function .text .align 2 ifunc: ret ifunc_hidden: ret test: bl ifunc bl ifunc_hidden "ld -shared" produces a shared object with one R_LARCH_NONE (instead of R_LARCH_JUMP_SLOT as we expect) to relocate the GOT entry of "ifunc". It's because the indices in .plt and .rela.plt mismatches for STV_DEFAULT STT_IFUNC symbols when another PLT entry exists for a STV_HIDDEN STT_IFUNC symbol, and such a mismatch breaks the logic of loongarch_elf_finish_dynamic_symbol. Fix the issue by reordering .plt so the indices no longer mismatch. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05LoongArch: Reject R_LARCH_32 from becoming a runtime reloc in ELFCLASS64Xi Ruoyao4-2/+36
We were converting R_LARCH_32 to R_LARCH_RELATIVE for ELFCLASS64: $ cat t.s .data x: .4byte x .4byte 0xdeadbeef $ as/as-new t.s -o t.o $ ld/ld-new -shared t.o $ objdump -R a.out: file format elf64-loongarch DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE 00000000000001a8 R_LARCH_RELATIVE *ABS*+0x00000000000001a8 But this is just wrong: at runtime the dynamic linker will run *(uintptr *)&x += load_address, clobbering the next 4 bytes of data ("0xdeadbeef" in the example). If we keep the R_LARCH_32 reloc as-is in ELFCLASS64, it'll be rejected by the Glibc dynamic linker anyway. And it does not make too much sense to modify Glibc to support it. So we can just reject it like x86_64: relocation R_X86_64_32 against `.data' can not be used when making a shared object; recompile with -fPIC or RISC-V: relocation R_RISCV_32 against non-absolute symbol `a local symbol' can not be used in RV64 when making a shared object Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-07-05x86: Correct position of ".s" for CCMPcc in disassemblerCui, Lili4-5/+24
Added new macro %SW to CCMPcc to print ".s" after the mnemonic. Before: ccmpbl {dfv=}.s %edx,%eax After: ccmpbl.s {dfv=} %edx,%eax gas/ChangeLog: * testsuite/gas/i386/x86-64-pseudos-apx.d: Add tests for CCMPcc. * testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Added %SW for CCMPcc swap operands. * i386-dis.c (struct dis386): Added %SW. (putop): Handle %SW.
2024-07-05x86: Add {load}/{store} tests for apx instructions.Cui, Lili3-0/+204
gas/ChangeLog: * testsuite/gas/i386/x86-64.exp: Add {load}/{store} tests for apx instructions. * testsuite/gas/i386/x86-64-pseudos-apx.d: New test. * testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto.
2024-07-05Automatic date update in version.inGDB Administrator1-1/+1
2024-07-04RISC-V: Fix BFD_RELOC_RISCV_PCREL_LO12_S patch issueSun Sunny4-40/+114
In commit dff565fcca8137954d6ad571ef39f6aec5c0429c, the fixups for PCREL_LO12_I and PCREL_LO12_S were mixed, so the "IMM" field were applied to incorrect position, this caused incorrect src registers to be encoded. gas/ * config/tc-riscv.c (md_apply_fix): Fix PCREL_LO12_S issue. * testsuite/gas/riscv/ixup-local.s: Updated for PCREL_LO12_S cases. * testsuite/gas/riscv/fixup-local-relax.d: Likewise. * testsuite/gas/riscv/fixup-local-norelax.d: Likewise. Signed-off-by: Jianwei Sun <sunny.sun@corelabtech.com>
2024-07-04RISC-V: hash with segment id and pcrel_hi address while recording pcrel_hiLifang Xia1-7/+17
When the same address across different segments (sections) needs to be recorded, it will overwrite the slot, leading to a memory leak. To ensure uniqueness, the segment (section) ID needs to be included in the hash key calculation. gas/ * config/tc-riscv.c (riscv_pcrel_hi_fixup): New "const asection *sec". (riscv_pcrel_fixup_hash): make sec->id and e->adrsess as the hash key. (riscv_pcrel_fixup_eq): Check sec->id at first. (riscv_record_pcrel_fixup): New member "sec". (md_apply_fix) <case BFD_RELOC_RISCV_PCREL_HI20>: Likewise. (md_apply_fix) <case BFD_RELOC_RISCV_PCREL_LO12_I>: Likewise.
2024-07-04mve: Fix encoding for vcvt[bt] single-half float conversion instructionsAndre Vieira2-72/+81
The encoding was previously not taking into account that the Quad vector registers were being encoded using their Q-register numbers rather than their D-register equivalent (multiply by 2). gas/ * config/tc-arm.c (do_neon_cvttb_1): Use Q-register vector number rather than their D-register equivalent. gas/testsuite/ * gas/arm/mve-vcvt-3.d: Correct expected values in test.
2024-07-04gas: Validate SFrame RA tracking and fixed RA offsetJens Remus1-5/+9
Verify all architectures participating in SFrame generation do define the mandatory SFrame return address (RA) tracking predicate function sframe_ra_tracking_p. Do so by explicitly not testing for the macro SFRAME_FRE_RA_TRACKING as otherwise required. Verify that architectures not using SFrame RA tracking specify a valid fixed RA offset. gas/ * gen-sframe.c (output_sframe_internal): Validate SFrame RA tracking and fixed RA offset. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Test predicate whether SFrame RA tracking is usedJens Remus1-2/+4
The existence of the macro SFRAME_FRE_RA_TRACKING only ensures the existence of the macro SFRAME_CFA_RA_REG and the predicate function sframe_ra_tracking_p. It does not indicate whether SFrame RA tracking is actually used. Test the return value of the SFrame RA tracking predicate function sframe_ra_tracking_p to determine whether RA tracking is used. This aligns the logic in functions get_fre_num_offsets and output_sframe_row_entry to the one used in all other places. gas/ * gen-sframe.c (get_fre_num_offsets, output_sframe_row_entry): Test predicate to determine whether SFrame RA tracking is used. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Don't skip SFrame FDE if .cfi_register specifies SP registerJens Remus1-3/+6
Neither ".cfi_offset SP, <offset>", ".cfi_register SP, <regno>", nor ".cfi_val_offset SP, <offset>" alter the tracking information to recover the stack pointer (SP). Doing so would need an explicit .cfi_def_cfa, which SFrame tracks. The stack pointer (SP) register contents on entry can be reconstructed from the SFrame CFA tracking information using information from the current and initial SFrame FREs of the SFrame FDE: 1. Compute CFA from the current CFA base register (SP or FP) and CFA offset from the SFrame CFA tracking information from the SFrame FRE for the current instruction address: CFA = <current_base_reg> + <current_cfa_offset> 2. Compute SP from the current CFA and the CFA offset from the SFrame CFA tracking information from the initial SFrame FRE of the FDE: SP = CFA - <initial_cfa_offset> While at it add comments to the processing of .cfi_offset and .cfi_val_offset that the SP can be reconstructed from the CFA tracking information. gas/ * gen-sframe.c (sframe_xlate_do_register): Do not skip SFrame FDE if .cfi_register specifies SP register. (sframe_xlate_do_offset,sframe_xlate_do_val_offset): Add comment that this is likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Don't skip SFrame FDE if .cfi_register specifies RA w/o trackingJens Remus1-1/+1
Do not skip SFrame FDE if .cfi_register specifies RA register without RA tracking being actually used. Without RA tracking the register contents can always be restored from the stack using the fixed RA offset from CFA. gas/ * gen-sframe.c (sframe_xlate_do_register): Do not skip SFrame FDE if .cfi_register specifies RA register without RA tracking being used. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Skip SFrame FDE if .cfi_window_saveJens Remus1-3/+22
CFI opcode DW_CFA_AARCH64_negate_ra_state is multiplexed with DW_CFA_GNU_window_save. Process DW_CFA_AARCH64_negate_ra_state on AArch64. Skip generation of SFrame FDE otherwise with the following warning message: skipping SFrame FDE; .cfi_window_save gas/ * gen-sframe.c: Skip SFrame FDE if .cfi_window_save. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Skip SFrame FDE if FP without RA on stackJens Remus1-2/+19
The SFrame format cannot represent the frame pointer (FP) being saved on the stack without the return address (RA) also being saved on the stack, if RA tracking is used. A SFrame FDE is followed by 1-3 offsets with the following information: Without RA tracking: 1. Offset from base pointer (SP or FP) to locate the CFA 2. Optional: Offset to CFA to restore the frame pointer (FP) With RA tracking: 1. Offset from base pointer (SP or FP) to locate the CFA 2. Optional: Offset to CFA to restore the return address (RA) 3. Optional: Offset to CFA to restore the frame pointer (FP) When RA tracking is used and a FDE is followed by two offsets the SFrame format does not provide any information to distinguish whether the second offset is the RA or FP offset. SFrame assumes the offset to be the RA offset, which may be wrong. Therefore skip generation of SFrame FDE information and print the following warning, if RA tracking is used and the FP is saved on the stack without the RA being saved as well: skipping SFrame FDE; FP without RA on stack gas/ * gen-sframe.c (sframe_do_fde): Skip SFrame FDE if FP without RA on stack, as the SFrame format cannot represent this case. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: User readable warnings if SFrame FDE is not generatedJens Remus5-28/+72
The following generic warning message, which is printed whenever the assembler skips generation of SFrame FDE, is not very helpful for the user: skipping SFrame FDE; CFI insn <name> (0x<hexval>) Whenever possible print meaningful warning messages, when the assembler skips generation of SFrame FDE: - skipping SFrame FDE; non-SP/FP register <regno> in .cfi_def_cfa - skipping SFrame FDE; non-SP/FP register <regno> in .cfi_def_cfa_register - skipping SFrame FDE; .cfi_def_cfa_offset without CFA base register in effect - skipping SFrame FDE; {FP|RA} register <regno> in .cfi_val_offset - skipping SFrame FDE; {SP|FP|RA} register <regno> in in .cfi_register - skipping SFrame FDE; .cfi_remember_state without prior SFrame FRE state - skipping SFrame FDE; non-default RA register <regno> gas/ * gen-sframe.h (SFRAME_FRE_BASE_REG_INVAL): New macro for invalid SFrame FRE CFA base register value of -1. * gen-sframe.c: User readable warnings if SFrame FDE is not generated. gas/testsuite/ * gas/cfi-sframe/common-empty-1.d: Update generic SFrame test case to updated warning message texts. * gas/cfi-sframe/common-empty-2.d: Likewise. * gas/cfi-sframe/common-empty-3.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04gas: Refactor SFrame CFI opcode DW_CFA_register processingJens Remus1-11/+26
Refactor SFrame processing of CFI opcode DW_CFA_register into a separate function. This harmonizes the CFI opcode processing. While at it reword the comment on CFI opcodes that are not processed. This is a purely mechanical change. gas/ * gen-sframe.c (sframe_do_cfi_insn, sframe_xlate_do_register): Refactor SFrame CFI opcode DW_CFA_register processing. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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