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Test the int/float instructions of LA64.
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Test the LSX/LASX instructions. Only LA64 supports
these instructions.
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Test the LBT/LVZ instructions. Only LA64 supports
these instructions.
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Test the alias instructions.
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There is an assertion error "gdb_assert (n < tdesc->reg_defs.size ())"
in find_register_by_number() when gdb connects to gdbserver, this
is because the value of LOONGARCH_LINUX_NUM_GREGSET (45, which contains
10 reserved regs) is different with the number of regs (35, which not
contains 10 reserved regs) in file gdb/features/loongarch/base64.xml.
Add a new macro LOONGARCH_USED_NUM_GREGSET which is defined as 35 to
keep consistent with the gdb/features/loongarch/base64.xml, and then
define LOONGARCH_FIRST_FP_REGNUM as LOONGARCH_USED_NUM_GREGSET so that
all the reg numbers in regcache are consistent with tdesc reg numbers.
without this patch:
Execute on the target machine:
$ gdbserver 192.168.1.123:5678 ./test
Execute on the host machine:
$ gdb ./test
(gdb) target remote 192.168.1.123:5678
Output on the target machine:
Process ./test created; pid = 67683
Listening on port 5678
Remote debugging from host 192.168.1.136, port 6789
gdbserver/regcache.cc:205: A problem internal to GDBserver has been detected.
find_register_by_number: Assertion 'n < tdesc->reg_defs.size ()' failed.
Output on the host machine:
Remote debugging using 192.168.1.123:5678
Remote connection closed
Signed-off-by: Hui Li <lihui@loongson.cn>
Approved-By: John Baldwin <jhb@FreeBSD.org>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
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In a couple of spots, the TUI tries to center some text in the window.
Andrew noticed that the calculation is done strangely and the text
ends up somewhat to the left of center.
This patch fixes the problem.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31355
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ChangeLog:
* gdb/jit.c: Fix missing word in code comment.
Signed-off-by: Will Hawkins <hawkinsw@obs.cr>
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Provide expected operand type in s390-specific assembler operand parsing
error message:
"error: operand <operand-number>: missing <operand-type> operand"
With <operand-type> being one of:
- base register
- displacement
- [vector] index register
- length
- access register
- control register
- floating-point register
- general-purpose register
- vector register
- [un]signed number
gas/
* config/tc-s390.c: Provide missing operand type in error
message.
* testsuite/gas/s390/zarch-base-index-0-err.l: Update test case
result validation patterns to operand number in operand syntax
error messages.
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Prepend the operand number "operand %d:" to the s390-specific assembler
operand parsing warning and error messages.
While at it reword the custom operand out of range error message text to
be closer to the one used by as_bad_value_out_of_range(). Additionally
reword the invalid FPR pair warning message to make it nicer.
gas/
* config/tc-s390.c: Print operand number in error messages.
* testsuite/gas/s390/zarch-base-index-0-err.l: Update test case
verification patterns to accept syntax error messages now
containing the operand number.
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
* testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise.
* testsuite/gas/s390/zarch-z9-109-err.l: Likewise.
* testsuite/gas/s390/zarch-z900-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The base register operand B may be omitted in D(B) by coding D and in
D(L,B) by coding D(L). The index register operand X may be omitted in
D(X,B) by coding D(B) or explicitly omitted by coding D(,B). In both
cases the omitted base register operand value defaults to zero.
Allow to explicitly omit the base register operand B in D(X,B) and
D(L,B) by coding D(X,) and D(L,). Default the omitted base register
operand value to zero.
gas/
* config/tc-s390.c: Allow to explicitly omit the base register
operand in assembly.
* NEWS: Mention that the base register now may be omitted on
s390.
* gas/testsuite/gas/s390/zarch-base-index-0.s: Update test cases
for change to allow to explicitly omit the base register
operand in assembly.
* gas/testsuite/gas/s390/zarch-base-index-0.d: Likewise.
* gas/testsuite/gas/s390/zarch-base-index-0-err.s: Likewise.
* gas/testsuite/gas/s390/zarch-base-index-0-err.l: Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index.s: Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index-err.s:
Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index-err.l:
Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Base and index register 0 have no effect in address computation:
"A value of zero in the B [base] or X [index] field specifies that no
base or index is to be applied, and, thus, general register 0 cannot be
designated as containing a base address or index."
IBM z/Architecture Principles of Operation [1], chapter "Organization",
section "General Registers".
Index register 0 is omitted in the s390 disassembly. Base register 0 is
omitted in D(B), D(L,B) and D(X,B) - the latter only if the index
register is zero.
To make it more apparent print base register 0 as "0" instead of "%r0",
whenever it would still be printed in the disassembly.
[1]: IBM z/Architecture Principles of Operation, SA22-7832-13,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
opcodes/
* s390-dis.c: Print base register 0 as "0" in disassembly.
binutils/
* NEWS: Mention base register 0 now being printed as "0" in s390
disassembly.
gas/
* testsuite/gas/s390/zarch-base-index-0.d: Update test case
output verification patterns to accept "0" as base base
register due to disassembler output format change.
* gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Print a warning message when the register type of a specified register
name does not match with the operand's register type:
operand {#}: expected {access|control|floating-point|general|vector}
register name [as {base|index} register]
Introduce a s390-specific assembler option "warn-regtype-mismatch"
with the values "strict", "relaxed", and "no" as well as an option
"no-warn-regtype-mismatch" which control whether the assembler
performs register name type checks and generates above warning messages.
warn-regtype-mismatch=strict:
Perform strict register name type checks.
warn-regtype-mismatch=relaxed:
Perform relaxed register name type checks, which allow floating-point
register (FPR) names %f0 to %f15 to be specified as argument to vector
register (VR) operands and vector register (VR) names %v0 to %v15 to
be specified as argument to floating-point register (FPR) operands.
This is acceptable as the FPRs are embedded into the lower halves of
the VRs. Make "relaxed" the default, as GCC generates assembler code
using FPR and VR interchangeably, which would cause assembler warnings
to be generated with "strict".
warn-regtype-mismatch=no:
no-warn-regtype-mismatch:
Disable any register name type checks.
Tag .insn pseudo mnemonics as such, to skip register name type checks
on those. They need to be skipped, as there do not exist .insn pseudo
mnemonics for every possible operand register type combination. Keep
track of the currently parsed operand number to provide it as reference
in warning messages.
To verify that the introduction of this change does not unnecessarily
affect the compilation of existing code the GNU Binutils, GNU C Library,
and Linux Kernel have been build with the new assembler, verifying that
the assembler did not generate any of the new warning messages.
gas/
* config/tc-s390.c: Handle new assembler options
"[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate
parsed register expressions with register type. Keep track of
operand number being parsed. Print warning message in case of
register type mismatch between instruction operand and parsed
register expression.
* doc/as.texi: Document new s390-specific assembler options
"[no-]warn-regtype-mismatch[=strict|relaxed|no]".
* NEWS: Mention new s390-specific register name type checks and
related assembler option "warn-regtype-mismatch=strict|
relaxed|no".
* testsuite/gas/s390/s390.exp: Add test cases for new assembler
option "warn-regtype-mismatch={strict|relaxed}".
* testsuite/gas/s390/esa-g5.s: Fix register types in tests for
didbr, diebr, tbdr, and tbedr.
* testsuite/gas/s390/zarch-z13.s: Fix register types in tests
for vgef, vgeg, vscef, and vsceg.
* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s:
Tests for assembler option "warn-regtype-mismatch=strict".
* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l:
Likewise.
* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s:
Tests for assembler option "warn-regtype-mismatch=relaxed".
* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l:
Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update
test cases for assembler option "warn-regtype-mismatch"
defaulting to "relaxed".
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
include/
* opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add
instruction flag to tag .insn pseudo-mnemonics.
opcodes/
* s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as
such.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Reorder, reword, and complete the s390-specific option descriptions.
Align the formatting of s390-specific assembler options to that of the
general assembler options in "as --help".
While at it change a warning message to use the term "z/Architecture"
instead of the deprecated "esame" (ESA Modal Extensions or ESAME) one.
gas/
* config/tc-s390.c: Revise s390-specific assembler option
descriptions.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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gas/
* testsuite/gas/s390/s390.exp: Add test cases for s390-specific
assembler option "warn-areg-zero".
* testsuite/gas/s390/zarch-warn-areg-zero.s: Likewise.
* testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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While at it add comments to logic to omit base and/or index register 0
in s390 disassembly.
opcodes/
* s390-dis.c: Add comments related to omitting base and/or index
register 0 in disassembly.
gas/
* testsuite/gas/s390/s390.exp: Add test cases for base and/or
index register 0.
* testsuite/gas/s390/zarch-base-index-0.s: Add test cases for
base and/or index register 0.
* testsuite/gas/s390/zarch-base-index-0.d: Likewise.
* testsuite/gas/s390/zarch-base-index-0-err.s: Add error test
cases for base and/or index register 0.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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gas/
* config/tc-s390.c: Add comments to assembler operand parsing
logic.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Assemble the esa-g5 test case with -march=g5.
Assemble the zarch-z900 test case with -march=z900.
gas/
* testsuite/gas/s390/s390.exp: Assemble processor specific test
cases for their respective processor (-march=<processor>).
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The combination of an architecture size of 32 bits and z/Architecture
mode requires the highgprs flag to be set in the ELF output. It causes
the high-halves of the general purpose registers (GPRs) to be preserved
at run-time, so that the code can use 64-bit GPRs.
The architecture size of 32 bits can either be the default in case of
a default architecture name of "s390" or due to specification of the
option -m31 (to generate the 31-bit file format).
The z/Architecture mode can either be the default or due to
specification of the option -mzarch (to assemble for z/Architecture
mode). It can also be selected using the pseudo commands
".machinemode zarch" and ".machinemode zarch_nohighgprs". The latter
not causing the highgprs flag to be set.
The highgprs flag was only set when the following s390-specific
assembler options were given in the following specific order:
"-m31 -mzarch".
The highgprs flag was erroneously not set when:
- the order of above options was inverse (i.e. "-mzarch -m31"),
- the architecture mode defaulted to z/Architecture mode and
option "-m31" was specified,
- the architecture size defaulted to 32 bits due to a default
architecture name of "s390" and option -mzarch was specified,
- the architecture size defaulted to 32 bits and the architecture
mode defaulted to z/Architecture due to the specified processor
(e.g. "-march=z900" or follow-on processor).
Determine whether to set the highgprs flag in init_default_arch() after
having processed all assembler options in md_parse_option(). This
ensures the flag is set in all of the above cases it was erroneously not
set. Add test cases for highgprs flag, including ones that use
.machinemode to switch the architecture mode.
gas/
* config/tc-s390.c: Correct setting of highgprs flag in ELF
output.
* testsuite/gas/s390/s390.exp: Add test cases for highgprs
flag.
* testsuite/gas/s390/blank.s: Empty assembler source used in
test cases for "highgprs" flag.
* testsuite/gas/s390/esa-highgprs-0.d: Add test case for
highgprs flag.
* testsuite/gas/s390/zarch-highgprs-0.d: Likewise.
* testsuite/gas/s390/zarch-highgprs-1.d: Likewise.
* testsuite/gas/s390/esa-highgprs-machinemode-0.s: Add test case
for highgprs flag when using .machinemode to switch
architecture mode.
* testsuite/gas/s390/esa-highgprs-machinemode-0.d: Likewise.
* testsuite/gas/s390/esa-highgprs-machinemode-1.s: Likewise.
* testsuite/gas/s390/esa-highgprs-machinemode-1.d: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The base register operand B may optionally be omitted in D(B) by coding
D and in D(L,B) by coding D(L). The index register operand X may
optionally be omitted in D(X,B) by coding D(,B) or D(B). Both base and
index register operands may optionally be omitted in D(X,B) by coding D.
In any case the omitted base and/or index register operand value
defaults to zero.
When parsing an erroneously omitted length L operand in D(L,B) by coding
D(,B) the base register operand B was erroneously consumed as length
operand. When using a register name for the base register operand this
was detected and reported as error. But when not using a register name
the base register operand value was erroneously used as length operand
value.
Correct the parsing of an omitted optional base or index register to not
erroneously use the base register operand value as length, when
erroneously omitting the length operand.
While at it rename the variable used to remember whether the base or
index register operand was omitted to enhance code readability.
Additionally add test cases for the optional omission of base and/or
index register operands.
Example assembler source:
mvc 16(1,%r1),32(%r2)
mvc 16(1),32(%r2)
mvc 16(,1),32(%r2) # undetected syntax error
Disassembly of bad assembly without commit shows the base register
operand value was erroneously used as length operand value:
0: d2 00 10 10 20 20 mvc 16(1,%r1),32(%r2)
6: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2)
c: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2)
Assembler messages with commit:
3: Error: operand 1: missing operand
gas/
* config/tc-s390.c: Correct parsing of omitted base register.
* testsuite/gas/s390/s390.exp: Add test cases for omitted base
and/or index register.
* testsuite/gas/s390/zarch-omitted-base-index.s: Test cases for
omitted optional base or index register.
* testsuite/gas/s390/zarch-omitted-base-index.d: Likewise.
* testsuite/gas/s390/zarch-omitted-base-index-err.s: Test cases
for omitted base and/or index register.
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Do not consume any unexpected character including newline ('\n') when
detecting a syntax error when parsing an operand block with parenthesis.
This resolves the unfavorable assembler messages from the example below,
including consuming the newline at the end of the current statement and
reporting the next statement as junk.
While at it change the only pre-increment of the current instruction
string pointer into a post-increment to align with the other instances.
Example assembler source:
mvi 16(),32 # syntax error
a %r1,16(%r2 # syntax error
a %r1,16(%r2)
mvc 16(1,),32(%r2) # syntax error
mvc 16(1,%r1,32(%r2 # syntax error
Assembler messages without commit:
1: Error: bad expression
1: Error: syntax error; missing ')' after base register
1: Error: syntax error; expected ','
1: Error: junk at end of line: `32'
2: Error: syntax error; missing ')' after base register
2: Error: junk at end of line: `a %r1,16(%r2)'
4: Error: bad expression
4: Error: syntax error; missing ')' after base register
4: Error: syntax error; expected ','
4: Error: operand out of range (32 is not between 0 and 15)
4: Error: syntax error; missing ')' after base register
4: Error: junk at end of line: `%r2)'
5: Error: syntax error; missing ')' after base register
5: Error: syntax error; expected ','
5: Error: operand out of range (32 is not between 0 and 15)
5: Error: syntax error; missing ')' after base register
5: Error: junk at end of line: `%r2'
Assembler messages with commit:
1: Error: bad expression
1: Error: syntax error; missing ')' after base register
2: Error: syntax error; missing ')' after base register
4: Error: bad expression
4: Error: syntax error; missing ')' after base register
5: Error: syntax error; missing ')' after base register
5: Error: syntax error; missing ')' after base register
gas/
* config/tc-s390.c: Do not erroneously consume newline when
parsing an addressing operand with parentheses.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Report s390 assembler syntax errors as error instead of fatal error.
This allows the assembler to continue and potentially report further
syntax errors in the source. This should not cause syntax errors to
be erroneously accepted, as both error and fatal error cause the
assembler to return with a non-zero return code.
The following syntax errors are changed from fatal to error:
- invalid length field specified
- odd numbered general purpose register specified as register pair
- invalid floating point register pair. Valid fp register pair operands
are 0, 1, 4, 5, 8, 9, 12 or 13.
gas/
* config/tc-s390.c: Lower severity of assembler syntax errors
from fatal to error.
* testsuite/gas/s390/zarch-z9-109-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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opcodes/
* s390-mkopc.c: Use proper string lengths when parsing opcode
table flags.
Fixes: c5306fed7d4 ("s390: Support for jump visualization in disassembly")
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
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opcodes/
* s390-mkopc.c: Whitespace fixes in conditional branch flavor
descriptions.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
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Consumers can't know which execution mode is in effect for a certain
piece of code; they can only go from object file properties. Hence which
register numbers to encode ought to depend solely on object file type.
In tc_x86_frame_initial_instructions() do away with parsing a register
name: We have a symbolic constant already for the 64-bit case, and the
32-bit number isn't going to change either. Said constant's definition
needs moving, though, to be available also for non-ELF. While moving
also adjust the comment to clarify that it's applicable to 64-bit mode
only.
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... plus the SME part of B16B16. As per
https://sourceware.org/pipermail/binutils/2024-February/132408.html
SVE2.1 support is both incomplete and buggy. SME2.1 "support" goes as
far as a single instruction (a subset of movaz forms) only. The SME part
of B16B16 is entirely missing.
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These uniformly ignore EVEX.W, and hence what we emit ought to be
controllable by the command line option.
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While most logic in optimize_encoding() is already covering APX by way
of the earlier NDD->REX2 conversion, there's a remaining set of cases
which wants handling separately.
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In this case spaces 0f38 and 0f3a may not be put in place. To achieve
the intended effect, operand parsing (but not operand processing) needs
pulling ahead, so we know whether eGRP-s are in use.
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Even when an EVEX encoding is available, use of such a prefix ought to
be respected (resulting in an error) rather than ignored. As requested
during review already, introduce a new encoding enumerator to record use
of eGPR-s, and update state transitions accordingly.
The optimize_encoding() change also addresses an internal assembler
error that was previously raised when respective memory operands used
eGPR-s for addressing.
While this results in a change of diagnostic issued for VEX-encoded
insns, the new one is at least no worse than the prior one.
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Today I realized that while the .debug_names writer uses DW_FORM_udata
for the DIE offset, DW_FORM_ref_addr would be more appropriate here.
This patch makes this change.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31361
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Say why we even mention shared libraries here (ET_DYN), and clarify
symbol resolution. There are of course many other ways that PIEs
resemble PDEs more closely than shared libraries.
PR 19871
* ld.texi (-pie): Clarify.
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This patch copies some changes to the compile headers from GCC's
include/ directory. It is the gdb equivalent of the GCC commit
bc0e18a9 -- however, while that commit also necessarily touched
libcc1, this one of course does not.
Tested by rebuilding and also running the gdb.compile tests.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31397
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The assembler wrongly expects plain register name instead of
memory-form 2nd operand for gcsstr and gcssttr instructions.
This patch fixes the issue.
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When running test-case gdb.dap/pause.exp 100 times in a loop, it passes
100/100.
But if we remove the two "sleep 0.2" from the test-case, we run into
(copied from dap.log and edited for readability):
...
Traceback (most recent call last):
File "startup.py", line 251, in message
def message():
KeyboardInterrupt
Quit
...
This happens as follows.
CancellationHandler.cancel calls gdb.interrupt to cancel a request in flight.
The idea is that this interrupt triggers while in fn here in message (a nested
function of send_gdb_with_response):
...
def message():
try:
val = fn()
result_q.put(val)
except (Exception, KeyboardInterrupt) as e:
result_q.put(e)
...
but instead it triggers outside the try/except.
Fix this by:
- in CancellationHandler, renaming variable in_flight to in_flight_dap_thread,
and adding a variable in_flight_gdb_thread to be able to distinguish when
a request is in flight in the dap thread or the gdb thread.
- adding a wrapper Cancellable to to deal with cancelling the wrapped
event
- using Cancellable in send_gdb and send_gdb_with_response to wrap the posted
event
- in CancellationHandler.cancel, only call gdb.interrupt if
req == self.in_flight_gdb_thread.
This makes the test-case pass 100/100, also when adding the extra stressor of
"taskset -c 0", which makes the fail more likely without the patch.
Tested on aarch64-linux.
Approved-By: Tom Tromey <tom@tromey.com>
PR dap/31275
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31275
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Move functions send_gdb and send_gdb_with_response, as well as class Invoker
to server module.
Separated out to make the following patch easier to read.
Tested on aarch64-linux.
Approved-By: Tom Tromey <tom@tromey.com>
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Commit 92d48a1e4eac ("Add an arm-tls feature which includes the tpidruro
register from CP15.") introduced the org.gnu.gdb.arm.tls feature, which
adds the tpidruro register, and unconditionally enabled it in
aarch32_create_target_description.
In Linux, the tpidruro register isn't available via ptrace in the 32-bit
kernel but it is available for an aarch32 program running under an arm64
kernel via the ptrace compat interface. This isn't currently implemented
however, which causes GDB on arm-linux with 64-bit kernel to list the
register but show it as unavailable, as reported by Tom de Vries:
$ gdb -q -batch a.out -ex start -ex 'p $tpidruro'
Temporary breakpoint 1 at 0x512
Temporary breakpoint 1, 0xaaaaa512 in main ()
$1 = <unavailable>
Simon Marchi then clarified:
> The only time we should be seeing some "unavailable" registers or memory
> is in the context of tracepoints, for things that are not collected.
> Seeing an unavailable register here is a sign that something is not
> right.
Therefore, disable the TLS feature in aarch32 target descriptions for Linux
and NetBSD targets (the latter also doesn't seem to support accessing
tpidruro either, based on a quick look at arm-netbsd-nat.c).
This patch fixes the following tests:
Running gdb.base/inline-frame-cycle-unwind.exp ...
FAIL: gdb.base/inline-frame-cycle-unwind.exp: cycle at level 3: backtrace when the unwind is broken at frame 3
FAIL: gdb.base/inline-frame-cycle-unwind.exp: cycle at level 5: backtrace when the unwind is broken at frame 5
FAIL: gdb.base/inline-frame-cycle-unwind.exp: cycle at level 1: backtrace when the unwind is broken at frame 1
Tested with Ubuntu 22.04.3 on armv8l-linux-gnueabihf in native,
native-gdbserver and native-extended-gdbserver targets with no regressions.
PR tdep/31418
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31418
Approved-By: John Baldwin <jhb@FreeBSD.org>
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* elfxx-x86.h: Add ATTRIBUTE_HIDDEN to internal functions.
* libbfd-in.h (_bfd_get_link_info): Add ATTRIBUTE_HIDDEN.
* libbfd.h: Regenerated.
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PR 21739
cpu/
* mep.opc (parse_lo16, parse_unsigned7): Mark %function
message as no-c-format.
opcodes/
* mep-asm.c: Regenerate.
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Only relocation handling for now; relaxation is not implemented yet.
bfd/
* elfnn-riscv.c (riscv_elf_check_relocs): Record GOT reference and
paired relocation for TLSDESC_HI20.
(riscv_elf_adjust_dynamic_symbol): Allocate GOT and reloc slots for
TLSDESC symbols.
(riscv_elf_size_dynamic_sections): Likewise but for local symbols.
(tlsdescoff): New helper to determine static addend for R_TLSDESC.
(riscv_elf_relocate_section): Ignore TLSDESC_CALL reloc for now (it is
relaxation only).
Handle TLSDESC_{LOAD,ADD}_LO12 as paired pcrel relocs.
For TLS GOT slot generation, generalize the logic to handle any
combination of (GD, IE, TLSDESC).
Add TLSDESC Rela generation.
* ld/testsuite/ld-riscv-elf/tls*: Add TLSDESC instruction sequences
next to the existing GD and IE sequences. Update expectations.
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As the size calculation is split by global and local symbols, using a
shared constant definition for its size improves clarity.
bfd/
* elfnn-riscv.c: Add macros for sizes of a normal GOT entry, TLS GD and
TLS IE entry.
(allocate_dynrelocs): Replace GOT size expressions with the new
constants.
(riscv_elf_size_dynamic_sections): Likewise.
(riscv_elf_relocate_section): Likewise.
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gas/
* tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi,
%tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype
renamed to percent_op_relax_only as this matcher is extended to handle
jalr as well which is not R-type.
(riscv_ip): Apply the percent_op_relax_only rename and update comment.
(md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to
TLS relocation check list.
* testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation
generation.
opcodes/
* riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with
%tlsdesc_call annotations.
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bfd/
* elfxx-riscv.c: Add 5 TLSDESC reloc descriptions.
* reloc.c: Likewise.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
include/
* elf/riscv.h: Add 5 TLSDESC reloc descriptions.
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Change the statement "use bignum" to "use bigint". This is sufficient
for gp-display-html to work and removes the dependency on bignum.
gprofng/ChangeLog
2024-02-27 Ruud van der Pas <ruud.vanderpas@oracle.com>
PR 31390
* gprofng/gp-display-html: One line change to "use bigint".
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No functional change
Approved-By: Simon Marchi <simon.marchi@efficios.com>
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