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When i386 glibc was assembled with commit:
commit 11c2852449825a5f486f63bc40aabed56b7c04c1 (HEAD)
Author: Jan Beulich <jbeulich@suse.com>
Date: Fri Feb 21 10:24:50 2025 +0100
x86: widen @got{,pcrel} support to PUSH and APX IMUL
With us doing the transformation to an immediate operand for MOV and
various ALU insns, there's little reason to then not support the same
conversion for the other two insns which have respective immediate
operand forms. Unfortunately for IMUL (due to the 0F opcode prefix)
there's no suitable relocation, so the pre-APX forms cannot be marked
for relaxation in the assembler.
"pushl main@GOT(%ebx)" in sysdeps/i386/start.S was assembled to
1c: ff b3 00 00 00 00 push 0x0(%ebx) 1e: R_386_GOT32X main
Linkers in binutils versions older than 2.45 treated it as jmp and relaxed
it to
22c: e9 cf ff ff ff jmp 200 <main>
231: 90 nop
Update elf_i386_convert_load_reloc in binutils versions older than 2.45
to check MODRM for call and jmp to work with i386 glibc assembled with
binutils 2.45 or newer. Do the same in elf_x86_64_convert_load_reloc.
PR ld/32991
* elf32-i386.c (elf_i386_convert_load_reloc): Check MODRM for
call and jmp.
* elf64-x86-64.c (elf_x86_64_convert_load_reloc): Likewise.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
(cherry picked from commit 452f5511154ca02095a271cf085e17f536587207)
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So far IBM z17 was identified as arch15. Add the real name, as it has
been announced. [1]
[1]: IBM z17 announcement letter, AD25-0015,
https://www.ibm.com/docs/en/announcements/z17-makes-more-possible
gas/
* config/tc-s390.c (s390_parse_cpu): Add z17 as alternate CPU
name for arch15.
* doc/c-s390.texi: Likewise.
* doc/as.texi: Likewise.
opcodes/
* s390-mkopc.c (main): Add z17 as alternate CPU name for arch15.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit 981fe5fd80faf511aa265e841a380c9b46be30e6)
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For the instructions of R_LARCH_B16/B21, if the immediate overflow,
add a B instruction and R_LARCH_B26 relocation.
For example:
.L1
...
blt $t0, $t1, .L1
R_LARCH_B16
change to:
.L1
...
bge $t0, $t1, .L2
b .L1
R_LARCH_B26
.L2
(cherry picked from commit 1fb3cdd87ec61715a5684925fb6d6a6cf53bb97c)
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opcodes/
* s390-opc.txt: Add arch15 Concurrent-Functions Facility
instructions.
* s390-opc.c (INSTR_SSF_RRDRD2, MASK_SSF_RRDRD2): New SSF
instruction format variant.
gas/testsuite/
* gas/s390/zarch-arch15.d: Tests for arch15 Concurrent-Functions
Facility instructions.
* gas/s390/zarch-arch15.s: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit 76445f36a2f9e41b1744d0327e7ec243cb7fac12)
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opcodes/
* s390-opc.txt: Add arch15 instruction names.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit b0588b2173bf9aeff9eadc0cc024c4c69e69114d)
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If we generate an object file using an assembler with the new
relocations added, and then linking those files with an older
linker, the link will still complete and the linked file will
be generated.
In this case we should report an error instead of continuing
the linking process.
(cherry picked from commit 5966e2eb3fed61ebe5c091a074b368b9238a68c1)
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The md_pre_output_hook creating fixup is asynchronous, causing relocs
may be out of order in .eh_frame. Define GAS_SORT_RELOCS so that reorder
relocs when write_relocs.
Reported-by: Rui Ueyama <rui314@gmail.com>
(cherry picked from commit 7c93730fe50c22129e751d8479e64bc970b75aac)
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opcodes/
* s390-mkopc.c (main) Accept arch15 as CPU string.
* s390-opc.txt: Add arch15 instructions.
include/
* opcode/s390.h (enum s390_opcode_cpu_val): Add
S390_OPCODE_ARCH15.
gas/
* config/tc-s390.c (s390_parse_cpu): New entry for arch15.
* doc/c-s390.texi: Document arch15 march option.
* doc/as.texi: Likewise.
* testsuite/gas/s390/s390.exp: Run the arch15 related tests.
* testsuite/gas/s390/zarch-arch15.d: Tests for arch15
instructions.
* testsuite/gas/s390/zarch-arch15.s: Likewise.
Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com>
Reviewed-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit a98a6fa2d8ef5eb61534b07db80850dcdf07bdb4)
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This leverages commit ("s390: Simplify (dis)assembly of insn operands
with const bits") to relax the operand constraints of the immediate
operand that contains the constant Z- or T-bit of the following extended
mnemonics:
risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt
Previously those instructions were the only ones where the assembler
on s390 restricted the specification of the subject I3/I4 operand values
exactly according to their specification to an unsigned 6- or 5-bit
unsigned integer. For any other instructions the assembler allows to
specify any operand value allowed by the instruction format, regardless
of whether the instruction specification is more restrictive.
Allow to specify the subject I3/I4 operand as unsigned 8-bit integer
with the constant operand bits being ORed during assembly.
Relax the instructions subject significant operand bit masks to only
consider the Z/T-bit as significant, so that the instructions get
disassembled as their *z or *t flavor regardless of whether any reserved
bits are set in addition to the Z/T-bit.
Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set
the T-bit in operand I3, as they otherwise get disassembled as their
rnsbgt, rosbgt, and rxsbgt counterpart.
This aligns GNU Assembler to LLVM Assembler.
opcodes/
* s390-opc.c (U6_18, U5_27, U6_26): Remove.
(INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define
as INSTR_RIE_RRUUU while retaining insn fmt mask.
(MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only
Z/T-bit of I3/I4 operand as significant.
gas/testsuite/
* gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit.
Reported-by: Dominik Steenken <dost@de.ibm.com>
Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit b8b60e2d0cb0ab1f235f082dbb8a4e8bc43aadf6)
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Simplify assembly and disassembly of extended mnemonics with operands
with constant ORed bits:
Their instruction template already contains the respective constant
operand bits, as they are significant to distinguish the extended from
their base mnemonic. Operands are ORed into the instruction template.
Therefore it is not necessary to OR the constant bits into the operand
value during assembly in s390_insert_operand.
Additionally the constant operand bits from the instruction template
can be used to mask them from the operand value during disassembly in
s390_print_insn_with_opcode. For now do so for non-length unsigned
integer operands only.
The separate instruction formats need to be retained, as their masks
differ, which is relevant during disassembly to distinguish the base
and extended mnemonics from each other.
This affects the following extended mnemonics:
- vfaebs, vfaehs, vfaefs
- vfaezb, vfaezh, vfaezf
- vfaezbs, vfaezhs, vfaezfs
- vstrcbs, vstrchs, vstrcfs
- vstrczb, vstrczh, vstrczf
- vstrczbs, vstrczhs, vstrczfs
- wcefb, wcdgb
- wcelfb, wcdlgb
- wcfeb, wcgdb
- wclfeb, wclgdb
- wfisb, wfidb, wfixb
- wledb, wflrd, wflrx
include/
* opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2,
S390_OPERAND_OR8): Remove.
opcodes/
* s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove.
(INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define
as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask.
(INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining
respective insn fmt mask.
(INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3):
Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt
mask.
* s390-dis.c (s390_print_insn_with_opcode): Mask constant
operand bits set in insn template of non-length unsigned
integer operands.
gas/
* config/tc-s390.c (s390_insert_operand): Do not OR constant
operand value bits.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit a3f1e7c56a60573562e8578ae8b675ec1f4448e7)
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opcodes/
* s390-opc.txt (rdp): Change opcode to lower-case.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit 1afe02759f1569fb647b691d308c95efc2116b23)
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Provide descriptions for instructions introduced with commit ba2b480f103
("IBM Z: Implement instruction set extensions"). This complements commit
69341966def ("IBM zSystems: Add support for z16 as CPU name."). Use
instruction names from IBM z/Architecture Principles of Operation [1] as
instruction description.
[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
opcodes/
* s390-opc.txt: Add descriptions for IBM z16 (arch14)
instructions.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
(cherry picked from commit 2ff609b4ce8f3142b4e5592116f28c83a07066c3)
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Change the bitwise operations names "and" and "or" to lower case. Change
the register name abbreviations "FPR", "GR", and "VR" to upper case.
opcodes/
* s390-opc.txt: Align letter case of instruction descriptions.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
(cherry picked from commit 8e194ff8cced7cd3924353d39706bd6656d654e2)
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(cherry picked from commit 6c0c7d489bdf106d90b300aeb8d042c7b1ad3d2b)
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IBM z13 (arch11) introduced ppno (Perform Pseudorandom Number Operation).
IBM z14 (arch12) introduced prno (Perform Random Number Operation) and
deprecated ppno.
opcodes/
* s390-opc.txt: Correct prno instruction name.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
(cherry picked from commit 6e1d1b2e7b2e12e53fa287387fbbca9c56dc29d0)
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Add extended mnemonics specified in the z/Architecture Principles of
Operation [1] and z/Architecture Reference Summary [2], that were
previously missing from the opcode table.
The following added extended mnemonics are synonyms to a base mnemonic
and therefore disassemble into their base mnemonic:
jc, jcth, lfi, llgfi, llghi
The following added extended mnemonics are more specific than their base
mnemonic and therefore disassemble into the added extended mnemonic:
risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt
The following added extended mnemonics are more specific than their base
mnemonic, but disassemble into their base mnemonic due to design
constraints:
notr, notgr
The missing extended mnemonic jl* conditional jump long flavors cannot
be added, as they would clash with the existing non-standard extended
mnemonic j* conditional jump flavors jle and jlh. The missing extended
mnemonic jlc jump long conditional is not added, as the related jl*
flavors cannot be added.
Note that these missing jl* conditional jump long flavors are already
defined as non-standard jg* flavors instead. While the related missing
extended mnemonic jlc could be added as non-standard jgc instead it is
forgone in favor of not adding further non-standard mnemonics.
The missing extended mnemonics sllhh, sllhl, slllh, srlhh, srlhl, and
srllh cannot be implemented using the current design, as they require
computed operands. For that reason the following missing extended
mnemonics are not added as well, as they fall into the same category of
instructions that operate on high and low words of registers. They
should better be added together, not to confuse the user, which of those
instructions are currently implemented or not.
lhhr, lhlr, llhfr, llchhr, llchlr, llclhr, llhhhr, llhhlr, llhlhr,
nhhr, nhlr, nlhr, ohhr, ohlr, olhr, xhhr, xhlr, xlhr
[1] IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
[2] IBM z/Architecture Reference Summary, SA22-7871-11,
https://www.ibm.com/support/pages/sites/default/files/2022-09/SA22-7871-11.pdf
opcodes/
* s390-opc.c: Define operand formats R_CP16_28, U6_18, and
U5_27. Define instruction formats RIE_RRUUU3, RIE_RRUUU4,
and RRF_R0RR4.
* s390-opc.txt: Add extended mnemonics jc, jcth, lfi, llgfi,
llghi, notgr, notr, risbhgz, risblgz, rnsbgt, rosbgt, and
rxsbgt.
gas/
* config/tc-s390.c: Add support to insert operand for format
R_CP16_28, reusing existing logic for format V_CP16_12.
* testsuite/gas/s390/esa-g5.s: Add test for extended mnemonic
jc.
* testsuite/gas/s390/esa-g5.d: Likewise.
* testsuite/gas/s390/zarch-z900.s: Add test for extended
mnemonic llghi.
* testsuite/gas/s390/zarch-z900.d: Likewise.
* testsuite/gas/s390/zarch-z9-109.s: Add tests for extended
mnemonics lfi and llgfi.
* testsuite/gas/s390/zarch-z9-109.d: Likewise.
* testsuite/gas/s390/zarch-z10.s: Add tests for extended
mnemonics rnsbgt, rosbgt, and rxsbgt.
* testsuite/gas/s390/zarch-z10.d: Likewise.
* testsuite/gas/s390/zarch-z196.s: Add tests for extended
mnemonics jcth, risbhgz, and risblgz.
* testsuite/gas/s390/zarch-z196.d: Likewise.
* testsuite/gas/s390/zarch-arch13.s: Add tests for extended
mnemonics notr and notgr.
* testsuite/gas/s390/zarch-arch13.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
(cherry picked from commit 2bf1f788bd7941375af27741715af645faa1cee6)
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The IBM z/Architecture Principle of Operation [1] specifies the last
operand(s) of some (extended) mnemonics to be optional. Align the
mnemonic definitions in the opcode table according to specification.
This changes the last operand of the following (extended) mnemonics to
be optional:
risbg, risbgz, risbgn, risbgnz, risbhg, risblg, rnsbg, rosbg, rxsbg
Note that efpc and sfpc actually have only one operand, but had
erroneously been defined to have two. For backwards compatibility the
wrong RR register format must be retained. Since the superfluous second
operand is defined as optional the instruction can still be coded as
specified.
[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
opcodes/
* s390-opc.txt: Align optional operand definition to
specification.
testsuite/
* zarch-z10.s: Add test cases for risbg, risbgz, rnsbg, rosbg,
and rxsbg.
* zarch-z10.d: Likewise.
* zarch-z196.s: Add test cases for risbhg and risblg.
* zarch-z196.d: Likewise.
* zarch-zEC12.s: Add test cases for risbgn and risbgnz.
* zarch-zEC12.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
(cherry picked from commit fca086d928a940dc5aa3b5c0586bc5ed37d6b374)
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This is a purely mechanical change. It allows subsequent insertions into
the operands table without having to renumber all operand indices.
The only differences in the resulting ELF object are in the .debug_info
section. This has been confirmed by diffing the following xxd and readelf
output:
xxd s390-opc.o
readelf -aW -x .text -x .data -x .bss -x .rodata -x .debug_info \
-x .symtab -x .strtab -x .shstrtab --debug-dump s390-opc.o
opcodes/
* s390-opc.c: Make operand table indices relative to each other.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
(cherry picked from commit eeafc61979c6f8399bb5ce770e46a00823a5cfae)
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The ESA opcode test cases for IBM z900 contain a few edge cases. They
exercise the brasl mnemonic with its largest allowed negative and
positive offsets. Linux on zSeries in ESA mode executes in 31-bit
addressing mode. Therefore the ESA test cases are assembled with -m31.
In 31-bit addressing mode the address computation using those large
offsets wraps, which is correctly reflected in the disassembly.
Linux on Z in z/Architecture mode executes in 64-bit addressing mode.
Therefore the z/Architecture (zarch) test cases are assembled with -m64.
In 64-bit addressing mode the address computation using those large
offsets does not necessarily wrap.
gas/
* testsuite/gas/s390/zarch-z900.s: Add brasl tests from ESA that
exercise edge cases.
* testsuite/gas/s390/zarch-z900.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
(cherry picked from commit 3f3c1e513bdf53d78adbde7f9d300c2281de21b9)
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Opcode test cases for z/Architecture instructions that use relative
addressing contained hardcoded offsets in the test verification
patterns. Inserting or reordering of instructions into those test cases
therefore required updating of those hardcoded offsets.
Use regular expressions with backreferences to verify results of test
cases containing instructions with relative addressing. This makes the
verification position independent.
gas/
* testsuite/gas/s390/esa-g5.d: Make opcode test verification
pattern position independent where possible.
* testsuite/gas/s390/esa-z900.d: Likewise.
* testsuite/gas/s390/zarch-z900.d: Likewise.
* testsuite/gas/s390/zarch-z10.d: Likewise.
* testsuite/gas/s390/zarch-z196.d: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
(cherry picked from commit 9c422a59953cd6b64bc8ed5f3d6e72a180f13540)
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A bug in ctf_dtd_delete led to refs in the string table to the
names of non-root-visible types not being removed when the DTD
was. This seems harmless, but actually it would lead to a write
down a pointer into freed memory if such a type was ctf_rollback()ed
over and then the dict was serialized (updating all the refs as the
strtab was serialized in turn).
Bug introduced in commit fe4c2d55634c700ba527ac4183e05c66e9f93c62
("libctf: create: non-root-visible types should not appear in name tables")
which is included in binutils 2.35.
libctf/
* ctf-create.c (ctf_dtd_delete): Remove refs for all types
with names, not just root-visible ones.
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The as and ld use _bfd_error_handler to output error messages when
checking relocation alignment and relocation overflow. However, the
abfd value passed by as to the function is NULL, resulting in an
internal error. The ld passes a non-null value to the function,
so it can output an error message normally.
(cherry picked from commit f87cf663af71e5d78c8d647fa48562102f3b0615)
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binutils/
* doc/binutils.texi (PowerPC -M option): Mention power11 and pwr11.
gas/
* config/tc-ppc.c: (md_show_usage): Mention -mpower11 and -mpwr11.
* doc/c-ppc.texi: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power11" and "pwr11" entries.
(powerpc_init_dialect): Default to "power11".
(cherry picked from commit 4199cf1e152daab0460f08cc7dbd1f727ac3e4cc)
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1. .so relaxation testcase
2. ld --no-relax testcase
3. segment alignment testcase
(cherry picked from commit 580a53dab47c9e4f97c8559440d2bc43fb7331b6)
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The first pass handles R_LARCH_RELAX relocations, the second pass
handles R_LARCH_ALIGN relocations.
(cherry picked from commit 8338aecd231af48483e36c93c103db1da715ac74)
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Previously the condition prevented shared objects from being relaxed.
To remove the limitation, we need to update program header size and
.eh_frame_hdr size before relaxation.
(cherry picked from commit 4f2469d0cdd0f3bd1d9040521e002e8df0a63a98)
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If deleting instructions in one relax_trip, set again to true to start the
next relax_trip.
(cherry picked from commit b130a0849a1b3e174210903cf5370092decc62d6)
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Directly delete relaxed instuctions in first relaxation pass, not use
R_LARCH_DELETE relocation. If not, the PC-relative offset may increase.
(cherry picked from commit 4e94082d95e046f357409cd689ffeedd60f6c673)
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When calling ld with --no-relax, pcalau12i + ld.d still can be relaxed.
This patch fix this bug and pcalau12i + ld.d can be relaxed with --relax.
(cherry picked from commit 363174776d13db9f35f2e54d8f7f5e34b64acbee)
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Before running our tests, we made a fake installation into ./tmpdir.
This installation changes libopcodes.la in the build area.
Gas testing may fail if gas and gprofng tests are run in parallel.
I create a script to run gprofng. Inside this script, LD_LIBRARY_PATH,
GPROFNG_SYSCONFDIR are set.
putenv_libcollector_ld_misc() first uses $GPROFNG_PRELOAD_LIBDIRS to create
directories for SP_COLLECTOR_LIBRARY_PATH ($SP_COLLECTOR_LIBRARY_PATH is used
to set up LD_PRELOAD).
gprofng/ChangeLog
2024-01-19 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
PR gprofng/31252
PR gprofng/30808
* src/envsets.cc (putenv_libcollector_ld_misc): Use
$GPROFNG_PRELOAD_LIBDIRS first to build SP_COLLECTOR_LIBRARY_PATH.
* testsuite/config/default.exp: Create a script to run gprofng.
* testsuite/lib/display-lib.exp: Fix typo.
(cherry picked from commit 26f557af696726a8556bff12f54e4d05cd7a5034)
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