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-rw-r--r--opcodes/aarch64-asm-2.c119
-rw-r--r--opcodes/aarch64-dis-2.c200
-rw-r--r--opcodes/aarch64-opc-2.c3
-rw-r--r--opcodes/aarch64-opc.c20
-rw-r--r--opcodes/aarch64-opc.h4
-rw-r--r--opcodes/aarch64-tbl.h36
6 files changed, 252 insertions, 130 deletions
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 77dcc9a..a4b02cd 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -675,21 +675,21 @@ aarch64_insert_operand (const aarch64_operand *self,
case 222:
case 223:
case 224:
- case 232:
- case 236:
- case 240:
- case 247:
- case 248:
- case 255:
- case 256:
- case 257:
+ case 235:
+ case 239:
+ case 243:
+ case 250:
+ case 251:
case 258:
+ case 259:
+ case 260:
+ case 261:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 118:
case 119:
- case 290:
- case 292:
+ case 293:
+ case 295:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -703,16 +703,16 @@ aarch64_insert_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
- case 294:
+ case 297:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 39:
case 40:
case 41:
- case 259:
- case 260:
- case 275:
- case 276:
- case 277:
+ case 225:
+ case 226:
+ case 229:
+ case 262:
+ case 263:
case 278:
case 279:
case 280:
@@ -723,6 +723,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 285:
case 286:
case 287:
+ case 288:
+ case 289:
+ case 290:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 42:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -770,13 +773,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 205:
case 206:
case 207:
- case 261:
- case 288:
- case 289:
+ case 264:
case 291:
- case 293:
- case 298:
- case 299:
+ case 292:
+ case 294:
+ case 296:
+ case 301:
+ case 302:
return aarch64_ins_imm (self, info, code, inst, errors);
case 51:
case 52:
@@ -924,7 +927,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 197:
case 198:
case 199:
- case 274:
+ case 277:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 212:
case 213:
@@ -936,69 +939,69 @@ aarch64_insert_operand (const aarch64_operand *self,
case 218:
case 219:
return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
- case 225:
- case 226:
case 227:
case 228:
- case 229:
case 230:
case 231:
- return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 232:
case 233:
- return aarch64_ins_sve_index_imm (self, info, code, inst, errors);
case 234:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
- case 235:
+ return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 236:
+ return aarch64_ins_sve_index_imm (self, info, code, inst, errors);
case 237:
- case 254:
- case 300:
- case 301:
- case 302:
- return aarch64_ins_sve_reglist (self, info, code, inst, errors);
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
case 238:
- case 239:
+ case 240:
+ case 257:
+ case 303:
+ case 304:
+ case 305:
+ return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 241:
case 242:
- case 243:
case 244:
- case 253:
- return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 245:
case 246:
- return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
+ case 247:
+ case 256:
+ return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
+ case 248:
case 249:
- case 251:
- case 262:
- return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
- case 250:
+ return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
case 252:
- return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 263:
- case 264:
+ case 254:
case 265:
+ return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 253:
+ case 255:
+ return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 266:
case 267:
case 268:
case 269:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 270:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 271:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 272:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 273:
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ case 274:
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ case 275:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 276:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 295:
- case 296:
- case 297:
+ case 298:
+ case 299:
+ case 300:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 303:
- case 304:
- case 305:
case 306:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 307:
+ case 308:
+ case 309:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 310:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index ef51a9b..35501d6 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20059,32 +20059,87 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 31) & 0x1) == 0)
+ if (((word >> 10) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x1x01xxxxx101xxxxxxxxxxxxx
- histseg. */
- return 2154;
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101000xxxxxxxxxx
+ histseg. */
+ return 2154;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101100xxxxxxxxxx
+ luti2. */
+ return 3388;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101x10xxxxxxxxxx
+ luti2. */
+ return 3389;
+ }
}
else
{
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101001xxxxxxxxxx
+ luti4. */
+ return 3390;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101101xxxxxxxxxx
+ luti4. */
+ return 3391;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101x11xxxxxxxxxx
+ luti4. */
+ return 3392;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
/* 33222222222211111111110000000000
10987654321098765432109876543210
110001x1x01xxxxx101xxxxxxxxxxxxx
ldff1sw. */
return 1751;
}
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x1x11xxxxx101xxxxxxxxxxxxx
- ldff1sw. */
- return 1750;
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 110001x1x11xxxxx101xxxxxxxxxxxxx
+ ldff1sw. */
+ return 1750;
+ }
}
}
}
@@ -33617,21 +33672,21 @@ aarch64_extract_operand (const aarch64_operand *self,
case 222:
case 223:
case 224:
- case 232:
- case 236:
- case 240:
- case 247:
- case 248:
- case 255:
- case 256:
- case 257:
+ case 235:
+ case 239:
+ case 243:
+ case 250:
+ case 251:
case 258:
+ case 259:
+ case 260:
+ case 261:
return aarch64_ext_regno (self, info, code, inst, errors);
case 6:
case 118:
case 119:
- case 290:
- case 292:
+ case 293:
+ case 295:
return aarch64_ext_none (self, info, code, inst, errors);
case 11:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -33650,16 +33705,16 @@ aarch64_extract_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
- case 294:
+ case 297:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 39:
case 40:
case 41:
- case 259:
- case 260:
- case 275:
- case 276:
- case 277:
+ case 225:
+ case 226:
+ case 229:
+ case 262:
+ case 263:
case 278:
case 279:
case 280:
@@ -33670,6 +33725,9 @@ aarch64_extract_operand (const aarch64_operand *self,
case 285:
case 286:
case 287:
+ case 288:
+ case 289:
+ case 290:
return aarch64_ext_simple_index (self, info, code, inst, errors);
case 42:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -33718,13 +33776,13 @@ aarch64_extract_operand (const aarch64_operand *self,
case 205:
case 206:
case 207:
- case 261:
- case 288:
- case 289:
+ case 264:
case 291:
- case 293:
- case 298:
- case 299:
+ case 292:
+ case 294:
+ case 296:
+ case 301:
+ case 302:
return aarch64_ext_imm (self, info, code, inst, errors);
case 51:
case 52:
@@ -33874,7 +33932,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 197:
case 198:
case 199:
- case 274:
+ case 277:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
case 212:
case 213:
@@ -33886,70 +33944,70 @@ aarch64_extract_operand (const aarch64_operand *self,
case 218:
case 219:
return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors);
- case 225:
- case 226:
case 227:
case 228:
- case 229:
case 230:
case 231:
- return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
+ case 232:
case 233:
- return aarch64_ext_sve_index_imm (self, info, code, inst, errors);
case 234:
- return aarch64_ext_sve_index (self, info, code, inst, errors);
- case 235:
+ return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
+ case 236:
+ return aarch64_ext_sve_index_imm (self, info, code, inst, errors);
case 237:
- case 254:
- return aarch64_ext_sve_reglist (self, info, code, inst, errors);
+ return aarch64_ext_sve_index (self, info, code, inst, errors);
case 238:
- case 239:
+ case 240:
+ case 257:
+ return aarch64_ext_sve_reglist (self, info, code, inst, errors);
case 241:
case 242:
- case 243:
case 244:
- case 253:
- return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
case 245:
case 246:
- return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
+ case 247:
+ case 256:
+ return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
+ case 248:
case 249:
- case 251:
- case 262:
- return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
- case 250:
+ return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
case 252:
- return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 263:
- case 264:
+ case 254:
case 265:
+ return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 253:
+ case 255:
+ return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 266:
case 267:
case 268:
case 269:
- return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 270:
- return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 271:
- return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
case 272:
- return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 273:
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ case 274:
+ return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ case 275:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 276:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
- case 295:
- case 296:
- case 297:
- return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
+ case 298:
+ case 299:
case 300:
- case 301:
- case 302:
- return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
+ return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
case 303:
case 304:
case 305:
+ return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
case 306:
- return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 307:
+ case 308:
+ case 309:
+ return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 310:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 7962b0f..bd1aa4f 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -249,8 +249,11 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm1_23_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i1_23}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm2_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i2}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 84a3955..bbe6f09 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -294,10 +294,14 @@ const aarch64_field fields[] =
{ 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
{ 5, 1 }, /* SVE_i1: single-bit immediate. */
+ { 23, 1 }, /* SVE_i1_23: single-bit immediate. */
+ { 22, 2 }, /* SVE_i2: 2-bit index, bits [23,22]. */
{ 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
{ 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
+ { 22, 2 }, /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */
{ 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
+ { 12, 1 }, /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */
{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
@@ -1813,6 +1817,18 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return 0;
break;
+ case AARCH64_OPND_SVE_Zm1_23_INDEX:
+ size = get_operand_fields_width (get_operand_from_code (type));
+ if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 1))
+ return 0;
+ break;
+
+ case AARCH64_OPND_SVE_Zm2_22_INDEX:
+ size = get_operand_fields_width (get_operand_from_code (type));
+ if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 3))
+ return 0;
+ break;
+
case AARCH64_OPND_SVE_Zn_INDEX:
size = aarch64_get_qualifier_esize (opnd->qualifier);
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
@@ -1840,6 +1856,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return 0;
break;
+ case AARCH64_OPND_SVE_Zm3_12_INDEX:
case AARCH64_OPND_SME_Zn_INDEX1_16:
case AARCH64_OPND_SME_Zn_INDEX2_15:
case AARCH64_OPND_SME_Zn_INDEX2_16:
@@ -4194,9 +4211,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
print_register_list (buf, size, opnd, "z", styler);
break;
+ case AARCH64_OPND_SVE_Zm1_23_INDEX:
+ case AARCH64_OPND_SVE_Zm2_22_INDEX:
case AARCH64_OPND_SVE_Zm3_INDEX:
case AARCH64_OPND_SVE_Zm3_22_INDEX:
case AARCH64_OPND_SVE_Zm3_19_INDEX:
+ case AARCH64_OPND_SVE_Zm3_12_INDEX:
case AARCH64_OPND_SVE_Zm3_11_INDEX:
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 23e634f..8bf3fc8 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -104,10 +104,14 @@ enum aarch64_field_kind
FLD_SVE_Zn,
FLD_SVE_Zt,
FLD_SVE_i1,
+ FLD_SVE_i1_23,
+ FLD_SVE_i2,
FLD_SVE_i2h,
FLD_SVE_i3h,
FLD_SVE_i3h2,
+ FLD_SVE_i3h3,
FLD_SVE_i3l,
+ FLD_SVE_i3l2,
FLD_SVE_imm3,
FLD_SVE_imm4,
FLD_SVE_imm5,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 6b98a1b..1d12630 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1529,9 +1529,21 @@
{ \
QLF2(S_H,S_H), \
}
+/* e.g. luti2 <Zd>.B, { <Zn>.B }, <Zm>[index]. */
+/* The third operand is an index (e.g. immediate or bit)
+ without a type qualifier and is checked separately
+ based on operand enum. */
#define OP_SVE_BBU \
{ \
- QLF3(S_B,S_B,NIL), \
+ QLF3(S_B,S_B,NIL), \
+}
+/* e.g. luti2 <Zd>.H, { <Zn>.H }, <Zm>[index]. */
+/* The third operand is an index (e.g. immediate or bit)
+ without a type qualifier and is checked separately
+ based on operand enum. */
+#define OP_SVE_HHU \
+{ \
+ QLF3(S_H,S_H,NIL), \
}
#define OP_SVE_BBB \
{ \
@@ -2731,6 +2743,8 @@ static const aarch64_feature_set aarch64_feature_fp8_sme2 =
AARCH64_FEATURES (2, FP8, SME2);
static const aarch64_feature_set aarch64_feature_lut =
AARCH64_FEATURE (LUT);
+static const aarch64_feature_set aarch64_feature_lut_sve2 =
+ AARCH64_FEATURES (2, LUT, SVE2);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2806,6 +2820,7 @@ static const aarch64_feature_set aarch64_feature_lut =
#define FP8_SVE2 &aarch64_feature_fp8_sve2
#define FP8_SME2 &aarch64_feature_fp8_sme2
#define LUT &aarch64_feature_lut
+#define LUT_SVE2 &aarch64_feature_lut_sve2
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -3001,6 +3016,9 @@ static const aarch64_feature_set aarch64_feature_lut =
F_STRICT | FLAGS, 0, TIED, NULL }
#define LUT_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, lut, 0, LUT, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define LUT_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS,CONSTRAINTS) \
+ { NAME, OPCODE, MASK, lut, 0, LUT_SVE2, OPS, QUALS, \
+ FLAGS, CONSTRAINTS, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -6579,6 +6597,13 @@ const struct aarch64_opcode aarch64_opcode_table[] =
LUT_INSN ("luti4", 0x4e402000, 0xffe0bc00, OP3 (Vd, LVn_LUT, Em_INDEX1_14), QL_VVUB, F_OD(1)),
LUT_INSN ("luti4", 0x4e401000, 0xffe09c00, OP3 (Vd, LVn_LUT, Em_INDEX2_13), QL_VVUH, F_OD(2)),
+ /* SVE2 lut. */
+ LUT_SVE2_INSN ("luti2", 0x4520b000, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_BBU, F_OD(1), 0),
+ LUT_SVE2_INSN ("luti2", 0x4520a800, 0xff20ec00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm3_12_INDEX), OP_SVE_HHU, F_OD(1), 0),
+ LUT_SVE2_INSN ("luti4", 0x4560a400, 0xff60fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm1_23_INDEX), OP_SVE_BBU, F_OD(1), 0),
+ LUT_SVE2_INSN ("luti4", 0x4520b400, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(2), 0),
+ LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
@@ -7052,12 +7077,21 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an SVE vector register") \
Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \
"an SVE vector register") \
+ Y(SVE_REG, simple_index, "SVE_Zm1_23_INDEX", \
+ 0, F(FLD_SVE_Zm_16, FLD_SVE_i1_23), \
+ "an indexed SVE vector register") \
+ Y(SVE_REG, simple_index, "SVE_Zm2_22_INDEX", \
+ 0, F(FLD_SVE_Zm_16, FLD_SVE_i2), \
+ "an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
"an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \
"an indexed SVE vector register") \
+ Y(SVE_REG, simple_index, "SVE_Zm3_12_INDEX", \
+ 0, F(FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2), \
+ "an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm3_19_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_imm2_19, FLD_SVE_imm3), \
"an indexed SVE vector register") \
generated by cgit v1.1 at 2024-10-19 22:50:30 +0000