diff options
Diffstat (limited to 'opcodes/arm-dis.c')
| -rw-r--r-- | opcodes/arm-dis.c | 27 |
1 files changed, 16 insertions, 11 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index a30afb9..59a5978 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -503,6 +503,8 @@ static const struct opcode32 coprocessor_opcodes[] = 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), @@ -515,6 +517,8 @@ static const struct opcode32 coprocessor_opcodes[] = 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), @@ -902,6 +906,12 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"}, + /* Dot Product instructions in the space of coprocessor 13. */ + {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), + 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), + 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"}, + /* V5 coprocessor instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, @@ -2689,7 +2699,6 @@ static const struct opcode16 thumb_opcodes[] = %<bitfield>W print bitfield*4 in decimal %<bitfield>r print bitfield as an ARM register %<bitfield>R as %<>r but r15 is UNPREDICTABLE - %<bitfield>S as %<>R but r13 is UNPREDICTABLE %<bitfield>c print bitfield as a condition code %<bitfield>'c print specified char iff bitfield is all ones @@ -2757,17 +2766,17 @@ static const struct opcode32 thumb32_opcodes[] = /* CRC32 instructions. */ {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, + 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, + 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, + 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, + 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, + 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, + 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, /* V7 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, @@ -5977,10 +5986,6 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) value_in_comment = val * 4; break; - case 'S': - if (val == 13) - is_unpredictable = TRUE; - /* Fall through. */ case 'R': if (val == 15) is_unpredictable = TRUE; |