diff options
| -rw-r--r-- | gas/config/tc-aarch64.c | 1 | ||||
| -rw-r--r-- | gas/doc/c-aarch64.texi | 3 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
4 files changed, 10 insertions, 0 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 8141ea4..6b29683 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10363,6 +10363,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)}, {"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)}, {"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)}, + {"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 7a8da72..b18ca5a 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -280,6 +280,9 @@ automatically cause those extensions to be disabled. @tab Enable the SME2.1 Extension. @item @code{sve2p1} @tab N/A @tab No @tab Enable the SVE2.1 Extension. +@item @code{rcpc3} @tab Armv9.4-A @tab No + @tab Enable the rcpc3 additional Support for Release Consistency Model + Extension. This implies @code{rcpc2}. @end multitable @node AArch64 Syntax diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 6f86a98..7c0f7ce 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -226,6 +226,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME2p1, /* SVE2.1 instructions. */ AARCH64_FEATURE_SVE2p1, + /* RCPC3 instructions. */ + AARCH64_FEATURE_RCPC3, AARCH64_NUM_FEATURES }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 128cbf5..149265a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2647,6 +2647,9 @@ static const aarch64_feature_set aarch64_feature_sme2p1 = AARCH64_FEATURE (SME2p1); static const aarch64_feature_set aarch64_feature_sve2p1 = AARCH64_FEATURE (SVE2p1); +static const aarch64_feature_set aarch64_feature_rcpc3 = + AARCH64_FEATURE (RCPC3); + #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2712,6 +2715,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1 = #define B16B16 &aarch64_feature_b16b16 #define SME2p1 &aarch64_feature_sme2p1 #define SVE2p1 &aarch64_feature_sve2p1 +#define RCPC3 &aarch64_feature_rcpc3 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } |